JPH04188359A - Method activating multiprocessor system - Google Patents

Abstract

PURPOSE:To eliminate necessity for installing a dip switch by storing the respective won identification codes of processors to be successively activated in a storing means and identifying the number of the activated processors according to the number of the own identification codes. CONSTITUTION:One of plural processors 1-4 is activated, and one of the other processors 2-4 is activated by the activated processor 1. Then, the own recognition codes of the successively activated processors 1-4 are successively stored and according to the number of stored own recognition codes, the number of the activated processors 1-4 is identified. Thus, it is not necessary to install the dip switch, and the number of processors is automatically recognized.

Description

[Detailed Description of the Invention] Field of Application in the FA Industry] The present invention relates to a so-called multiprocessor system consisting of a plurality of processors, and is particularly concerned with the startup sequence of each processor when the power is turned on. The present invention relates to a method for starting a multiprocessor system that can recognize multiple processors without changing the hardware.

Background Art] Recently, multiprocessor systems using multiple processors have been developed.These multiprocessor systems are usually equipped with an operating system (O5) that supports multiprocessor processors. has been done. An operating system is the basic software that makes effective use of a computer's resources.

In the operating system of a multiprocessor system, it is necessary to recognize the number of processors and processor numbers when the power is turned on in order to appropriately distribute tasks to each processor.

FIG. 2 is a block diagram showing the configuration of an embodiment of a conventional multiprocessor system. The operation of each processor when power is turned on in a conventional multiprocessor system will be explained using the same figure.

1 in the diagram. 2. 3. 4 are each processors (
FIG. 2 shows a case where the number of processors is four.

), 5 is B configured with read-only memory.

otROM stores programs for each processor; 6 is a display control device for controlling the CRT 7; 8 is a main memory shared by each processor and used for storing work and data; 9 controls the hard disk 10. An auxiliary storage control device 11 is an input control device for controlling input devices such as a keyboard 12. A data storage device 14 is used to set the identification number of each processor and the number of processors.
15 is a reset signal 1 to each processor.
16 is a delay circuit for delaying the reset signal 17 for a predetermined time; 22 is a delay reset signal delayed by the delay circuit 16; is the processor's address and data bus.

In a conventional multiprocessor system configured as described above, the fifth
This will be explained with reference to flowchart 1 shown in the figure.

First, when the power is turned on, the reset signal of the processor is released. At this time, the other processors are reset, and no processors other than processor 0 are activated. Processor 1 whose reset has been released is BootR
Execute the boot program stored in OM5.

Then, the identification number of processor 1 (hereinafter referred to as ``Yori'') and the dip switch for setting the number of processors are read. As a result, the processor 1 recognizes its own ID and the number of processors. Here, processor l confirms that it is processor 1, which is the master, loads the main program stored in hard disk 10 onto main storage device 8, and executes it. Thereafter, the processor 1 activates a timer (f in the figure) and shifts to the Wait state. Delay circuit 16ζ It was set to release the reset of processors 2, 3, and 4 at exactly this time, and processors 2, 3, which were released from reset,
, 4 simultaneously execute the boot program stored in the 13oo tR○M5. This program is the same as that executed by processor 1. However, the deep switch for L ID confirmation is selected according to each processor. Processors 2, 3, and 4 recognize that they are not master processors, enter the Id1e state, and wait for instructions from the master processor. The timer activated by the processor 1 times out exactly at this time, and the next processing of the Main program continues. In this way, the initialization process when the power is turned on is completed. Here, the dip switch referred to by each processor must be set to a predetermined value before power is turned on.

[Problems to be Solved by the Invention] However, in the above conventional multiprocessor system, it is necessary to specially install a dip switch for setting the ID and a dip switch for setting the number of processors.
Furthermore, each time the number of processors changes, it is necessary to change the deep switch settings, which leads to switch setting errors and reduces reliability. In order to solve the problem, the present invention stores the self-identification code of each processor that is sequentially activated in a storage means, and identifies the number of activated processors based on the number of self-identification codes. By doing so, the number of processors can be determined by the data stored in the storage means.

[Embodiment] An apparatus using a method for starting a multiprocessor system according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an apparatus using a method for starting a multiprocessor system according to an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a device Bo shown in FIG.

This is a detailed diagram showing the circuit configuration of the tROM5 and address latch 13, and FIG. 4 is a detailed diagram showing the circuit configuration of the tROM5 and address latch 13.
This is a memory map showing the memory contents of OM5.
and FIG. 7 are flowcharts of the operations of each processor when the power is turned on. The operation of each processor at power-on of a multiprocessor system according to an embodiment of the present invention will be described with reference to the above diagram.

1 in Figure 1. 2, 3, and 4 are processors (the first
The figure shows a case where the number of processors is four. ), 5
6 is a Boot ROM consisting of a read-only memory, in which programs for each processor 1 to 4 are stored; 6 is a display control device 8 for controlling the CRT 7, which is shared by each processor 1 to 4 and stores data and programs for each processor. 9 is an auxiliary storage control device for controlling the hard disk IO. 11 is a human power control device for controlling input devices such as the keyboard 12. 13 is an address supplied to the BootROM 5. 15, a reset circuit 18 for supplying a reset signal 17 to each processor, a HALT output signal of the processor 1, which is the first processor; 19. 20. 21
are the HALT output signals of the processors 2, 3, and 4, and 23 is the address/data bus of the processors.

3, 24 is an address signal supplied to the BootROM 5, 25 is a data signal supplied to the BootROM 5, and 26 is an address latch signal for changing the output of the address latch 13, which is connected to the output of the address latch 13 and the processor. The BootROM is accessed based on the output address 24, and 27 is the BootRO
M5 chip enable signal, 28 is BootROM
This is the output enable signal of No. 5.

Regarding the multiprocessor system configured as described above, a method of starting each processor when the power is turned on will be described below. The explanation will proceed with reference to the flowchart shown in Fig. 6 @ Fig. 7.

After a predetermined period of time after the power is turned on, the reset signal 17 is released and the processor 1 is activated. At this time, processor 1 is in the HALT state, and processor 1 has BootROM 5
A first program for the processor 1 stored in the processor 1 is executed.

The specific access area and access method of the Boot ROM 5 at this time will be explained using FIGS. 3 and 4. Third Compendy B shown in Figure 4.

OtROM5 is a ROM with a capacity of 256 Kbit. When the power is turned on, the reset signal 17 becomes active and the output of the address latch 13 becomes ``0''. Assuming that processor 0 is executed from address 24 of 0000H (hexadecimal), the area accessed in the BootROMs is the area where the first program is stored. At this time, the ROM chip enable signal 27 and the ROM
Output enable signal 28 is generated by a decoder (not shown). If the latch signal 26 is activated and the output of the address latch 13 is set to "I I+," the area to be accessed becomes the area where the second program is stored.
is accessed.

The explanation of the flowcharts in FIGS. 6 and 7 will be continued.

The processor 1 running the first program checks the main memory 8 and peripheral devices.
The main storage device 8 is cleared. Then, data ``''bit'' is written to the ID area on the main storage device. At this time, processor 1 is operating as a master processor. Next, processor 1 writes the main program stored in hard disk 10. is loaded into the main memory 8. The processor l starts executing the M a i n program and outputs the address latch signal 26. After that, the H
A. Release LT output signal 1B. At this point, processor 2 starts up, processor 1 starts up a timer (not shown), and shifts to a Wait state. Processor 2, which has failed to start up, is forced to access BootROM 5. Since the output of address latch 13 has been changed to "1", the area accessed by processor 2 stores the second program. The processor 2 executes the second program and the main memory 8
Check the ID area and add 1 to the contents of the ID area to find out your ID. And that own I
Write D in the ID area again. In this way, the processor 1 recognizes its own ID (in this case, [ID area contents] -1-1= ] + 1 = 2). Thereafter, the HALT output signal 19 connected to the HALT input signal of the processor 3 is released, and the processor 3 enters the Idle state and waits for instructions. Processor 3 is activated here, and thereafter the second program is executed in all processors, and the same processing as processor 2 is performed. In this way, each processor can know its own ID. When all processors have started and completed processing, the timer started by processor 1 times out. Here, processor 1 checks the contents of the ID area of main memory 8 and recognizes the number of processors (in this case, it is 4).

At this point, the preprocessing for power-on is completed, and processor 1
continues with the next step in the M a i program.

As described above, according to this embodiment ('L), it is possible to uniquely determine the order in which the processors are activated when the power is turned on, and to differentiate between the programs executed by the master processor and the programs executed by other processors. In addition, each processor can recognize its own ID in the process of executing the program, and the master processor stores the ID area written by each processor in the main memory. By checking the value, you can easily get an idea of the number of processors.

Effects of the Invention This invention (I) It is possible to uniquely determine the startup order of multiple processors when the power is turned on, and each processor can be assigned its own ID by software, regardless of external settings such as dip switches. Moreover, even if the number of processors differs, it is possible to start up an excellent multiprocessor system that can automatically recognize the number of processors without changing the hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a device using a method for starting a multiprocessor system according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a multiprocessor system in a conventional example. Boo shown in
Figure 4 shows the detailed circuit configuration of the tROM 5 and address latch 13. The memory configuration shown in Figure 5 shows the memory contents of the Boot ROM 5 shown in Figure 1 (a>(b)).
6 is a flowchart showing the processing procedure when the multiprocessor system is powered on in a conventional example, and FIG. 6 is a flowchart showing the processing procedure when the multiprocessor system is powered on according to an embodiment of the present invention. 1 to 4...Processor, 5...BootROM,
8... Main memory device 9... Auxiliary memory control device 10... Hard disk drive 11... Input control device 12... Keyboard mi 13... Address latch 15... Reset circuit

Claims (1)

[Claims] 1) Activate one of the plurality of processors, activate another processor by the activated processor, sequentially store self-recognition codes of the sequentially activated processors, and store self-recognition codes of the sequentially activated processors; A method for starting a multiprocessor system, characterized in that the number of activated processors is identified based on the number of recognition codes. 2) Claim 1, wherein the plurality of processors write self-recognition codes to predetermined addresses in a main memory.
How to start a multiprocessor system as described. 3) The method of starting a multiprocessor system according to claim 1, wherein the identification number of each processor is a value obtained by adding 1 to the identification number of the processor that was started immediately before.