JPH04187793A - Semiconductor device and its production - Google Patents

Semiconductor device and its production

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Publication number
JPH04187793A
JPH04187793A JP31561190A JP31561190A JPH04187793A JP H04187793 A JPH04187793 A JP H04187793A JP 31561190 A JP31561190 A JP 31561190A JP 31561190 A JP31561190 A JP 31561190A JP H04187793 A JPH04187793 A JP H04187793A
Authority
JP
Japan
Prior art keywords
conductive film
plating
film
semiconductor device
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31561190A
Other languages
Japanese (ja)
Inventor
Tatsuya Hirose
達哉 廣瀬
Koichiro Kotani
小谷 絋一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP31561190A priority Critical patent/JPH04187793A/en
Publication of JPH04187793A publication Critical patent/JPH04187793A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

PURPOSE:To produce a semiconductor device with its opening being always covered by impressing the voltage/current alternately changing its direction between a plating electrode in a plating soln. and an electrode connected to a conductive material to be plated. CONSTITUTION:A plating tank 24 is filled with a plating soln. 25 contg. a surface brightener as the additive. One plating electrode 26a and a conductive material 27 to be plated connected to the other plating electrode 26b are dipped in the soln. 25. The electrode 26a is connected to minus of a DC power source 28 and to plus of a pulse power source 29, and the electrode 26b to plus of the source 28 and to minus of the source 29. Both power sources 28 and 29 are superimposed, and the voltage/current alternately changing its direction is impressed on the electrodes 26a and 26b. The additive forms a nucleus, a conductive plating film is formed on the material 27 with the opening being always covered and then removed by the counter voltage/current, hence the electric resistance of the conductive film is reduced, and an increase in hardness is prevented.

Description

【発明の詳細な説明】 〔目次〕 ・概要 ・産業上の利用分野 ・従来の技術(第5図〜第7図) ・発明が解決しようとする課題 ・課題を解決するための手段 ・作用 ・実施例 ■第1の実施例(第1図、第2図) ■第2の実施例(第3図) ■第3の実施例(第4図) ・発明の効果 [概要] 半導体装置及びその製造方法に関し、更に詳しく言えば
、電解メッキ法によりコンタクトホールやピアホールを
被覆して形成された電極等を有する半導体装置及びその
製造方法に関し、開口部のカバレージを保持するととも
に、電極又は配線の電気抵抗を低減し、更に、電極又は
配線金属の硬度に起因して絶縁膜に生しる歪みを低減す
ることができる半導体装置及びその製造方法を提供する
ことを目的とし、 半導体装置の製造方法は、添加剤を含むメッキ液中に一
方のメッキ電極と、他方のメッキ電極に接続された被メ
ッキ導電物とを入れ、交互に方向の変わる電圧/電流を
前記メッキ電極間に印加して前記被メッキ導電物上に導
電膜を形成することを含み構成し、 半導体装置は、第1に、導電体上の絶縁膜の開口部を被
覆する被メッキ導電膜の上に電解メッキにより形成され
た2層以上の多層導電膜を有する半導体装置であって、
前記多層導電膜の最下層の第1の導電膜が添加剤を含ま
ないメッキ液を用いて形成されたものであり、前記第1
の導電膜上の第2の導電膜が添加剤を含むメッキ液を用
いて形成されたものであることを含み構成し、第2に、
前記添加剤を含むメッキ液を用いて形成された第2の導
電膜が第1の発明に記載の製造方法により形成されたも
のであることを含み構成する。
[Detailed Description of the Invention] [Table of Contents] - Overview - Field of industrial application - Conventional technology (Figures 5 to 7) - Problems to be solved by the invention - Means and effects for solving the problems - Examples ■First example (Fig. 1, Fig. 2) ■Second example (Fig. 3) ■Third example (Fig. 4) - Effects of the invention [Summary] Semiconductor device and its Regarding the manufacturing method, more specifically, regarding a semiconductor device having an electrode, etc. formed by covering a contact hole or a peer hole by electrolytic plating, and its manufacturing method, the coverage of the opening is maintained, and the electrical conductivity of the electrode or wiring is maintained. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce resistance and further reduce strain that occurs in an insulating film due to the hardness of electrodes or wiring metal. , one plating electrode and a conductive object to be plated connected to the other plating electrode are placed in a plating solution containing additives, and a voltage/current with alternating directions is applied between the plating electrodes. The semiconductor device includes forming a conductive film on a plated conductor, and firstly, a conductive film is formed by electrolytic plating on a conductive film to be plated that covers an opening in an insulating film on the conductor. A semiconductor device having a multilayer conductive film having more than one layer,
The first conductive film at the bottom layer of the multilayer conductive film is formed using a plating solution containing no additives, and the first conductive film is formed using a plating solution containing no additives.
The second conductive film on the conductive film is formed using a plating solution containing an additive, and secondly,
The second conductive film formed using the plating solution containing the additive is formed by the manufacturing method according to the first invention.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体装置及びその製造方法に関し、更に詳
しく言えば、電解メッキ法によりコンタクトホールやピ
アホールを被覆して形成された電極等を有する半導体装
置及びその製造方法に関する。
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having electrodes formed by covering contact holes and peer holes by electrolytic plating, and a method for manufacturing the same.

近年、半導体装置の更なる高密度化に伴い、配線の多層
化及び微細化が図られており、半導体基板の表面の凹凸
が激しくなってきている。従って、ピアホール等のアス
ペクト比が大きくなるため、カバレージの良い配線等の
形成方法が望まれている。
In recent years, as semiconductor devices have become more densely packed, wiring has become more multilayered and finer, and the surface of semiconductor substrates has become increasingly uneven. Therefore, since the aspect ratio of pier holes and the like becomes large, a method of forming wiring and the like with good coverage is desired.

(従来の技術) 従来、カバレージの良い配線等を形成する一方法として
表面光沢剤を含むメッキ液を用いる電解メッキ法がある
(Prior Art) Conventionally, as a method for forming wiring and the like with good coverage, there is an electrolytic plating method using a plating solution containing a surface brightener.

第7図(a)〜(c)は、このような電解メッキ法を用
いて上部配線層及び下部配線層を形成する方法について
説明する断面図である。
FIGS. 7(a) to 7(c) are cross-sectional views illustrating a method of forming an upper wiring layer and a lower wiring layer using such an electrolytic plating method.

まず、第7e(a)に示す半導体基Fi1及びバッファ
電極3上の下地絶縁膜2に形成されたコンタクトホール
2aを被覆してスパッタなどにより第1の下地導電膜4
を形成した後、第5図に示すメッキ槽9中の表面光沢剤
を含むメッキ液1oを用いて直流iff源13からの電
圧/電流を印加して行う電解メッキによりこの第1の下
地導1を膜4(被メッキ導電物12)上に第1のAu膜
5を形成する。このとき、表面の凹凸を滑らかにする表
面光沢剤の作用にまりカバレージの良い第1のAu膜5
が形成される(第7図(b))。
First, the contact hole 2a formed in the base insulating film 2 on the semiconductor substrate Fi1 and the buffer electrode 3 shown in No. 7e(a) is covered with a first base conductive film 4 by sputtering or the like.
After forming the first base conductor 1, electrolytic plating is performed using a plating solution 1o containing a surface brightener in a plating bath 9 shown in FIG. 5 and applying voltage/current from a DC IF source 13. A first Au film 5 is formed on the film 4 (the conductive material 12 to be plated). At this time, the first Au film 5 with good coverage is applied to the action of the surface brightener that smooths out the unevenness of the surface.
is formed (Fig. 7(b)).

次いで、第1のAu膜(下部導電膜)5及び第1の下地
導電膜4をパターニングして下部配線層12aを形成し
た後、下部配線層12aを被覆して層間絶縁膜6を形成
する。
Next, the first Au film (lower conductive film) 5 and the first base conductive film 4 are patterned to form a lower wiring layer 12a, and then an interlayer insulating film 6 is formed to cover the lower wiring layer 12a.

次に、下部配線層12a上の層間絶縁膜6にピアホール
6aを形成した後、第7図(b)に示す方法と同様にし
てピアホール6aを被覆して第2のAu膜(上部導!1
1り 8を形成し、その後、第2のAu膜8及び第2の
下地導電膜7をパターニングして上部配線層12bを形
成する(第7図(C))。
Next, after forming a pier hole 6a in the interlayer insulating film 6 on the lower wiring layer 12a, the pier hole 6a is covered with a second Au film (upper conductor 1) in the same manner as shown in FIG. 7(b).
After that, the second Au film 8 and the second underlying conductive film 7 are patterned to form an upper wiring layer 12b (FIG. 7(C)).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、上記の方法では、形成された第1及び第2のA
u膜5及び8に表面光沢剤を含むため、■硬い。
However, in the above method, the formed first and second A
■Hard because the u-films 5 and 8 contain a surface brightener.

■電気抵抗が大きい。■High electrical resistance.

このため、 ■第1及び第2のAu膜5及び8と接する。又は近接す
る下地絶縁膜2又は層間絶縁膜6に応力を与え、これら
の絶縁M2,6にクラックが入る場合があり、絶縁性が
低下する。
Therefore, (1) it comes into contact with the first and second Au films 5 and 8; Alternatively, stress may be applied to the adjacent base insulating film 2 or interlayer insulating film 6, causing cracks to appear in these insulations M2 and 6, resulting in a decrease in insulation properties.

■電圧の降下が大きく、半導体装置の特性が低下する。■The voltage drop is large and the characteristics of the semiconductor device are degraded.

という問題がある。There is a problem.

本発明は、かかる従来の問題点に鑑みてなされたもので
、開口部のカバレージを保持するとともに、電極又は配
線の電気抵抗を低減し、更に、電極又は配線金属の硬度
に起因して絶縁膜に生じる歪みを低減することができる
半導体装置及びその製造方法を提供することを目的とす
るものである。
The present invention has been made in view of such conventional problems, and it maintains the coverage of the opening, reduces the electrical resistance of the electrode or wiring, and further improves the resistance of the insulating film due to the hardness of the electrode or wiring metal. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can reduce distortion caused in the semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は、第1に、添加剤を含むメッキ液中に一方の
メッキ電極と、他方のメッキ電極に接続された被メッキ
導電物とを入れ、交互に方向の変わる電圧/電流を前記
メッキ電極間に印加して前記被メンキ導電物とに導電膜
を形成することを特徴とする半導体装置の製造方法によ
って達成され、第2に、導電体上の絶縁膜の開口部を被
覆する被メッキ導電膜の上に電解メッキにより形成され
た2層以上の多層導電膜を有する半導体装置であって、
前記多層導電膜の最下層の第1の導電膜が添加剤を含ま
ないメッキ液を用いて形成されたものであり、前記第1
の導電膜上の第2の導電膜が添加剤を含むメッキ液を用
いて形成されたものであることを特徴とする半導体装置
によって達成され、 第3に、導電体上の絶縁膜の開口部を被覆する被メッキ
導電膜の上に電解メッキにより形成された3層以上の多
層導電膜を有する半導体装置であって、前記多層導電膜
の最下層の第1の導電膜及び最上層の第3の導電膜が添
加剤を含まないメ。
First, one plating electrode and a conductive material to be plated connected to the other plating electrode are placed in a plating solution containing additives, and a voltage/current that alternately changes direction is applied to the plating electrode. This is achieved by a method for manufacturing a semiconductor device characterized in that a conductive film is formed on the conductive material to be plated by applying an electric current between the conductive material and the conductive material to be plated. A semiconductor device having a multilayer conductive film of two or more layers formed by electrolytic plating on a film,
The first conductive film at the bottom layer of the multilayer conductive film is formed using a plating solution containing no additives, and the first conductive film is formed using a plating solution containing no additives.
A semiconductor device characterized in that the second conductive film on the conductive film is formed using a plating solution containing an additive, and thirdly, an opening in the insulating film on the conductor. A semiconductor device having a multilayer conductive film of three or more layers formed by electrolytic plating on a conductive film to be plated that covers a conductive film, the first conductive film being the bottom layer and the third conductive film being the top layer of the multilayer conductive film. The conductive film does not contain additives.

キ液を用いて形成されたものであり、前記第1の導電膜
及び第3の導電膜の間に添加剤を含む、メッキ液を用い
て形成されたものであることを特徴とする半導体装置に
よって達成され、 第4に、前記添加剤を含むメッキ液を用いて形成された
第2の導電膜が第1の発明に記載の方法により形成され
たものであることを特徴とする第2の発明、或いは第3
の発明いずれかに記載の半導体装置によって達成される
A semiconductor device, characterized in that the semiconductor device is formed using a plating solution, and the semiconductor device is formed using a plating solution that contains an additive between the first conductive film and the third conductive film. Fourthly, the second conductive film formed using the plating solution containing the additive is formed by the method according to the first invention. invention or third
This is achieved by the semiconductor device according to any one of the inventions.

〔作用] 第1の発明の半導体装置の製造方法によれば、第1図(
a)、(b)及び第2図(a)、(b)に示すように、
メッキのための電圧/電流を交互に方向を変えて印加し
ているので、まず第1図(a)のメッキ電極26a、2
6bから被メッキ導電物27に向かって電流が流れてい
る間(第2図(c)、(d))は表面光沢剤(添加剤)
33が被メッキ導電物27の凸部35に電着し、これを
核として導電膜34が電着されてい(が、逆方向に流れ
る間(第2図(e))は逆に被メッキ導電物27から電
着された表面光沢剤33が除去される。従って、これを
繰り返して(第2図(f)〜(i))形成された導電膜
34中の表面光沢剤33の含有量は激減する。
[Operation] According to the method for manufacturing a semiconductor device of the first invention, the method shown in FIG.
As shown in a), (b) and Fig. 2 (a), (b),
Since the voltage/current for plating is applied in alternating directions, first the plating electrodes 26a and 2 in FIG.
While the current is flowing from 6b toward the conductive material 27 to be plated (Fig. 2(c) and (d)), the surface brightener (additive)
33 is electrodeposited on the convex portion 35 of the conductive material 27 to be plated, and the conductive film 34 is electrodeposited using this as a nucleus (however, while flowing in the opposite direction (Fig. 2(e)), the conductive film 34 is electrodeposited on the convex portion 35 of the conductive material 27 to be plated. The surface brightener 33 electrodeposited from the object 27 is removed. Therefore, the content of the surface brightener 33 in the conductive film 34 formed by repeating this process (FIG. 2(f) to (i)) is Decrease sharply.

これにより、電気抵抗を低減することができる。Thereby, electrical resistance can be reduced.

しかも、電着は表面光沢剤33を介して行われるため、
表面光沢剤33の作用により導電膜34のカバレージは
もとのまま保持される。
Moreover, since electrodeposition is performed via the surface brightener 33,
Due to the action of the surface brightener 33, the coverage of the conductive film 34 is maintained as it was.

また、第2の発明の半導体装置によれば、表面光沢剤(
添加剤)を含まないメッキ液を用いて作成した第1の導
電膜が絶縁膜に近い方に設けられている。
Further, according to the semiconductor device of the second invention, a surface brightener (
A first conductive film created using a plating solution containing no additives is provided closer to the insulating film.

更に、層間絶縁膜により被覆される場合には、第3の発
明の半導体装置のように最下層の第1の導電膜及び最上
層の第3の導電膜が表面光沢剤(添加剤)を含まないメ
ッキ液を用いて作成されていれば、第1の導電膜及び第
3の導電膜が層間絶縁膜と近接し又は接することになる
Furthermore, when covered with an interlayer insulating film, the first conductive film at the bottom layer and the third conductive film at the top layer contain a surface brightener (additive) as in the semiconductor device of the third invention. If the first conductive film and the third conductive film are formed using a plating solution other than the interlayer insulating film, the first conductive film and the third conductive film will be close to or in contact with the interlayer insulating film.

従って、通常、表面光沢剤を含まないメ、7キ液を用い
て作成された導電膜は軟らかいので、第1及び第3の導
電膜の間に表面光沢剤を含まないメッキ液を用いて作成
された硬い第2の導電膜が存在していても、第1及び第
3の導電膜により第2の導電膜から絶縁膜への応力は緩
和される。特に、第2の導電膜が第1の発明に記載の電
解メッキ法により形成されることにより電気抵抗を低減
できる。
Therefore, since the conductive film created using a plating solution that does not contain a surface brightener is usually soft, a plating solution that does not contain a surface brightener is used between the first and third conductive films. Even if the hard second conductive film is present, the stress from the second conductive film to the insulating film is alleviated by the first and third conductive films. In particular, the electrical resistance can be reduced by forming the second conductive film by the electrolytic plating method described in the first invention.

更に、表面光沢剤を含まないメッキ液を用いて作成され
た第1又は第3の導電膜だけでは、カバレージが悪化す
るので、第1の導電膜の上に又は第1の導電膜と第3の
導電膜との間に、表面光沢剤を含まないメッキ液を用い
て作成した第2の導電膜が形成されることにより、カバ
レージはもとのまま保持される。
Furthermore, if only the first or third conductive film is formed using a plating solution that does not contain a surface brightener, the coverage will be deteriorated. A second conductive film made using a plating solution that does not contain a surface brightener is formed between the conductive film and the second conductive film, thereby maintaining the original coverage.

〔実施例〕〔Example〕

以下、図面を参照しながら本発明の実施例について説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

■第1の実施例 本発明の第1の実施例の電解メッキ法について第1図(
a)、(b)及び第2図(a) 〜(i)を参照しなが
ら説明する。
■First Example The electrolytic plating method of the first example of the present invention is shown in Figure 1 (
This will be explained with reference to a), (b) and FIGS. 2(a) to (i).

第1図は、本発明の第1の実施例の電解メッキ法につい
て説明する図、第2図(a)〜(i)は作用について説
明する図である。
FIG. 1 is a diagram for explaining the electrolytic plating method according to the first embodiment of the present invention, and FIGS. 2(a) to (i) are diagrams for explaining the operation.

まず、第1図(a)に示すように、表面光沢剤(添加剤
)を含むメ・7キ液24として例えば日木工しクトロプ
レーティングエンジュャーズ社(EEJA)製のAuメ
ッキ液オートロネクスMP(商品名)をメッキ槽24に
入れる。そして、チタン(Ti)材に白金(Pt)膜を
コーティングしたメツシュ状の一方のメッキ電極26a
と、他方のメッキ電極26bに接続した被メッキ導電物
27とを浸せきする。更に、これらの電極26a、26
bにそれぞれ直流電源28の一例、+側を接続し、かつ
直流電源28と並列にパルス電源29の+側。
First, as shown in FIG. 1(a), as a metal plating liquid 24 containing a surface brightener (additive), for example, the Au plating liquid AUTOTROL manufactured by Nikki Koutro Plating Enjurs Co., Ltd. (EEJA) is used. Place NEX MP (trade name) into the plating tank 24. One of the plated electrodes 26a is a mesh-like plated electrode made of titanium (Ti) coated with a platinum (Pt) film.
and the conductive material to be plated 27 connected to the other plating electrode 26b. Furthermore, these electrodes 26a, 26
An example of a DC power supply 28 and the + side thereof are connected to b, respectively, and the + side of a pulse power supply 29 is connected in parallel with the DC power supply 28.

−側を接続する。Connect the − side.

次いで、第1図(b)に示すように、直流電源28によ
り電流密度(Jl )約1mA/cm”の直流電流を供
給し、かつパルス電源29から電流密度(J、)のピー
ク値が100〜50(l m A / c m’ 。
Next, as shown in FIG. 1(b), the DC power supply 28 supplies a DC current with a current density (Jl) of about 1 mA/cm'', and the pulse power supply 29 supplies a DC current with a current density (Jl) of about 100 mA/cm''. ~50 (l m A / cm'.

パルス幅0.1秒3周期1秒のパルス電流を供給すると
、被メッキ導電物27上にAu膜(導電膜)が電着しは
じめる。
When a pulse current with a pulse width of 0.1 seconds and 3 cycles of 1 second is supplied, an Au film (conductive film) begins to be electrodeposited on the conductive material 27 to be plated.

このとき、メッキのための電圧/電流が交互に方向を変
えながら印加されるので、まずメッキ電極26aから被
メッキ導電物27に向かって電流が流れている間(第2
図(c)、(d))は表面光沢剤33が被メッキ導電物
27の凸部35に電着し、これを核として導電膜(第2
の導電膜)34が電着されていくが、逆方向に流れる間
(第2図(e))は逆に被メッキ導電物27から電着さ
れた表面光沢剤33が除去される。従って、これを繰り
返して(第2図(f)〜(i))形成された導電膜34
中の表面光沢剤33の含有量は激減する。
At this time, the voltage/current for plating is applied while changing the direction alternately, so first, while the current is flowing from the plating electrode 26a toward the conductive object 27 to be plated (second
Figures (c) and (d) show that the surface brightener 33 is electrodeposited on the convex portion 35 of the conductive material 27 to be plated, and uses this as a core to form the conductive film (second
The electroconductive film 34 is electrodeposited, but while the electroconductive film 34 is flowing in the opposite direction (FIG. 2(e)), the electrodeposited surface brightener 33 is removed from the conductive material 27 to be plated. Therefore, the conductive film 34 formed by repeating this process (FIG. 2(f) to (i))
The content of the surface brightener 33 inside is drastically reduced.

その後、この状態を所定時間保持することにより所定の
膜厚の導電膜34が電着する。
Thereafter, by maintaining this state for a predetermined time, a conductive film 34 having a predetermined thickness is electrodeposited.

以上のように、第1の実施例の電解メッキ法によれば、
形成された導電膜34中の表面光沢剤33の含有量は激
減するので、硬度を低減し、電気抵抗を低減することが
できる。しかも、電着は表面光沢剤33を介して行われ
るため、表面光沢剤33の作用により電着する導電膜3
4のカバレージはもとのまま保持される。
As described above, according to the electrolytic plating method of the first embodiment,
Since the content of the surface brightener 33 in the formed conductive film 34 is drastically reduced, the hardness and electrical resistance can be reduced. Moreover, since the electrodeposition is performed via the surface brightener 33, the conductive film 3 is electrodeposited by the action of the surface brightener 33.
The coverage of 4 is kept intact.

なお、第1の実施例では、Auメッキ液を用いているが
、アルミニウム(Af)、銅(Cu)。
Note that in the first embodiment, an Au plating solution is used, but aluminum (Af) and copper (Cu) are used.

ニッケル(N i ) 、白金(Pt)、Rh、Ruの
メッキ液を用いることができる。
Plating solutions of nickel (N i ), platinum (Pt), Rh, and Ru can be used.

■第2の実施例の半導体装置 次に、本発明の第2の実施例の半導体装置について第3
図を参照しながら説明する。
■Semiconductor device according to the second embodiment Next, we will discuss the semiconductor device according to the second embodiment of the present invention in the third section.
This will be explained with reference to the figures.

第3図は、本発明の第2の実施例の半導体装置の断面図
である。
FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

同図において、14は化合物半導体などからなる半導体
基板、16は半導体基板14を配線と接続するために半
導体基板I4上に選択的に設けられたバッファ電極、1
5はバッファ電極16を露出するように設けられたSi
O□膜などからなる下地絶縁WI(絶縁膜)、15aは
バッファ電極16上の下地絶縁膜15に設けられたコン
タクトホール(開口部)である。
In the figure, 14 is a semiconductor substrate made of a compound semiconductor or the like, 16 is a buffer electrode selectively provided on the semiconductor substrate I4 to connect the semiconductor substrate 14 to wiring, and 1
5 is a Si provided to expose the buffer electrode 16.
A base insulating film WI (insulating film) 15a made of an O□ film or the like is a contact hole (opening) provided in the base insulating film 15 on the buffer electrode 16.

また、17はメッキ金属を電着するための、膜厚約30
0人のTi膜とその上の膜厚約1000人の篩膜からな
る下地導電膜、18aは表面光沢剤(添加剤)を含まな
いメッキ液を用いて通常の直流の電解メ・、キ法により
作成された下地導電膜17上の、膜厚2000〜400
0人のAuからなる第1の導電膜で、この第1の導電膜
18aは表面光沢剤を含まないので軟らかい。更に、1
9は表面光沢剤(添加剤)を含むメッキ液を用いて第1
の実施例の電解メ・ゼキ法により作成された第1の導電
膜18a上の膜厚5000〜6000人のAuからなる
第2の導電膜で、この第2の導電膜19は表面光沢剤が
非常に少なくなっているので、通常に表面光沢剤を含む
膜と比較して軟らかく、電気抵抗は非常に小さくなって
いる。なお、表面光沢剤が非常に少なくなっているとは
いえ、表面光沢剤を含むので、表面光沢剤を含む第1の
導電膜18aと比較して硬い、また、18bは第1の導
電膜18aと同様に表面光沢剤を含まないメッキ液を用
いて通常の直流の電解メッキ法により作成された第2の
導電膜19上の膜厚2000〜4000人のAuからな
る軟らかい第3の導電膜である。なお、第1の導電膜1
8a/第2の導電膜19/第3の導電膜18bの3層膜
により多層導電膜31を構成し、この多層導電膜31と
下地導電膜17とで下部配線層を構成する。
In addition, 17 is a film thickness of approximately 30 mm for electrodepositing plating metal.
The base conductive film 18a consists of a Ti film of 0.0000000000000000 and a sieve film of about 1000000000000 on top of it. The film thickness on the base conductive film 17 created by
The first conductive film 18a is made of 0% Au and is soft because it does not contain a surface brightener. Furthermore, 1
9 is the first step using a plating solution containing a surface brightener (additive).
The second conductive film 19 is made of Au with a thickness of 5000 to 6000 on the first conductive film 18a prepared by the electrolytic method of Example 1. Since the amount is very small, the film is softer and has a much lower electrical resistance than a film that normally contains a surface brightener. Although the amount of the surface brightener is very small, since it contains the surface brightener, it is harder than the first conductive film 18a that contains the surface brightener. A soft third conductive film made of Au with a film thickness of 2,000 to 4,000 nm is formed on the second conductive film 19, which is created by a normal DC electrolytic plating method using a plating solution that does not contain a surface brightener in the same manner as above. be. Note that the first conductive film 1
A multilayer conductive film 31 is composed of three layers of 8a/second conductive film 19/third conductive film 18b, and this multilayer conductive film 31 and base conductive film 17 constitute a lower wiring layer.

更に、20は下部配線層を被覆する膜厚約1μmのPS
G膜などからなる層間絶縁膜、20aは下部配線層上に
設けられたピアホール(開口部)、21は下部配線層を
構成する下地導電膜17と同じ金属、かつ同様な方法で
形成された、ピアホール20を被覆する膜厚約300人
のTi膜とその上の膜厚約1000人の^U膜からなる
下地導電膜、22は下部配線層を構成する第1の導電膜
18aと同じメッキ液、かつ同様な方法で形成された、
下地導電膜21上の、膜厚2000〜4000人の軟ら
かいAuからなる第1の導電膜、23は下部配線層を構
成する第2の導電膜19と同じメッキ液、かつ同様な方
法で形成された、第1の導電膜22上の膜厚50OO〜
6000人の少し硬いAuからなる第2の導電膜である
。なお、これらの第1の導電膜22/第2の導電膜23
の2層膜が多層導電W!32を構成し、この多層導電膜
32と下地導電膜21とが上部配線層を構成する。
Furthermore, 20 is PS with a thickness of about 1 μm covering the lower wiring layer.
An interlayer insulating film made of a G film or the like, 20a a peer hole (opening) provided on the lower wiring layer, 21 made of the same metal as the base conductive film 17 constituting the lower wiring layer, and formed by the same method. An underlying conductive film consisting of a Ti film with a thickness of about 300 thick covering the peer hole 20 and a U film overlying it with a thickness of about 1000 thick, 22 is the same plating solution as the first conductive film 18a constituting the lower wiring layer. , and formed in a similar manner,
A first conductive film 23 made of soft Au having a film thickness of 2,000 to 4,000 on the base conductive film 21 is formed using the same plating solution and using the same method as the second conductive film 19 constituting the lower wiring layer. In addition, the film thickness on the first conductive film 22 is 50 OO~
This is a second conductive film made of slightly harder Au of 6,000 yen. Note that these first conductive films 22/second conductive films 23
The two-layer film is multilayer conductive W! 32, and this multilayer conductive film 32 and base conductive film 21 constitute an upper wiring layer.

以上のような第2の実施例の半導体装置によれば、下部
配線層において、表面光沢剤を含まないメッキ液を用い
て作成した第1の導電膜18aと第3の導電膜18bと
により表面光沢剤を含むメッキ液を用いて作成された第
2の導電膜が挾まれている。
According to the semiconductor device of the second embodiment as described above, in the lower wiring layer, the first conductive film 18a and the third conductive film 18b are formed using a plating solution that does not contain a surface brightener. A second conductive film created using a plating solution containing a brightener is sandwiched therebetween.

従って、軟らかい第1の導電膜18aと第3の導電膜1
8bが絶縁膜15.20と近接し又は接することになる
ので、第1の導電膜18aと第3の導電膜18bとの間
により硬い第2の導電11119が存在していても、第
1の導電膜18a及び第3の導電膜18bにより第2の
導電膜19から絶縁膜への応力は緩和される。また、第
2の導電膜19は表面光沢剤を僅かしか含まないので、
電気抵抗を低減できる。
Therefore, the soft first conductive film 18a and the third conductive film 1
8b is close to or in contact with the insulating film 15.20, even if the harder second conductive film 11119 exists between the first conductive film 18a and the third conductive film 18b, the first The stress from the second conductive film 19 to the insulating film is relaxed by the conductive film 18a and the third conductive film 18b. Furthermore, since the second conductive film 19 contains only a small amount of surface brightener,
Electrical resistance can be reduced.

また、上部配線層においても、層間絶縁膜20と硬い第
2の導電膜23の間に軟らかい第1の導電膜22を有し
ているので、下部配線層の場合と同様な作用・効果を有
する。また、第2の導電膜23は表面光沢剤を僅かしか
含まないので、電気抵抗を低減できる。
In addition, since the upper wiring layer also has the soft first conductive film 22 between the interlayer insulating film 20 and the hard second conductive film 23, it has the same function and effect as the lower wiring layer. . Furthermore, since the second conductive film 23 contains only a small amount of surface brightener, electrical resistance can be reduced.

なお、第2の実施例では、下部配線層及び上部配線層の
第2の導電膜19.23が第1の実施例の電解メッキ法
により作成されたものであるが、通常の直流の電解メッ
キ法により表面光沢剤を含むメッキ液を用いて形成され
たものでもよい。これにより、第1の導電膜18a、2
2及び第3の導電1118 bにより第2の導電膜19
.23から絶縁膜への応力は緩和される。
In addition, in the second embodiment, the second conductive films 19 and 23 of the lower wiring layer and the upper wiring layer were created by the electrolytic plating method of the first embodiment, but ordinary DC electrolytic plating was used. It may be formed using a plating solution containing a surface brightener by a method. As a result, the first conductive films 18a, 2
The second conductive film 19 is formed by the second and third conductive films 1118 b.
.. The stress from 23 to the insulating film is relaxed.

■第3の実施例の半導体装置の製造方法次に、第3の実
施例の半導体装置の製造方法について第4図(a)〜(
h)を参照しながら説明する。
■Method for manufacturing a semiconductor device according to the third embodiment Next, the method for manufacturing a semiconductor device according to the third embodiment will be explained in FIGS.
This will be explained with reference to h).

まず、電解メッキ法により導電膜を形成するため、第4
[ff1(a)に示す半導体基板14及びバッファ電極
16(導電体)上の下地絶縁膜(絶縁膜)I5に形成さ
れたコンタクトボール(開口部)15aを被覆して、ス
パッタなどにより膜厚約300人のTi膜とその上の膜
厚約1000人のAu膜からなる下地導電膜17を形成
した後、表面光沢剤を含まないメンキ液、例えば日本エ
レクトロブレーティング社製のテンペレックス401 
(商品名)を用いて通常の電解メッキ法によりAuから
なる第1の導電膜18aを形成する(第4図(b))。
First, in order to form a conductive film by electrolytic plating, the fourth
[ff1(a) The contact balls (openings) 15a formed in the base insulating film (insulating film) I5 on the semiconductor substrate 14 and the buffer electrode 16 (conductor) are covered with a film thickness of approximately After forming the base conductive film 17 consisting of a 300-layer Ti film and an approximately 1000-layer Au film thereon, a Menki solution containing no surface brightening agent, such as Temperex 401 manufactured by Nippon Electroblating Co., Ltd., is applied.
A first conductive film 18a made of Au is formed by a normal electrolytic plating method using (trade name) (FIG. 4(b)).

なお、この第1の導電膜18aは表面光沢剤を含まない
ので、通常軟らかい。
Note that since this first conductive film 18a does not contain a surface brightener, it is usually soft.

次に、第1図(a)に示すように、メッキ槽24中の表
面光沢剤(添加剤)を含むメッキ液25を用いて直流電
源28とパルス電源29により、第1の導電膜18aと
メッキ電極26aとの間に印加する電圧/電流を、第1
図(b)に示すように、印加力向を交互に変えながら行
う電解メッキ法によりこの第1の導電膜18a(被メッ
キ導電物)上にAu膜からなる第2の導電膜19を形成
する。
Next, as shown in FIG. 1(a), the first conductive film 18a is coated with the plating solution 25 containing a surface brightener (additive) in the plating bath 24 using the DC power supply 28 and the pulse power supply 29. The voltage/current applied between the plating electrode 26a and the first
As shown in Figure (b), a second conductive film 19 made of an Au film is formed on the first conductive film 18a (conductor to be plated) by electrolytic plating, which is performed while alternating the direction of applied force. .

このとき、表面の凹凸を滑らかにする表面光沢剤の作用
により第2の導電膜19はカバレージが良い(第4図(
C))。
At this time, the second conductive film 19 has good coverage due to the action of the surface brightener that smooths out the unevenness of the surface (see Fig. 4).
C)).

次いで、第2の導電膜19上に、第4図(ト)と同様に
してAuからなる第3の導電膜18bを形成する(第4
図(d))、なお、この第3の導電膜18bも表面光沢
剤を含まないので、通常軟らかい。そして、第1の導電
膜18a/第2の導電膜19/第3の導電膜18bの3
層膜が多層導電膜31を構成し、多層導電膜31と下地
導電膜17とが下部配線層(N電体)を構成する。
Next, a third conductive film 18b made of Au is formed on the second conductive film 19 in the same manner as in FIG.
Note that this third conductive film 18b also does not contain a surface brightener and is therefore usually soft. 3 of the first conductive film 18a/second conductive film 19/third conductive film 18b.
The layers constitute a multilayer conductive film 31, and the multilayer conductive film 31 and the base conductive film 17 constitute a lower wiring layer (N conductor).

次に、下部配線層を被覆してPSG膜等からなる層間絶
縁膜20を形成した後、下部配線層上の層間絶縁膜20
にピアホール(開口部)20aを形成する(同図(e)
)。
Next, after forming an interlayer insulating film 20 made of a PSG film or the like to cover the lower wiring layer, the interlayer insulating film 20 on the lower wiring layer is formed.
A pier hole (opening) 20a is formed in ((e) of the same figure).
).

次いで、第4図(b)と同様な金属及び方法によりピア
ホール20aを被覆して上部配線層を構成する下地導電
膜21と第1の導電膜22とを形成する(同図(f))
Next, a base conductive film 21 and a first conductive film 22 which cover the peer hole 20a and constitute an upper wiring layer are formed using the same metal and method as in FIG. 4(b) (FIG. 4(f)).
.

次に、第4図(C)と同様な金属及び方法により第1の
導電M22上に第2の導tM23を形成する(同図(g
))。なお、第1の導電膜22/第2の導電膜23の2
層膜が多層導電膜32を構成する。
Next, a second conductor tM23 is formed on the first conductor M22 using the same metal and method as in FIG.
)). Note that 2 of the first conductive film 22/second conductive film 23
The layers constitute a multilayer conductive film 32.

その後、第2の導電膜23.第1の導電膜22及び下地
導電膜21をパターニングして上部配線層を形成する(
同図(h)、第1図)。
After that, the second conductive film 23. The first conductive film 22 and the base conductive film 21 are patterned to form an upper wiring layer (
Figure 1 (h).

以上のように、本発明の第3の実施例の半導体装置の製
造方法によれば、表面光沢剤を含まないメッキ液を用い
て作成された第1又は第3の導電膜18a又は18bだ
けでは、カバレージが悪化するが、第1の導電膜22の
上に又は第1の導電膜18aと第3の導電膜18bとの
間に、表面光沢剤を含むメッキ液を用いて作成した第2
の導電膜23又は19が形成されることにより、カバレ
ージはもとのまま保持される。
As described above, according to the method for manufacturing a semiconductor device according to the third embodiment of the present invention, the first or third conductive film 18a or 18b created using a plating solution that does not contain a surface brightener is not enough. , the coverage deteriorates, but the second conductive film is formed using a plating solution containing a surface brightener on the first conductive film 22 or between the first conductive film 18a and the third conductive film 18b.
By forming the conductive film 23 or 19, the original coverage is maintained.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明の半導体装置の製造方法によれば
、メンキのだめの電流を順逆交互に流しているので、ま
ず順方向にメッキ電流が流れている間は表面光沢剤が被
メ・ンキ用導電膜の凸部に電着し、これを核としてメッ
キ膜が電着されていくが、逆方向に流れる間は逆に被メ
ッキ物上から電着された表面光沢剤が除去される。従っ
て、これを繰り返して形成された導電膜中には表面光沢
剤の含有量は激減する。
As described above, according to the method for manufacturing a semiconductor device of the present invention, since the current in the plating reservoir is passed alternately in forward and reverse directions, first, while the plating current is flowing in the forward direction, the surface brightener is applied to the coating material. The electroplating agent is electrodeposited on the convex portion of the conductive film, and the plating film is electrodeposited using this as a core, but while flowing in the opposite direction, the electrodeposited surface brightener is removed from the object to be plated. Therefore, the content of the surface brightener in the conductive film formed by repeating this process is drastically reduced.

これにより、電気抵抗を低減することができる。Thereby, electrical resistance can be reduced.

しかも、電着は表面光沢剤を介して行われるため、表面
光沢剤の作用によりメッキ膜のカバレージはもとのまま
保持される。
Furthermore, since the electrodeposition is performed via a surface brightener, the coverage of the plating film is maintained as it was due to the action of the surface brightener.

また、本発明の半導体装置によれば、表面光沢剤を含ま
ないメッキ液を用いて作成した導電膜を絶縁膜に近い方
に設けている。更に、層間絶縁膜により被覆される場合
には、最上層の第3の導電膜も表面光沢剤を含まないメ
ッキ液を用いて作成されていれば、第3の導電膜は層間
絶縁膜と接することになる。いま、表面光沢剤を含まな
いメッキ液を用いて作成した導電膜は、軟らかいので、
これらの導電膜は眉間絶縁膜に応力を与えにくい。
Further, according to the semiconductor device of the present invention, the conductive film created using a plating solution that does not contain a surface brightener is provided closer to the insulating film. Furthermore, in the case of being covered with an interlayer insulating film, if the third conductive film on the top layer is also created using a plating solution that does not contain a surface brightener, the third conductive film will be in contact with the interlayer insulating film. It turns out. Currently, conductive films created using plating solutions that do not contain surface brighteners are soft, so
These conductive films hardly apply stress to the glabellar insulating film.

更に、表面光沢剤を含まないメッキ液を用いて作成した
導電膜だけでは、カバレージが悪化するので、これを防
ぐため表面光沢剤を含まないメ。
Furthermore, if a conductive film is formed using only a plating solution that does not contain a surface brightener, the coverage will deteriorate, so to prevent this, a method that does not contain a surface brightener is used.

キ液を用いて作成した導電膜をこれらの導電膜の間又は
上に形成している。
A conductive film made using a liquid is formed between or on these conductive films.

また、この導電膜は上記の方法を用いて形成されている
ので、電気抵抗を低減できる。
Furthermore, since this conductive film is formed using the above method, electrical resistance can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の第1の実施例の電解メッキ法につい
て説明する図、 第2図は、本発明の第1の実施例の電解メッキ法の作用
について説明する図、 第3図は、本発明の第2の実施例の多層配線構造につい
て説明する断面図、 第4図は、本発明の第2の実施例の多層配線層を作成す
る方法について説明する断面図、第5図は、従来例の電
解メッキ方法について説明する図、 第6間は、従来例の多層配線構造について説明する断面
図、 第7図は、従来例の多層配線の作成方法について説明す
る断面図である。 [符号の説明] 1.14・・・半導体基板、 2・・・下地絶縁膜、 2a・・・コンタクトホール、 3.16・・・ハンファ電極、 4.7.17.21・・・下地導電膜、5・・・第1の
Au膜(下部導電膜)、6・・・層間絶縁膜、 6a・・・ピアホール、 8・・・第2のAu膜(上部導電膜)、9.24・・・
メッキ槽、 10.25・・・メッキ液、 11.26a、26b−・・メッキ電極、12a・・・
下部配線層、 12b・・・上部配線層、 13.28・・・直流電源、 15・・・下地絶縁膜(絶縁膜)、 15a・・・コンタクトホール(開口部)、18a、2
2・・・第1の導電膜(被メッキ導電物)、18b・・
・第3の導電膜、 19.23・・・第2の導電膜(導電膜)、20・・・
層間絶縁膜(絶縁H)、 20a・・・ピアホール(開口部)、 27・・・被メッキ導電物、 29・・・パルス電源、 30・・・導電体、 31.32・・・多層導電膜、 33・・・表面光沢剤(添加剤)、 34・・・導電膜、 35・・・凸部。
FIG. 1 is a diagram explaining the electrolytic plating method according to the first embodiment of the present invention. FIG. 2 is a diagram explaining the action of the electrolytic plating method according to the first embodiment of the present invention. FIG. , FIG. 4 is a sectional view illustrating a method for creating a multilayer wiring structure according to the second embodiment of the present invention, and FIG. , a diagram illustrating a conventional electrolytic plating method, a sixth section is a sectional view illustrating a conventional multilayer wiring structure, and FIG. 7 is a sectional view illustrating a conventional method for creating a multilayer wiring. [Explanation of symbols] 1.14...Semiconductor substrate, 2...Base insulating film, 2a...Contact hole, 3.16...Hanwha electrode, 4.7.17.21...Base conductive film Film, 5... First Au film (lower conductive film), 6... Interlayer insulating film, 6a... Pier hole, 8... Second Au film (upper conductive film), 9.24.・・・
Plating bath, 10.25... Plating solution, 11.26a, 26b-... Plating electrode, 12a...
Lower wiring layer, 12b... Upper wiring layer, 13.28... DC power supply, 15... Base insulating film (insulating film), 15a... Contact hole (opening), 18a, 2
2...First conductive film (conductor to be plated), 18b...
- Third conductive film, 19.23... Second conductive film (conductive film), 20...
Interlayer insulating film (insulation H), 20a... Pier hole (opening), 27... Conductive material to be plated, 29... Pulse power source, 30... Conductor, 31.32... Multilayer conductive film , 33... Surface brightener (additive), 34... Conductive film, 35... Convex portion.

Claims (4)

【特許請求の範囲】[Claims] (1)添加剤を含むメッキ液中に一方のメッキ電極と、
他方のメッキ電極に接続された被メッキ導電物とを入れ
、交互に方向の変わる電圧/電流を前記メッキ電極間に
印加して前記被メッキ導電物上に導電膜を形成すること
を特徴とする半導体装置の製造方法。
(1) One plating electrode in a plating solution containing additives,
A conductive material to be plated connected to the other plating electrode is inserted, and a voltage/current with alternating directions is applied between the plating electrodes to form a conductive film on the conductive material to be plated. A method for manufacturing a semiconductor device.
(2)導電体上の絶縁膜の開口部を被覆する被メッキ導
電膜の上に電解メッキにより形成された2層以上の多層
導電膜を有する半導体装置であって、前記多層導電膜の
最下層の第1の導電膜が添加剤を含まないメッキ液を用
いて形成されたものであり、 前記第1の導電膜上の第2の導電膜が添加剤を含むメッ
キ液を用いて形成されたものであることを特徴とする半
導体装置。
(2) A semiconductor device having a multilayer conductive film of two or more layers formed by electrolytic plating on a conductive film to be plated covering an opening in an insulating film on a conductor, the bottom layer of the multilayer conductive film being formed by electrolytic plating. The first conductive film is formed using a plating solution containing no additives, and the second conductive film on the first conductive film is formed using a plating solution containing additives. A semiconductor device characterized in that it is a semiconductor device.
(3)導電体上の絶縁膜の開口部を被覆する被メッキ導
電膜の上に電解メッキにより形成された3層以上の多層
導電膜を有する半導体装置であって、前記多層導電膜の
最下層の第1の導電膜及び最上層の第3の導電膜が添加
剤を含まないメッキ液を用いて形成されたものであり、 前記第1の導電膜及び第3の導電膜の間に添加剤を含む
メッキ液を用いて形成されたものであることを特徴とす
る半導体装置。
(3) A semiconductor device having a multilayer conductive film of three or more layers formed by electrolytic plating on a conductive film to be plated that covers an opening in an insulating film on a conductor, wherein the lowest layer of the multilayer conductive film is The first conductive film and the third conductive film as the uppermost layer are formed using a plating solution that does not contain an additive, and the additive is present between the first conductive film and the third conductive film. A semiconductor device characterized in that it is formed using a plating solution containing.
(4)前記表面光沢剤を含むメッキ液を用いて形成され
た第2の導電膜が請求項1記載の方法により形成された
ものであることを特徴とする請求項2又は請求項3いず
れかに記載の半導体装置。
(4) Either claim 2 or claim 3, wherein the second conductive film formed using the plating solution containing the surface brightener is formed by the method according to claim 1. The semiconductor device described in .
JP31561190A 1990-11-20 1990-11-20 Semiconductor device and its production Pending JPH04187793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31561190A JPH04187793A (en) 1990-11-20 1990-11-20 Semiconductor device and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31561190A JPH04187793A (en) 1990-11-20 1990-11-20 Semiconductor device and its production

Publications (1)

Publication Number Publication Date
JPH04187793A true JPH04187793A (en) 1992-07-06

Family

ID=18067447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31561190A Pending JPH04187793A (en) 1990-11-20 1990-11-20 Semiconductor device and its production

Country Status (1)

Country Link
JP (1) JPH04187793A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714891A (en) * 1993-06-11 1995-01-17 Internatl Business Mach Corp <Ibm> Method and equipment for inspecting integrated circuit chip
JPH11315385A (en) * 1998-04-30 1999-11-16 Ebara Corp Plating method of substrate and its device
WO2001007687A1 (en) * 1999-07-26 2001-02-01 Tokyo Electron Limited Plating method and device, and plating system
JP2001152387A (en) * 1999-09-16 2001-06-05 Ishihara Chem Co Ltd Void-free copper plating method
JP2014508859A (en) * 2011-01-26 2014-04-10 エンソン インコーポレイテッド Filling via holes in the microelectronics industry
JP2015097251A (en) * 2013-10-09 2015-05-21 日立化成株式会社 Method of manufacturing multilayer wiring board
JP2015097253A (en) * 2013-10-09 2015-05-21 日立化成株式会社 Method of manufacturing multilayer wiring board
JP2015097254A (en) * 2013-10-09 2015-05-21 日立化成株式会社 Multilayer wiring board manufacturing method

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714891A (en) * 1993-06-11 1995-01-17 Internatl Business Mach Corp <Ibm> Method and equipment for inspecting integrated circuit chip
JPH11315385A (en) * 1998-04-30 1999-11-16 Ebara Corp Plating method of substrate and its device
WO2001007687A1 (en) * 1999-07-26 2001-02-01 Tokyo Electron Limited Plating method and device, and plating system
US6607650B1 (en) 1999-07-26 2003-08-19 Tokyo Electron Ltd. Method of forming a plated layer to a predetermined thickness
JP2001152387A (en) * 1999-09-16 2001-06-05 Ishihara Chem Co Ltd Void-free copper plating method
JP2014508859A (en) * 2011-01-26 2014-04-10 エンソン インコーポレイテッド Filling via holes in the microelectronics industry
US10103029B2 (en) 2011-01-26 2018-10-16 Macdermid Enthone Inc. Process for filling vias in the microelectronics
US10541140B2 (en) 2011-01-26 2020-01-21 Macdermid Enthone Inc. Process for filling vias in the microelectronics
JP2015097251A (en) * 2013-10-09 2015-05-21 日立化成株式会社 Method of manufacturing multilayer wiring board
JP2015097253A (en) * 2013-10-09 2015-05-21 日立化成株式会社 Method of manufacturing multilayer wiring board
JP2015097254A (en) * 2013-10-09 2015-05-21 日立化成株式会社 Multilayer wiring board manufacturing method
JP2015097252A (en) * 2013-10-09 2015-05-21 日立化成株式会社 Multilayer wiring board

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