JPH04186895A - Formation of circuit - Google Patents

Formation of circuit

Info

Publication number
JPH04186895A
JPH04186895A JP31442090A JP31442090A JPH04186895A JP H04186895 A JPH04186895 A JP H04186895A JP 31442090 A JP31442090 A JP 31442090A JP 31442090 A JP31442090 A JP 31442090A JP H04186895 A JPH04186895 A JP H04186895A
Authority
JP
Japan
Prior art keywords
layer
copper
plating
film
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31442090A
Other languages
Japanese (ja)
Inventor
Shuichi Ogasawara
修一 小笠原
Tomomichi Nihei
知倫 二瓶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP31442090A priority Critical patent/JPH04186895A/en
Publication of JPH04186895A publication Critical patent/JPH04186895A/en
Pending legal-status Critical Current

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Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To highly accurately form a precise circuit on an insulator by specifying the thickness of the first covering copper layer. CONSTITUTION:The first copper film is formed on a polyimide film by electroless copper plating. The thickness of the first copper film is maintained to be less than 1.0mum.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はプリント配線板(PWB) 、フレキシブルプ
リント回路(FPC)、テープ自動ボンディング(T 
A B)テープ等の絶縁体上に回路を形成することによ
って得られる電子部品の製造工程において回路の形状お
よび寸法精度を改良した回路形成法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to printed wiring boards (PWB), flexible printed circuits (FPC), tape automatic bonding (T
A B) This invention relates to a circuit forming method that improves the shape and dimensional accuracy of circuits in the manufacturing process of electronic components obtained by forming circuits on insulators such as tapes.

[従来の技術] PWB、FPCSTAB等の電子部品における回路形成
法は従来、絶縁体上に形成された銅被膜上ニエッチング
レジスト層を形成し、銅被膜の露出した部分を溶解除去
した後、レジスト層を除去する、いわゆるサブトラクテ
ィブ法が一般的であった。この方法の利点は工程が簡単
であること、経済性に優れることなど挙げられるが、最
大の欠点は回路をエツチングによって形成するため導通
層の断面が矩形にならず台形〜カマボコ状になる、いわ
ゆるサイドエツチングが発生することである。
[Prior Art] Conventionally, the circuit formation method for electronic components such as PWB and FPCSTAB involves forming a etching resist layer on a copper film formed on an insulator, dissolving and removing the exposed portion of the copper film, and then removing the resist. The so-called subtractive method, in which layers are removed, was common. The advantages of this method are that the process is simple and economical, but the biggest disadvantage is that because the circuit is formed by etching, the cross section of the conductive layer is not rectangular but trapezoidal or semicylindrical. This is because side etching occurs.

というのは、導通層が台形〜カマボコ状に変形した場合
、導通層の断面が矩形状の回路と同一の電気量を確保す
るためには、絶縁体に接している辺がより長くなる必要
があり、この場合前記のように導通層と導通層の間隔が
特に狭い場合は導通層と導通層の絶縁不良や短絡が発生
し易くなるからである。
This is because if the conductive layer is deformed into a trapezoidal or semicylindrical shape, the side in contact with the insulator needs to be longer in order to secure the same amount of electricity as a circuit with a rectangular cross section. In this case, if the distance between the conductive layers is particularly narrow as described above, poor insulation and short circuits between the conductive layers are likely to occur.

上記問題を解決する手段として考案された方法が、絶縁
体上に無電解めっき法あるいは引続き行われる電気めっ
き法等により 2〜5μmの厚みを持った第1の銅被膜
層を形成し、さらに銅被膜上の一部にレジスト層を形成
した後、レジスト層の形成されていない部分、即ち第1
の銅被膜層の露出した部分に無電解めっき法あるいは電
気めっき法によって所望の厚さまで銅めっきを行い第2
の銅被膜層を形成し、その後レジスト層を除去し、さら
に露出した第1の銅被膜層を、第2の銅被膜層をマスク
として除去することによって回路を形成する、いわゆる
アディティブ法である。このアディティブ法によって形
成された導通層の断面はほぼ矩形状であるため、前記の
ように導通層と導通層の間隔が狭くなっても絶縁不良や
短絡等の問題は発生しない。
A method devised as a means to solve the above problem is to form a first copper coating layer with a thickness of 2 to 5 μm on an insulator by electroless plating or a subsequent electroplating method, and then coat the insulator with copper. After forming a resist layer on a part of the film, the part where the resist layer is not formed, that is, the first
Copper plating is performed on the exposed portion of the copper coating layer to the desired thickness by electroless plating or electroplating.
This is a so-called additive method in which a circuit is formed by forming a copper film layer, then removing the resist layer, and then removing the exposed first copper film layer using the second copper film layer as a mask. Since the conductive layer formed by this additive method has a substantially rectangular cross section, problems such as poor insulation and short circuits do not occur even if the distance between the conductive layers becomes narrow as described above.

[発明が解決しようとする課題] 近年、電子部品の小型、軽量化にともない上記PWB、
FPC,TAB等の電子部品もより一層cv高Ef化が
要求されるようになり、回路形状においては導通層の幅
および導通層と導通層の間隔をより狭めることが要求さ
れるようになった。
[Problem to be solved by the invention] In recent years, with the miniaturization and weight reduction of electronic components, the above-mentioned PWB,
Electronic components such as FPCs and TABs are now required to have even higher CV and Ef, and in terms of circuit shapes, it has become necessary to narrow the width of conductive layers and the spacing between conductive layers. .

ところがこのアディティブ法であっても、サブトラクテ
ィブ法によるより、より矩形状の断面をもつ導通層を得
ることができるものの、やはり完全な矩形状導通層は得
られない。そのため、さらに導通層の間隔が狭まれば、
アディティブ法(こよって得られた導通層も絶縁不良あ
るいは短絡等の危険性が高まり、またこの危険性を回避
しようとすれば導通層の幅を極端に狭くする必要性か生
じ、技術的に困難になるばかりでなく必要な電気量が得
られなくなる。
However, even with this additive method, although it is possible to obtain a conductive layer with a more rectangular cross section than with the subtractive method, a completely rectangular conductive layer cannot be obtained. Therefore, if the distance between the conductive layers becomes even narrower,
Additive method (The conductive layer obtained by this method also increases the risk of poor insulation or short circuits, and to avoid this risk, it becomes necessary to extremely narrow the width of the conductive layer, which is technically difficult. Not only will it become a problem, but you will not be able to obtain the necessary amount of electricity.

本発明の目的は、絶縁体上に微細な回路を精度良く形成
するための回路形成法を提供することにある。
An object of the present invention is to provide a circuit formation method for forming fine circuits on an insulator with high precision.

[課題を解決するための手段] 上記目的を達成するための本発明の方法は、絶縁体の表
面に無電解めっき法によって、要すれば引続き行う電解
めっき法によって第1層の銅めつき被膜を形成した後、
該銅めつき表面の一部にレジスト層を形成し、レジスト
層の形成されていない該銅めっき被膜上に無電解めっき
法、あるいは電解めっき法によって第2層の銅めっき被
膜を形成した後、レジストを除去し、第2層の銅めっき
被膜をマスクとして第1層の銅めっき層を除去すること
による回路形成法において、前記第1の銅被膜層の厚み
を1.0μm以下とする点に特徴がある。
[Means for Solving the Problems] The method of the present invention for achieving the above object is to apply a first layer of copper plating to the surface of an insulator by electroless plating or, if necessary, by subsequent electrolytic plating. After forming the
After forming a resist layer on a part of the copper plating surface and forming a second layer of copper plating film on the copper plating film on which the resist layer is not formed, by electroless plating method or electrolytic plating method, In the circuit forming method by removing the resist and removing the first copper plating layer using the second copper plating film as a mask, the thickness of the first copper film layer is set to 1.0 μm or less. It has characteristics.

本発明において形成される第1の銅被膜層の厚みが1.
0μmを超える場合は、第1の銅被膜を溶解除去する際
に第2の銅被膜層によって形成された導通層も明らかに
侵食され導通層の断面が矩形とならず、信頼性の高い回
路を精度良く形成することはできない。
The thickness of the first copper coating layer formed in the present invention is 1.
If it exceeds 0 μm, the conductive layer formed by the second copper film layer will also be clearly eroded when the first copper film is dissolved and removed, and the cross section of the conductive layer will not be rectangular, resulting in a highly reliable circuit. It cannot be formed with high precision.

[作用] 本発明の方法により微細な回路を精度良く、かつ信頼性
高く形成できるのは、アディティブ法における第1の銅
被膜の厚みを1.0μm以下にすることにより第1の銅
被膜の溶解除去を迅速に行うことが可能となり、この際
第2の銅被膜によって形成された導通層の溶解は回路の
寸法精度に影響を及ぼすほど起こらないためである。
[Function] The method of the present invention enables the formation of fine circuits with high precision and high reliability by reducing the thickness of the first copper film to 1.0 μm or less in the additive method. This is because removal can be carried out quickly, and at this time, the conductive layer formed by the second copper coating does not dissolve to the extent that it affects the dimensional accuracy of the circuit.

本発明の方法によって得られる効果は、第1の銅被膜の
溶解除去処理に特に影響を受けない。即ち、溶解除去液
としては公知の銅を溶解する能力を持つもので差し支え
なく、一般的には、塩化第2鉄、塩化第2銅、過硫酸ア
ンモニウム、アンモニア、硫酸、過酸化水素水等を単独
で、あるいは2種以上含有する水溶液が良く用いられる
。また溶解除去条件は温度、時間等過不足の無いように
あらかじめ予備実験等で最適条件を求めておく必要があ
る。さらに溶解除去方法としては、基板を溶解液に浸漬
することによって行っても良いし、溶解液を基板にシャ
ワー状に吹き付けることによって行っても良い。
The effects obtained by the method of the invention are not particularly affected by the dissolution and removal treatment of the first copper coating. In other words, the solution for dissolution and removal may be any known solution capable of dissolving copper, and generally, ferric chloride, cupric chloride, ammonium persulfate, ammonia, sulfuric acid, hydrogen peroxide, etc. are used alone. or an aqueous solution containing two or more types is often used. Further, it is necessary to determine the optimum conditions for dissolution and removal in advance through preliminary experiments, etc., so that there is no excess or deficiency in temperature, time, etc. Further, the dissolution and removal method may be performed by immersing the substrate in a solution, or by spraying the solution in a shower onto the substrate.

[実施例] 鐘淵化学工業社製NPI−50型ポリイミドフィルム上
に無電解銅めっき法により厚さ0.5μmの第1の銅被
膜を形成した。その後肢銅被膜上に東京応化工業製PM
ER−HC600型フオトレジストを厚さ40μmに均
一に塗布し、70℃で30分間ベーキングした。その後
導通層幅40μm、導通層間隔40μmの回路が形成さ
れるように基板上にマスキングを施し、フォトレジスト
層に10100O/cm’の紫外線を照射した後、レジ
スト層の現像を行った。その後露出した銅の無電解めっ
き被膜上に以下に示す条件で銅の電気めっきを行い第2
の銅被膜を形成した。
[Example] A first copper coating having a thickness of 0.5 μm was formed on an NPI-50 type polyimide film manufactured by Kanekabuchi Chemical Industry Co., Ltd. by electroless copper plating. Tokyo Ohka Kogyo PM on the hindlimb copper coating
ER-HC600 type photoresist was applied uniformly to a thickness of 40 μm and baked at 70° C. for 30 minutes. Thereafter, the substrate was masked so that a circuit with a conductive layer width of 40 μm and a conductive layer interval of 40 μm was formed, the photoresist layer was irradiated with ultraviolet rays of 10,100 O/cm', and then the resist layer was developed. After that, copper electroplating is performed on the exposed copper electroless plating film under the conditions shown below.
A copper coating was formed.

(浴組成) CuSO4’5HiOH80g/I HzSO<          180 g/](電解
条件) 温度    25°C 陰極電流密度  :     3 A/dm”攪はん 
    :  空気攪はん 及びカソードロッカー 時 間          1時間 その後レジスト層の剥離除去を行い、露出した第1の銅
被膜を第2の銅被膜をマスクとして以下に示す条件で溶
解除去を行った。
(Bath composition) CuSO4'5HiOH80g/IHzSO<180g/] (Electrolysis conditions) Temperature 25°C Cathode current density: 3 A/dm Stirring
: Air agitation and cathode rocker time: 1 hour After that, the resist layer was peeled off and the exposed first copper film was dissolved and removed using the second copper film as a mask under the conditions shown below.

(浴組成) CLIClz・2HzO’    100 g/]NH
,CI           100 g/INH=C
Om           20 g/]29% アン
モニア水       °       400  m
l/1(溶解条件) 温度     25℃ 攪はん         な し 時間       25秒 該基板上に得られた導通層の断面は40 X  35μ
mの矩形状であり導通層間の絶縁不良、短絡等は観察さ
れなかった。
(Bath composition) CLIClz・2HzO' 100 g/]NH
, CI 100 g/INH=C
Om 20 g/] 29% ammonia water ° 400 m
l/1 (melting conditions) Temperature: 25°C No stirring Time: 25 seconds The cross section of the conductive layer obtained on the substrate is 40 x 35μ
m rectangular shape, and no insulation defects or short circuits between conductive layers were observed.

[比較例1] ポリイミド樹脂上に形成する第1の銅被膜層の厚みを1
.5μmとし、第1の銅被膜の溶解時間を90秒とした
以外は実施例1と同様の手順で回路を形成した。 得ら
れた導通層間に絶縁不良、短絡等は観察されなかったが
、導通層の断面はポリイミド樹脂に接している辺の長さ
は40μmであるものの、他の辺及び角の部分において
は著しく侵食され、直線性が喪失した。
[Comparative Example 1] The thickness of the first copper coating layer formed on the polyimide resin was 1
.. A circuit was formed in the same manner as in Example 1 except that the thickness was 5 μm and the dissolution time of the first copper film was 90 seconds. Although no insulation defects or short circuits were observed between the conductive layers obtained, although the cross section of the conductive layer had a length of 40 μm on the side in contact with the polyimide resin, there was significant erosion on other sides and corners. linearity was lost.

[比較例2コ ポリイミド樹脂上に形成する第1の銅被膜層の厚みを1
.5μmとし、第1の銅被膜の溶解時間を60秒とした
以外は実施例1と同様の手順で回路を形成した。 得ら
れた導通層間に絶縁不良、短絡等が多数観察された。
[Comparative Example 2 The thickness of the first copper coating layer formed on the copolyimide resin was 1
.. A circuit was formed in the same manner as in Example 1 except that the thickness was 5 μm and the dissolution time of the first copper film was 60 seconds. Many insulation defects, short circuits, etc. were observed between the resulting conductive layers.

[発明の効果コ 本発明の方法によれば、従来のアディティブ法によって
も困難であった微細な回路を絶縁体上に精度良く安定し
て形成することが可能となり、さ。
[Effects of the Invention] According to the method of the present invention, it is possible to stably form fine circuits on an insulator with high precision, which was difficult even with conventional additive methods.

らにこの方法によって得られた基板をPWB、FPCS
TAB等の電子部品として使用すれば、より高密度配線
が可能になるばかりでなく、高い信頼性が得られるなど
その効果は大きい。
Furthermore, the substrate obtained by this method is used for PWB and FPCS.
If it is used as an electronic component such as a TAB, it not only enables higher density wiring but also has great effects such as high reliability.

特許出願人 住友金属鉱山株式会社Patent applicant: Sumitomo Metal Mining Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims]  絶縁体の表面に無電解めっき法によって、要すれば引
続き行う電解めっき法によって第1層の銅めっき被膜を
形成した後、該銅めっき表面の一部にレジスト層を形成
し、レジスト層の形成されていない該銅めっき被膜上に
無電解めっき法、あるいは電解めっき法によって第2層
の銅めっき被膜を形成した後、レジストを除去し、第2
層の銅めっき被膜をマスクとして第1層の銅めっき層を
除去する回路形成法において、前記第1の銅被膜層の厚
みを1.0μm以下とすることを特徴とする回路形成法
After forming a first layer of copper plating on the surface of the insulator by electroless plating or, if necessary, by subsequent electrolytic plating, a resist layer is formed on a part of the copper plating surface to form a resist layer. After forming a second layer of copper plating film on the unused copper plating film by electroless plating or electrolytic plating, the resist is removed and a second layer of copper plating is formed.
A circuit forming method in which a first copper plating layer is removed using a copper plating layer as a mask, characterized in that the first copper plating layer has a thickness of 1.0 μm or less.
JP31442090A 1990-11-21 1990-11-21 Formation of circuit Pending JPH04186895A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31442090A JPH04186895A (en) 1990-11-21 1990-11-21 Formation of circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31442090A JPH04186895A (en) 1990-11-21 1990-11-21 Formation of circuit

Publications (1)

Publication Number Publication Date
JPH04186895A true JPH04186895A (en) 1992-07-03

Family

ID=18053136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31442090A Pending JPH04186895A (en) 1990-11-21 1990-11-21 Formation of circuit

Country Status (1)

Country Link
JP (1) JPH04186895A (en)

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