JPH04186880A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To achieve high image-quality liquid crystal display by laminating an a-Si film and an n<+> a-Si film which turn into a high resistor vertically inserted between isolated source gates and drain gates and forming a source electrode and a drain electrode on these n<+> Si films. CONSTITUTION:A gate insulation electrode 6, an active layer 5 induced by an a-Si film and an SiN film 8 are consecutively laminated and installed on a gate electrode 1 formed on a glass substrate 9. An a-Si film 7 which is isolated in the section of the SiN film 8 and serves as a high resistor vertically installed between source drains, is installed while an ohmic layer 4 is further installed, which is produced by an n<+> a-Si layer 7. A source electrode 2 and a drain electrode 3 are formed on the ohmic layer 4 by these n<+> a-Si layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to thin film transistors, and particularly to a thin film transistor suitable for use in active matrix driving of liquid crystals that require high voltage, and a method for manufacturing the same.

[Prior Art] In recent years, liquid crystals that do not use polarizing plates have become popular. Since this liquid crystal needs to be driven at a high voltage of about 60 V to 80 V, a thin film transistor (TPT) with a high breakdown voltage is required when driving the liquid crystal in an active matrix manner.

A high breakdown voltage TPT (Thin Film) that can be used to drive such a liquid crystal in an active matrix
As a conventional technology regarding mT transistor,
For example, [International Electron Device Meeting Digest 87, pp. 440-443 (IED: v187 DIGEST pp
.

440-443) J et al. is known.

FIG. 2 is a cross-sectional view showing the device structure of a high voltage TPT according to the prior art. In FIG. 2, 1 is a gate electrode;
2.3 is the source and drain electrode, 4 is the ohmic layer,
5 is an active layer (channel layer), and 6 is a gate insulating film.

The illustrated conventional TFT is a-5i (intrinsically amorphous)
A gate electrode made of Cr or the like is provided on one surface of the active layer 5 formed of a 5iN (silicon nitride) film via a gate insulating film 6 made of a 5iN (silicon nitride) film, and a gate electrode made of Cr or the like is provided on the other surface of the active layer 5.
A source electrode 2 and a drain electrode 3 made of Aff are provided via an ohmic layer 4 made of an i film.

In the TPT configured in this way, the L shown in the figure
l is the channel length where carriers are induced at the interface between the gate insulating film 6 and the active layer 5 (SiN/i layer interface) when the TPT is in the on state, and L2 is the channel length when the TPT is in the on state. This is a region where carriers are not induced at the SiN/1 layer interface, that is, a high resistance portion.

In this TPT, when in the on state, the drain-source current IDS is limited by the lateral resistance of the active layer 5 in the L2 region, and when in the off state, IDS is limited by the lateral resistance of the active layer 5 in the L1 region and the L2 region.
It is limited by the sum of the lateral resistances of the two regions.

[Problems to be Solved by the Invention] In the conventional technology having the device structure as described above, the L2 region, which is a high resistance portion, is formed using a photolithography process, so its accuracy is limited by process rules. In order to normally drive the above-mentioned liquid crystal, the length of the L2 region only needs to be about 1 .mu.m to 2 .mu.m. However, in order to form the L2 region with the above length, a process rule of 1 μm to 2 μm is required, and this requirement cannot be met when considering a large area TPT-LCD. Therefore, the conventional technique has the problem that it is only possible to form TPT with high precision over the entire large-area TF""-LCD.

In addition, in the conventional technology, due to the low selectivity between the intrinsic semiconductor layer (active layer 5) and the extrinsic semiconductor layer (ohmic layer 4) in the photolithography process, the intrinsic semiconductor layer that becomes the channel layer, i.e., the active Layer 5 can be formed extremely thin beyond a certain level, but since its sheet resistance cannot be made high, it is difficult to reduce the leakage current between the source and drain when the TPT is in the OFF state, and when the TPT is in the OFF state, it is difficult to・There is a problem that it is not possible to obtain a high off ratio.

The purpose of the present invention is to solve the problems of the prior art described above,
Provided is a thin film transistor that has a high breakdown voltage, a large on-off ratio, can be formed in a small area, and can be used in the display section of a TPT-LCD to enable a liquid crystal display with excellent display quality, and a method for manufacturing the same. It's about doing.

Means for Solving the Problems] According to the present invention, the object is to transform the element structure of TPT into a high resistance part (intrinsic semiconductor layer) inserted between the drain and source.
This is achieved by forming the element in the vertical direction and creating an element structure in which the drain-source current flows in the vertical direction.

The purpose is to (a) deposit and pattern a gate electrode on an insulating substrate; (b) thereafter form a gate insulating film and an intrinsic semiconductor film (active layer);
(c) After that, a step of depositing and patterning an insulating film; (d) After that, an intrinsic semiconductor film, an extrinsic semiconductor film (ohmic layer), and a source/drain electrode. The process includes sequentially depositing and sequentially patterning the source/drain electrodes, extrinsic semiconductor film, and intrinsic semiconductor film.
This is achieved by forming a structure.

[Function] By forming the high resistance part (intrinsic semiconductor layer) inserted between the source and drain in the vertical direction, it is no longer subject to precision constraints in the photolithography process, and the film thickness can be reduced. TPT with desired characteristics can be formed only by control. The film thickness can be controlled in units of several tens of angstroms, and the thickness can be controlled in units of tens of angstroms, with the thickness of 1 μm required for high resistance parts.
It is possible to precisely control the thickness of ~2 μm.

In addition, in the photolithography step during process processing, there is no need to selectively pattern the intrinsic semiconductor layer and the extrinsic semiconductor layer, and it is sufficient to selectively pattern the insulating film and the intrinsic semiconductor film. Since the selection ratio between the insulating film and the intrinsic semiconductor film is high, it is possible to reduce the thickness of the intrinsic semiconductor film forming the chatter layer to an extremely thin film thickness of about several hundred angstroms.

As a result, the present invention makes it possible to form a TPT requiring a voltage of about 60 to 80 ~' using the above-described device structure, and to reduce the drain-source current (2) when the TPT is on. , and the IDS when the TPT is off can be made small, that is, the on-off ratio can be made large.

[Example 2] A thin film transistor and a method for manufacturing the same according to the present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a sectional view showing the device structure of a TPT according to a first embodiment of the present invention. In Figure 1, 7 is a-S
i (intrinsic amorphous silicon) film, 8 a SiN film, 9 a glass substrate, and other symbols are the same as in FIG. 2.

As shown in FIG. 1, in the TPT according to the first embodiment of the present invention, on a gate electrode 1 formed on a glass substrate 9,
Gate insulating film 6, active layer 5 made of a-Si film, S]
``-3'' films 7 and n+a, which are formed by sequentially stacking films 8 and 1 to 1, and are separated by the SIN film 8 and become a high-resistance part inserted vertically between the source and drain. - An ohmic layer 4 made of a Si film is further provided, and these n″a-
A source electrode 2 and a drain electrode 3 are formed on an ohmic layer 4 made of a Si film.

The first embodiment of the present invention is formed by the following manufacturing process.

(a) A gate electric fence made of Cr or the like is deposited on the glass substrate 9 and patterned.

(b) Thereafter, a gate insulating film 6 made of a 5iN (silicon nitride) film and an a-Si (intrinsic amorphous silicon) film which will become the active layer 5 are sequentially deposited, and the a-Si film is patterned.

(C) After that, a SiN film 8 is deposited and patterned.

(cl) After that, an a-Si film 7, an n+a-Si (phosphorus-doped a-Si) film that will become the ohmic layer 4, an AQ electrode that will become the source electrode 2, and the drain electrode 3 are deposited in order. n''a-Si film, a-3] The film 7 is sequentially patterned to remove up to the SiN film 8, and the source region and drain region are separated on the gate electrode 1.

The device structure according to the first embodiment of the present invention described above is as follows:
a-S which becomes a high resistance layer inserted between the source and drain
Since the i-film 7 is formed in the vertical direction, the film thickness can be controlled in units of tens of angstroms without being constrained by the photolithography process.
It is possible to precisely control the thickness of about 2 μm.

In addition, in the photolithography step of the processing process, since the selectivity between the SiN film 8 and the active layer 5 made of the a-Si film is high, the a-Si film (active layer 5) which becomes the channel layer is
It is possible to form an extremely thin film with a thickness of about several hundred angstroms.

As a result, in the FT according to the first embodiment of the present invention, the source-drain current during ON operation flows vertically under the source electrode 2 and drain electrode 3, and the gate electrode 1
It flows laterally within the a-31 film (active layer 5) which becomes the upper channel layer, resulting in a small on-resistance. Furthermore, since the second active layer 5 is formed extremely thin, leakage current during off-operation can be extremely reduced.

That is, in the first embodiment of the present invention, the voltage is 60 to 80V.
By forming a TPT which requires a voltage of approximately
It is possible to reduce the IDS when the switch is off. Also, a is a high-resistance layer inserted between the source and drain.
-Since the Si film 7 is formed in the vertical direction, one element can be formed in a small area, and when this element is formed in an LCD, the pixel area can be increased.

FIG. 3 is a sectional view showing the device structure of a TPT according to a second embodiment of the present invention, and the reference numerals in the figure are the same as those in FIG. 1.

The second embodiment of the present invention uses an ohmic layer 4 made of a n''a-3] film, and has a source electrode 2 and a drain electrode 3 in ohmic contact with the a-3] film 7. This embodiment differs from the first embodiment of the present invention in this respect, but the structure is the same in other respects.

Formation of the element in this case is performed through the following steps.

(a) Gate electrode made of Cr on the glass substrate 9] is deposited and patterned.

(b) After that, gate insulating film 6 made of SiN film, a-S
An active layer 5 made of an i-film is sequentially deposited, and a second a-Si film is patterned.

(C) After that, an S 1N film 8 is deposited and patterned.

(d) After that, AR electrodes which will become the a-Si film 7, the source electrode 2, and the drain electrode 3 are sequentially deposited, and the Aff electrode and the a-
The Si film 7 is sequentially patterned to remove up to the S''N film 8, and the source region and drain region are connected to the gate electrode 1.
Separate at the top.

The TPT according to the second embodiment of the present invention described above is L″
a-Si film; since the secondary ohmic layer 4 is not used, the process is simplified; and for the same reason as in the device structure according to the first embodiment of the present invention shown in The thickness of the film 7 can be accurately formed to be about 2 μm to 2 μm, and the thickness of the active layer 5 made of the a-Si film can be formed to be about several hundred osygestros.

Therefore, when an i-FT that requires a voltage of about 60 to 80 V is formed using the above device structure, the drain-source current L) S when the TPT is on is increased.
Moreover, IDs when the TPT is off can be made small.

FIG. 4 is a sectional view showing the device structure of a TPT according to a third embodiment of the present invention, and the reference numerals in the figure are the same as those in FIG. 1.

The TPT according to the third embodiment of the present invention shown in FIG. In the second case, the same effect as in the case of FIG. 1 can be obtained. Note that this embodiment may be constructed by removing the a-Si film 7, which is a high resistance layer between the gate and drain.

Formation of the element in this case is performed through the following steps.

(a) A gate electrode 1 made of Cr or the like is deposited on a glass substrate 9 and patterned.

(b) After that, gate insulating film 6 made of SiN film, a-S
An active layer 5 made of an i film is sequentially deposited, and this a-Si film is patterned.

(C) After that, a SiN film 8 is deposited and patterned for the first time.

(d) After that, an a-Si film 7 is deposited and patterned to remove the a-Si film 7 on the source side or drain side.

(e) After that, the second patterning of the SiN film 8 is performed.

(f) After that, an ohmic layer 4 made of an n+a-Si film,
An AQ electrode that will become a source electrode 2 and a drain electrode 3 is sequentially deposited, and the AQ electrode and an ohmic layer 4 made of an n''a-Si film are sequentially patterned, and the source region and drain region are formed in the same manner as in the previous embodiment. Then, they are separated on the gate electrode].

In the device structure of the TFT according to the third embodiment of the present invention, the a-Si film 7, which is a high resistance layer, is inserted only on one side between the gate and drain or between the gate and source. The IDS at the time of oscillation can be made even larger than that of the first and second embodiments described above. Further, in this embodiment, the thickness of the a-Si film 5 can be made approximately several hundred angstroms for the same reason as in the first embodiment of the present invention shown in FIG.

Therefore, when a TPT that requires a voltage of about 60 to 80 V is formed using the above device structure, it is possible to increase the IDS when the TPT is on and to decrease the IpS when the TPT is off.

FIG. 5 is a cross-sectional view showing the device structure of a TPT according to a fourth embodiment of the present invention, and the reference numerals in the figure are the same as those in FIG. 1.

In the fourth embodiment of the present invention, the source electrode 2 and drain electrode 3 are provided on the surface of the glass substrate 9, and the gate electrode 1 is provided in the upper layer, that is, the layer structure of the first embodiment of the present invention described above. is configured in reverse, and in this case as well, the same effects as in the other embodiments can be obtained.

TP according to the fourth embodiment of the present invention configured as described above
T can be formed by the following steps.

(a) On a glass substrate 9, electrodes made of Cr etc. to become the source electrode 2 and drain electrode 3, an ohmic layer 4 made of an n+a-Si film, and an a-Si film 7 are sequentially deposited.
, the n+a-Si film 4, and electrodes made of Cr, etc. are sequentially patterned, and the portion that will become the gate region is removed down to the surface of the glass substrate 9, thereby separating the source region and the drain region.

(b) After that, an SjN film 8 is deposited and patterned.

(c) After that, an active layer 5 made of a-Si film, S]N film 6
are sequentially deposited to form a SIN film 6 and an active layer 5 made of an a-Si film.
are sequentially patterned.

(d) After that, a gate electrode 1 is deposited and patterned using AQ.

In the TPT device structure according to the fourth embodiment of the present invention, since the AQ electrode, which becomes the gate electrode 1, is provided at the top, it can be deposited relatively thickly, and the sheet resistance of the gate electrode 1 can be lowered. I can do it.

Further, in the fourth embodiment of the present invention described above, the thickness of the a-Si film 7 is set to about 1 μm to 2 μm for the same reason as the embodiment explained in FIG. 5
The thickness can be precisely controlled to about several hundred angstroms.

Therefore, when a TPT requiring a voltage of about 60 to 80 V is formed using the above device structure, it is possible to increase the IDS when the TPT is on and to decrease the IDS when the TPT is off.

FIG. 6 shows a TPT-LCD in which one of the above-mentioned embodiments of the present invention is used for the TPT-LCD.
FIG. 2 is a block diagram showing the overall configuration. In Figure 6,
20 is a signal side drive circuit, 21 is a scanning side drive circuit, and LC is a pixel using liquid crystal.

The illustrated TPT-LCD is a liquid crystal display device that does not use a polarizing plate. Normally, when a polarizing plate is not used, a voltage of 60 V to 80 V is required to drive the liquid crystal, so the TPT-LCD according to the present invention is used. By doing so, an image with good display quality can be obtained.

FIG. 7 is a plan view of an LCD when the TPT according to the present invention is applied to a TPT-LCD, and FIG. 8 is an A-A in FIG. 7.
' This is a cross-sectional view. In Figures 7 and 8, 10 is I
T○ film, 11 is alignment film, 12 is color filter, 13
1 is an SjN film, 14 is a liquid crystal, and other symbols are the same as in the case of FIG.

The second LCD uses the TPT of the present invention shown in FIG. 1 to drive a liquid crystal, and as shown in FIG. 7, the gate electrode 1 and source electrode 2 are arranged in a matrix. A TPT according to the present invention is formed at each intersection, and an ITO film 1 that drives the liquid crystal 14 and forms each pixel is placed on the drain 3.
0 is connected.

In the LCD using the TPT according to the present invention, T and F occupy the total area of each pixel surrounded by the gate electrode 1 and the source electrode 2 arranged in a matrix.
The area of T can be reduced, and an image with high display quality can be obtained with efficiency.

[Effects of the Invention] As explained above, according to the present invention, the TPT source
An intrinsic semiconductor layer with a thickness of 1 to 2 μm can be inserted between the drains without photolithography restrictions, and the channel layer can be made as thick as several hundred angstroms, making it possible to use TPT with a high on-off ratio. can be provided.

Therefore, by using a liquid crystal that does not use a polarizing plate and the TPT according to the present invention, a liquid crystal display device with excellent display quality can be provided.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a device structure according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing a device structure of a high voltage TPT according to the prior art, and FIGS. 3, 4, and 5 are A cross-sectional view showing the device structure of the second, third, and fourth embodiments of the present invention, and FIG. 6 is a block diagram showing the overall configuration of a TPT-LCD in which the liquid crystal is actively driven using the TPT according to the present invention. , FIG. 7 shows the TPT according to the present invention, TPT-
When applied to an LCD, FIG. 8 is a plan view of the LCD, and is a sectional view taken along the line AA' in FIG. 7. 1... Gate electrode, 2... Source electrode, 3...
...Drain electrode, 4...Ohmic layer, 5
... Active layer (channel layer), 6 ... Gate insulating film, 7 ... a-Si (intrinsic amorphous silicon) film, 8.13 ... SiN film , 9...Glass substrate, 1o...ITO film, 11...
・Alignment film, 12... Color filter, 14...
··liquid crystal. Figure 1 1: JT'”-to wo wolf! 6: so-to
: Drain skewer A 8: SiN layer 4: /V-mic layer 9: 〃'Las I4 anti 5: 5 layer Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6

Claims (1)

[Claims] 1. On the gate electrode, a gate insulating film, an a-Si film, a Si
An a-Si film, n^, in which N films are sequentially stacked and is inserted vertically between the source and gate and between the drain and gate, separated by the SiN film, and serves as a high resistance part.
A +a-Si film is further laminated, and these n^
A thin film transistor characterized in that a source electrode and a drain electrode are formed on a +a-Si film. 2. On the gate electrode, gate insulating film, a-Si film, Si
N films are sequentially stacked and provided, and an a-Si film serving as a high resistance portion is provided vertically between the source and gate and between the drain and gate, separated by the SiN film, and A thin film transistor characterized in that a source electrode and a drain electrode are formed on these a-Si films. 3. On the gate electrode, gate insulating film, a-Si film, Si
N films are sequentially stacked and provided, and a high resistance part is inserted vertically between the source and gate or between the drain and gate, separated by the SiN film part.
-Si film and n^+a-Si film are further laminated and provided, and on the other side, n^+a-Si film is provided, and these n^
A thin film transistor characterized in that a source electrode and a drain electrode are formed on a +a-Si film. 4. In the method for manufacturing a thin film transistor, (a) a step of depositing and patterning a gate electrode on an insulating substrate; (b) a step of sequentially depositing a gate insulating film and an intrinsic semiconductor film and patterning the intrinsic semiconductor film; ( c) After that, a step of depositing and patterning an insulating film, (d) After that, sequentially depositing an intrinsic semiconductor film, an extrinsic semiconductor film, and a source/drain electrode, and forming a source/drain electrode.
A method for manufacturing a thin film transistor, comprising a step of sequentially patterning an extrinsic semiconductor film and an intrinsic semiconductor film. 5. In the method for manufacturing a thin film transistor, (a) a step of depositing and patterning a gate electrode on an insulating substrate; (b) a step of sequentially depositing a gate insulating film and an intrinsic semiconductor film and patterning the intrinsic semiconductor film; ( c) thereafter, depositing and patterning an insulating film; (d) thereafter, sequentially depositing an intrinsic semiconductor film and source/drain electrodes, and sequentially patterning the source/drain electrodes and the intrinsic semiconductor film. A method for manufacturing thin film transistors. 6. In the method for manufacturing a thin film transistor, (a) a step of depositing and patterning a gate electrode on an insulating substrate; (b) a step of sequentially depositing a gate insulating film and an intrinsic semiconductor film and patterning the intrinsic semiconductor film; ( c) Then, a step of depositing an insulating film and patterning it for the first time; (d) A step of then depositing and patterning an intrinsic semiconductor film; (e) A step of then patterning the insulating film for a second time; (f) A method for manufacturing a thin film transistor, comprising the steps of: thereafter, sequentially depositing an extrinsic semiconductor film and source/drain electrodes, and sequentially patterning the source/drain electrodes and the extrinsic semiconductor film. 7. In the method of forming a thin film transistor, (a) sequentially depositing a source/drain electrode, an extrinsic semiconductor film, and an intrinsic semiconductor film on an insulating substrate, and sequentially patterning the intrinsic semiconductor film, extrinsic semiconductor film, and source/drain electrode. (b) Then, a step of depositing and patterning an insulating film; (c) Then, a step of sequentially depositing an intrinsic semiconductor film and a gate insulating film, and sequentially patterning the gate insulating film and the intrinsic semiconductor film; (d) After that. A method for manufacturing a thin film transistor, comprising the steps of depositing and patterning a gate electrode. 8. An active matrix liquid crystal display device driven by an active matrix, characterized in that the thin film transistor according to claim 1, 2, or 3 is used as a driving element.