JPH04186596A - Semiconductor integrated circuit containing data coincidence detector - Google Patents

Abstract

PURPOSE:To reduce power consumption by separately storing data in first and second memories, and selectively operating a second memory reading sense amplifier based on a detection output regarding coincidence. CONSTITUTION:Data indispensable for detecting coincidence is stored in a first memory 14, and data necessary after the coincidence of the data is detected is stored in a second memory 16. A sense amplifier 17 is selectively operated by the output of a detector 15 regarding a coincidence, and data is read from the memory 16. A cash memory decides a processing speed by delay of a coincidence detection of an address stored in a directory memory 14 and address input from an address bus. Accordingly, a predetermined high speed coincidence detector is used for the detector 15, and when only necessary sense circuit is operated in the sense circuit 17, a high speed operation can be performed almost without increasing an output delay time to a data bus 19, and power consumption is also low.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory, and in particular to a method for configuring a large-capacity, high-speed cache memory using a semiconductor integrated circuit, and data suitable for an associative memory used in the cache memory. This invention relates to a coincidence detection circuit.

[Conventional technology]

As a publicly known example related to this invention, JP-A No. 63-11
No. 9096, JP-A-59-231789, JP-A-60
-117495, etc. can be mentioned.

Traditionally, large-scale computer systems have been equipped with cache memory, which functions as a high-speed buffer memory and stores part of the program in main memory, between the central processing unit and main memory in order to speed up the system. It's dark.

The cache memory has two memory arrays. The first memory array uses an associative memory, and stores the physical address data (address on the main memory or a part thereof) of the stored data (a part of the above program) to be recalled from the main memory. Memory array No. 2 stores the stored data itself to be recalled. When searching for stored data in cache memory.

First, search data is input into the associative memory section and checked or compared with address data stored in the memory to determine whether they match or do not match.

On the other hand, in preparation for reading data, the stored data is output from the second memory array in parallel with the search of the associative memory, and when a match is confirmed by the search of the associative memory,
The configuration is such that the data read out in advance is sent to the outside.

As expected from the above configuration, data reading from the second memory array is performed in parallel with the search operation, so it is fast. However, since the output of the read data is controlled using the match detection result of the associative memory at the end, it is important for high-speed operation that the match data from the associative memory is outputted quickly. Furthermore, since the number of data outputs from the associative memory and the second memory array are large, the power consumption of the sense amplifier and output buffer circuit for data output increases, which increases the power consumption of the cache memory. This is a contributing factor.

Furthermore, since associative memory does not call up stored information by specifying an address but by comparing the stored contents, a match detection circuit is required to detect a match between the search data and the data stored in the associative memory. is necessary.

Regarding this coincidence detection circuit, an associative memory is known in which each memory cell is provided with an individual coincidence detection circuit for comparing search data and stored data (Japanese Patent Laid-Open No. 59-231789). (see official bulletin).

In addition, as another example, there is known a device equipped with a circuit that compares search data with a sense circuit for reading data from a memory cell (Japanese Patent Laid-Open No. 11749/1989).
(See Publication No. 5).

[Problem to be solved by the invention]

In the above conventional technology, the first challenge is to increase the speed of the match detection circuit of the associative memory, the second challenge is to reduce the power consumption of the cache memory, and the third challenge is to increase the memory capacity by reducing the memory cell area. It is. The method of providing a match detection circuit for each memory cell to detect a match between the search data and the data stored in the memory cell has the problem that the memory cell area per bit is large and a large amount of data cannot be held. there were.

In addition, in the case of ordinary memory cells that do not have a coincidence detection circuit for each memory cell, the contents of the memory cell are first read out by a sense circuit, and then coincidence detection is performed.
Since a MOS transistor sense amplifier is used, there is a problem in that the delay time is large and high-speed operation is not possible.

An object of the present invention is to provide a data coincidence detection circuit and a cache memory using the same for realizing a large-capacity and high-speed associative memory.

[Means to solve the problem]

First, in order to perform data match detection in the associative memory at high speed, the first problem is to divide the associative memory into two parts.The first memory part stores the data essential for data match detection, and the second
Data required after the match detection is stored in the memory section. By this division, the memory capacity of the first memory section becomes smaller than the capacity before division, so that speeding up can be achieved. In addition, the present invention improves the coincidence detection circuit to increase the speed as described below.

A cache memory includes an associative memory unit that compares stored data read on differential data lines connected to a plurality of memory cells with search data, and outputs predetermined information when both data match. Two pairs of bipolar differential amplifiers for amplifying the signals of the differential data lines are provided as this data coincidence detection circuit, and the current of the differential amplifiers is switched based on search data. This switching operation causes the output of the differential amplifier pair to be at a low level when the read storage data and search data match, and to be at a high level when they do not match. The output signal of this differential amplifier and the output signal of a similar differential amplifier from another data line are subjected to wired ○R logic and are used as a data coincidence detection signal. This signal is further amplified to a predetermined signal amplitude and outputs a low level when the data match is confirmed, and a high level when the data do not match. This circuit configuration makes it possible to detect data matches at high speed.

The second issue, to reduce power consumption, is to selectively operate only the circuits necessary for reading data out of the sense amplifier and output sofa circuit, which account for most of the power consumption, using the output of the data match detection circuit. Achieve with.

A cache memory includes a data match detection circuit that compares stored data read out to differential data lines connected to a plurality of memory cells with search data, and outputs predetermined information when both data match; The configuration is such that stored data is read from the second memory and its output is controlled by the output of the coincidence circuit.

In the present invention, the current supply to the sense amplifier for reading data of the second memory circuit is controlled by the output of the coincidence detection circuit, and the current is supplied only to the sense amplifier necessary for reading data, and the current to the sense amplifier that does not require reading is It's blocked. This reduces power consumption.

The third reduction in memory cell area is achieved by using a memory cell that occupies the smallest area and operates stably, which is used in a normal memory.

Furthermore, ease of testing, such as checking stored data and stored data after writing, is also required as one of the functions of the cache memory. For this purpose, it is desirable to be able to read out the data used for comparison in parallel with the -number construction. In the present invention, this function is realized by the following configuration. In cache memory, a readout circuit reads stored data read out to differential data lines connected to multiple memory cells, and compares the stored data with search data, and outputs predetermined information when both data match. This is a semiconductor memory equipped with a data number detection circuit. In the present invention, in this circuit,
A differential data line is created by switching the currents of two differential amplifier pairs whose inputs are connected to the differential data line or the common data line that transmits the signal, and whose output ends are cross-connected, using the search data. Signal Exclusive
A circuit for generating OR and Exclusive N OR signals, and the Exclusive OR and Exclusive
a circuit that amplifies the ve NOR signal as a differential signal;
A coincidence detection circuit is provided which outputs the logical sum of the Exclusive N OR outputs of the amplifier circuit using a wired OR circuit. This realizes a semiconductor memory that outputs the data coincidence detection output as well as the stored data read from the memory cell.

[Effect]

In the circuit of the above invention, the associative memory, which was conventionally composed of one memory, is divided into a first and second memory section, realizing high-speed data reading from the first memory section, and By increasing the speed of the ridge circuit, the output of the match detection circuit in the associative memory is generated at high speed. As a result, even if the sense amplifier of the second memory section is selectively operated using the coincidence detection signal, the operation speed of the entire associative memory does not decrease, that is, the delay time until data output does not increase. Therefore, the number of sense amplifiers operated for data reading is reduced, and power consumption reduction is achieved. Furthermore, this method uses memory cells for general-purpose memory, so it also has a feature that the memory cell area is small.

- To increase the speed of multiple output circuits, the signal of the differential data line connected to multiple memory cells is connected to the base of two pairs of bipolar differential amplifiers, and the current of the same pair of differential amplifiers is used as search data. The output of the differential amplifier pair is made to output a low level when the storage data read from the memory cell and the search data match, and a high level when they do not match. The circuit is configured to perform a wired OR circuit on the output signals from other data lines, amplify the signal to a predetermined signal amplitude, and output the amplified signal. In this circuit, the circuit provided for each differential data line has a simple circuit configuration consisting of only four bipolar transistors and one resistor, and furthermore, since each transistor can share two collectors, It occupies a small area, and the output of the -number circuit is composed of one stage of bipolar differential amplifier and one stage of current switch for waveform shaping of the wired OR circuit, so high-speed operation is achieved.

In addition, in the cache memory of the present invention, the output ends are cross-connected to directly transmit the stored data signal read out to the differential data line to which the plurality of memory cells are connected, or through a common data line that transmits the signal. is connected to the inputs of two pairs of differential amplifiers, and the currents of the two pairs of differential amplifiers are switched according to the search data to perform Exclusive OR and Exclusive OR of the signal of the differential data line and the search data.
Create an NOR signal and use this Exclusive
After amplifying the OR and Exclusive N OR signals as differential signals, they are led to a wired OR circuit that outputs a logical sum to generate a coincidence detection signal. Exclusive OR, Exclusive in parallel to this minus number output signal output
Output any of the ive NOR signals as a storage data signal, or write Exc in the output buffer circuit.
A circuit for restoring the original stored data using the search data obtained by lusive OR and exclusive N OR is installed, and the data is output after being restored to the original data. As a result, the coincidence detection circuit and the stored data output can be output in parallel at high speed and with low power consumption.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 shows an example of the configuration of a cache memory using the coincidence detection circuit of this embodiment. 10 is an address bus, 11 is an address register, and 12.13 is an address output from the address register.

14 is a directory storage section, 17 is a sense circuit, 18 is a data register, 19 is a data bus, and 20 is a signal indicating that stored data and search data match. In the cache memory, the speed is determined by the delay in detecting a match between the address stored in the directory storage unit 14 and the address input from the address bus, so if a high-speed multi-channel output circuit, which will be described later, is used for the match detection circuit 15, - Several building exit circuit 1
Even if only the sense circuits necessary for reading data in the sense circuit 17 are selectively operated by the output of the sensor 5, there is almost no increase in the delay time until the data is output to the data bus 19, and high-speed operation is achieved. A cache memory with low power consumption can be realized.

FIG. 15 is a circuit diagram of the sense circuit 17 of FIG. 1. The sense amplifier of the sense circuit 17 uses the output signal 20 from the coincidence detection circuit 15 to operate only the sense amplifier necessary for reading data, thereby reducing power consumption. This circuit is a bipolar circuit, so it can operate at high speed, and since data selection is done through a common collector connection, it has both sense circuit selection and data multiplexer functions, making it suitable for high-speed operation. It has characteristics. A detailed explanation will be given below according to the figures.

- A circuit 1410 surrounded by a dotted line is one of the memory arrays that includes a plurality of sense circuits 1411 for reading data. The sense circuit 1411 has a differential signal line eoll! that transmits a memory cell signal. eoo' is connected to the base of the transistor.

The transistors form a differential amplifier, and when the signal f, is at a high level, the data line e. . .

It is output as a current signal to the data line group 1405 according to e[lo'. Here, if fO is the output of the data detection circuit and is set to a high level, and all other lines such as fl are set to a low level, the data line group 1405 receives a current signal only from the memory array 1410 to which the signal of fo is supplied. It is output as a signal, amplified to a predetermined signal amplitude by the differential current signal sense circuit and output buffer circuit 1420, and output.

Even if f becomes a high level as a result of the data detection circuit, the data of the memory array of f is output in the same way. The circuit 1420 may be provided with an output control circuit or an output latch circuit included in a conventional bipolar circuit.

FIG. 5 shows an example of the configuration of a cache memory using the coincidence detection circuit of this embodiment. 10 is an address bus, 11 is an address register, 12 is an address output from the address register, and the number on the line shows the bit width of the address. 14 is an address storage unit whose inputs are compared; 14';
is a data storage unit corresponding to address 14, 15 is a matching detection circuit between personnel salary data and comparison data, and 17' is 14'
Detects and amplifies data read from circuit 1.
This circuit receives a match signal of No. 5 and controls data output. Reference numeral 21 denotes an address storage unit for controlling the output of the cache memory 16, and the output 21 and the output 20 of the circuit 17' are
' is checked in circuit 15'. As a result, the sense circuit 17 that detects and amplifies the data in the cache memory 16 is controlled, and only the sense amplifier that amplifies the data to be output is operated by the signal 20, and the data register 1
The data is output to the data bus 19 via the bus 8.

The following will mainly explain the differences compared to FIG. 1.

In this embodiment, the memory of the address translation unit corresponding to the directory storage unit 14 in FIG.
Memory 14 for match detection, which requires high-speed operation, is divided into 4'
The data reading time necessary for coincidence detection is shortened by reducing the memory capacity of the memory capacity and increasing the applied power if necessary, and the read data is sent to the coincidence detection circuit 15. By increasing the speed of this read data output and increasing the speed of the coincidence detection circuit 15, which will be described later, the delay time until the output of the coincidence detection circuit 15 is shortened. By shortening the delay time, among the sense circuits 17' which read out the data stored in the second memory group 14' using the output of the coincidence detection circuit 15, only the sense circuits which read out the data for which a data match has been confirmed are operated. Even with this configuration, it is possible to hardly cause an increase in the delay time until the data output 20' based on the coincidence detection result is output. That is,
This configuration has the feature that power consumption can be reduced because the number of operating sense amplifiers can be reduced without causing an increase in operating time. In this method, the percentage of sense amplifiers that operate is at most 50%, usually 10% or less, and power consumption is significantly reduced.

In this way, the memory of the address translation unit is divided into two types of memory groups, and the access time for the match detection memory, which requires high-speed operation, is reduced by reducing the integration density or increasing the input power, and the match detection circuit 15 Delay time until output is memory 1
If the delay time is set to approximately match the delay time until the data stored in 4' is output to the sense amplifier 17', it is only necessary to operate only the sense amplifiers necessary for retrieving data among the sense amplifiers 17'. The number of operating sense amplifiers is reduced, which has the effect of significantly reducing power consumption. Similar operation is performed by the coincidence detection circuit 15' and the sense amplifier 17.
Since the relationship with

Next, let us consider the delay time of the memory configuration shown in FIG.
A comparison with the configuration in Figure 6 is given below. In the circuit of FIG. 16, the delay time until the match data is output to the data bus 19 is the address access time of the memory 14, and the match detection circuit 15. Second
The delay time of the matching circuit 15' and the data register 1
This is the sum of delay times for controlling 8. On the other hand, in the configuration of FIG. 5, the address access time of the memory 14 and the match detection circuit 15. Sense amplifier 17', coincidence detection circuit 15', sense amplifier 17. It is given by the sum of the delay times of each data register. In other words, the delay time until the data output in the circuit of the present invention shown in FIG. be.

Generally, in a B1CMOS memory, when the integration density is reduced to 1/4, the address access time is reduced by about 20%. Therefore, in a 5 ns memory, by reducing the degree of integration to 1/4, the speed can be increased by about 1 ns.

On the other hand, since the sense circuit of the present invention using the same device has a delay time of about 0.5 ns, the delay time remains the same as a whole by canceling out the increase and decrease. It goes without saying that if the sense circuit shown in FIG. 15 is used in this circuit, higher speed and lower power consumption will be achieved.

FIG. 2 shows an embodiment of the directory storage section 14 of FIG. 1 and the address storage section 14, 14' of FIG. 5.

In FIG. 2, reference numeral 14 represents the comparison bit 14 of FIG. 5 as a memory cell array. Further, 15 indicates a coincidence detection circuit. Note that the third large capacity memory array in the cache memory is not shown here.

In the memory array 14, 1 is a data line load circuit;
M is a memory cell, W1 to W are word lines for selecting the memory cell M, and ai and al' are differential data lines for outputting data stored in the memory cell M. The circuit 15 is a more detailed version of the coincidence detection circuit shown in FIGS. 1 and 5. As will be described in detail later using FIG. 6, 2 is two pairs of current switch circuits, 3
is a voltage-current conversion circuit that converts the voltage output of the switch circuit 2 into a current output, a resistor that converts the current into a voltage, and an OR
This is a circuit made of bipolar transistors used for logic. bt+bi′ is differential search data, ci, c, +
is the differential output of EX-OR and EX-NOR of logic circuit 2,
Reference numeral 4 indicates a wired-ORed output line for calculating the logical sum of the outputs of the circuit 3, and 5 indicates an output circuit for converting the wired OR output into a logical amplitude output 6.

FIG. 6 shows detailed configurations of the data line load circuit 1, memory cell M, and coincidence detection circuit 15 shown in FIG. 2. In FIG. 6, in the data line load circuit 1, a potential approximately 0.5 V lower than the positive power supply potential Vcc is supplied to the source terminal 105, and a negative power supply potential Vee is supplied to the gate electrode terminal 106 in the data read state. In the state, the positive power supply potential Vc
P-type MO8)-transistor 101, 10 supplied with c
2 (hereinafter referred to as PMO5).

It is abbreviated as NMO8. ) and PMO3103, 104 whose data electrode terminals are supplied with a negative power supply potential, and the differential data a+, ar' are connected to a positive potential (Vcc-0, 5V).
It's pulled up to. Here, the reason why the voltage supplied to the source of PMO3 is lowered by about 0.5V from the positive power supply Vcc is to prevent the bipolar differential amplifier from operating in saturation.
Although it does not have to be 5V, it is convenient to set it at about 0.5V in view of the fact that the saturation margin is increased by this decrease and the margin for stable operation of the memory cell due to the decrease in the potential of the data line.

High resistance R11 and NMO5T- of the load of memory cell M
2 by M12, high resistance R21 and NMO8M22
The input and output of two inverter circuits are cross-connected to store differential data m, m', and the N
MO8TM13. M23 connects the storage nodes m and m' to the differential data lines at and at', respectively. Logic circuit 2 is search data bl.

NMO8T-201°202 controlled by bt'
and the differential data line at+at' and the differential output Ct.

C
4 outputs EX OR, and ci' outputs EX-LNOR. The current of C1, Ql' is resistance 304°30
5 into a voltage signal and guided to the base of a bipolar transistor (hereinafter abbreviated as BJT) 306. The emitter of the BJT 306 is connected to the wired-OR output line 4, and a low level is output only when data a1 and bi match. Here, wired OR output is used because it consumes less power and operates at high speed compared to other OR logic circuits.
The R circuit may be used or both may be used in combination.

Next, the operation of this embodiment will be explained using FIG. 3. Third
As shown in the figure, the potential level at each point is represented by ■. When word line W reaches logic level IL H+1,
NMO8M13.23 in the memory cell in FIG. 6 is turned on, and the voltage level of the differential data lines at, a, + becomes the voltage level of data m stored in memory cell M = "H", ■□V II ′, the differential data voltage becomes ■2□〉vat'. Search data b, =
11 For Hl+, NMOST2O1 is on and N
MOS T 202 is off, so the differential output C
The voltage level of I+Q+' is the differential data voltage V at +
■Corresponding to al′, the differential output voltage V e r <
V c t. Here, V C+ + V C1'
The voltage level of is determined by the product of the current flowing through resistors 303 and 304 and the resistance, and each current is distributed according to the amplitude of the long differential data line, so 1■□-V□' 1:30
Assuming mV, the current is distributed approximately 1=3. current to 0
．． 5mA, and the resistance is 2Ω, the potential of C1nch' becomes -0.25V and -0.75V, respectively.

The C1 signal is connected to the base of the BJT 306, and a low level is output to the output line 4.

The above shows the case where the stored data m is II H)+, but when the stored data m is ii L 11, cl, cl'
The differential current outputs of the BJT 306 have an inverse relationship, and the output line 4 of the BJT 306 becomes a high level. The relationship between the voltages of the differential outputs C+, c, + is as follows: storage data m and search data b.

There are four ways based on the logic.

(1) When rn = “HII, b, = 11 HII (match), Vat >Vat', 201 is on V CL < V c + ' (2) m = “H”, b, = II L II (3) m= flLJJ , b, = 1lB4!+
(mismatch), Vai<Vat', 201 is on Vc+>Vcl' (4) m=“L +1, b, = II L 11
When (match), Vat<Vat'', 202 is on V c * < V c ma' Here, as the logical value at differential data line al and differential output c1, , = II H71 is Va L > V
a l' and ct="H" as V c t >
Defining Vcs', the logic circuit 2 outputs the EX-OR logic of the differential data line a1 and the differential output b1 as the differential output ct. The current-voltage conversion circuit 3 converts the differential current output into voltage using resistors 304 and 305. That is, if the data m stored in the memory cell M and the search data b match, a current flows through the resistor 305 and the wired OR output outputs a low level, and when they do not match, no current flows through the resistor 305. , Wired OR
The output is high level. Therefore, unless the data m stored in the memory cell M and the search data b1 all match, the wired ○R output line 4 is at a high level, so that it operates as a -several sheet output circuit.

According to the embodiments described above, ordinary memory cells can be used in the storage data section to be detected by -M, so that large-capacity memory cells can be integrated on a chip.

Furthermore, since there is no need to read data from the memory cells using a sense circuit, there is an effect that the delay until the output of -several cells is small and the configuration is simple.

FIG. 4 shows a configuration example of the coincidence detection circuit 5 shown in FIGS. 1 and 2 and a reference voltage VR generation circuit used therein.

When the wired ○R output line 4 is lower than the reference voltage VR, the potential of the node 514 is about 0.5 V lower than the power supply, so the output 6 becomes 11 LD.

Conversely, when the output 4 becomes higher than the reference voltage VR, the voltage of the wired ○R output 4 can be used as the output of the logic circuit.

401 in FIG. 4 indicates a reference voltage VR generation circuit. 6th
The resistor 304 in the figure is divided into two to create resistors 515 and 516, and the constant current source 517 uses the same circuit as the constant current source 1 in FIG. Here, the transistor 520 is for aligning the voltage applied to the constant current source with that of the constant current source shown in FIG. 6, and may be omitted. Transistor 519 is resistor 5
This is a transistor for level-shifting the voltage divided into two by 15,516 and assigning it to the middle of the high and low levels of the wired ○R output line 4. With this reference voltage generation method, the potential difference between the data line pair at and a1' is 30rn.
Stable operation can be achieved even when V is extremely small.

FIG. 7 is a diagram showing the second invention of the present invention.

Since the illustration corresponds to FIG. 6, points different from FIG. 6 will be described in detail.

The point where the signal of the memory cell M is generated by the data line load circuit 1 to generate a potential difference between the data line pair ai, at' is the same as in FIG. The signals ai and at' are characterized by the configuration of 2' in which they are transmitted straight or across to CITC 1' according to the comparison data bl and bt'. bz'
is 'H' and bl is II L''', ai,
at' is connected to Cl and Ci', respectively, and when bi+'E)+' is reversed, at and a length' are connected to cl and C+', respectively. For this reason, EX-OR, EX-NOR logic is configured in the same way as the circuit in FIG. The output produces a signal similar to that shown in FIG.

This circuit has the feature that the conventional circuit configuration can be used as is by simply adding two PMO3s.

8 to 12 relate to a memory circuit that detects coincidence between stored data and search data, and also outputs the stored data itself.

FIG. 8 shows a storage data readout circuit 8 in addition to the circuit shown in FIG. 6.
This is a circuit with 10 added. This circuit is characterized by high-speed coincidence detection and high-speed output of stored data. Here, 801 and 802 are signal lines 803 and 8 that transmit stored data as a current signal to the output circuit.
04 is a bipolar transistor that constitutes a differential amplifier,
806 is its constant current source. If the current source 806 is turned on and off by the data line selection signal Y, the signal line 801°8
It is also possible to use common signal lines 02 as 911 and 912 in FIG. 9, which will be described later.

FIG. 9 shows that the output signal of circuit 3 of FIG. 8 is used as the input of the data readout circuit 910, and that the current source 806 of
is made up of NMO8903 and is turned on and off by the Y1 signal, for example, by making the signal Yi times high level, the signal from the data line pair ai, at' is transferred to the signal line 911.912.
The feature is that it is sent as a current signal. If the differential amplifier is operated by the Y1 signal in this way, the signal of the desired data line pair can be extracted to 911 and 912 by the Y1 signal, so the signal lines 911 and 912 can be shared to reduce the number of output buffer circuits. The number of elements and power consumption can be reduced. In addition, the circuit in FIG. 9 has an input amplitude of 0.3 V or more because a signal amplified by one stage by a differential amplifier is connected to the bases of transistors 903 and 9011 compared to the circuit in FIG. 8. , signal lines 901, 90
2 has the characteristic that there is no current shunting.

FIG. 10 shows another embodiment suitable for the circuit 910 of FIG. In circuit 910, exclude O1+C1'
Since the ive OR and Exclusive N OR signals are output, if the data is output as is, the output of the stored data will change depending on the search data. In order to remove the influence of this search data, search data b, □.

It is characterized in that the signal of CIT Ci' is returned to stored data by the signals b and □' and then output to the signal line 1002.100.3. Here, b, 1. b, □′ is bt.

b1' may be used, but in order to avoid increasing the delay time due to an increase in the parasitic capacitance of the bi and bt' signal lines,
It is desirable to supply it after passing through a buffer circuit. Since the circuit 1010 is a well-known current detection circuit, a description thereof will be omitted.

FIG. 11 shows another embodiment of the circuit from the sense amplifier of the memory circuit to the input of the output buffer circuit which outputs the output of the data coincidence detection circuit and the output of the stored data in parallel. Differential data line pair at.

aI′ is ExClusjve OR, Exclusi
The current is detected by one circuit 1010 via the ve N OR circuit 111o, and a coincidence detection signal is generated at 4' by ORing the wire 1, and the differential output of the circuit 1010 is again Ex
exclusive OR.

It is characterized by taking Exclusive N OR and reproducing stored data. According to this circuit, signal line 1
Even if the capacitance attached to the wiring increases by extending 101.1102, the increase in delay time is small, so the output line 4' of the wired OR can be placed at a desired position.

FIG. 12 shows another embodiment of the circuit from the sense amplifier to the input of the output buffer circuit of a memory circuit that outputs the output of the data coincidence detection circuit and the output of stored data in parallel. The circuit that receives the signals of the differential data lines a l and a +' and obtains the output 1206 is the same as the sense amplifier to output buffer circuit of the B1CMOS memory. The output of the current detection circuit of this circuit is PMOS 1201. l 2Q2
It is characterized in that it is led to the bias data transistor 1207 and connected to the wired ○R signal line 4'. According to this circuit, P Iv
Since a coincidence signal can be generated by adding two iOSs and one bipolar transistor, simple and high-speed operation can be achieved. Hey, in this example, P
I connected the MOS source to the output terminal of the current detection circuit, but
It may be connected to the output terminals 1205 and 1206 of the differential amplifier.

FIG. 13 shows another embodiment of the circuit of FIG.

Wj, at, and M are the same as in FIG. First, data coincidence detection using this circuit will be explained. At this time, WE
If ' is the negative power supply Vee and the WE terminal is the positive power supply Vcc, then PMO81303, Yu304, ], 305°13
06.1309.1310 is on state, 1,307°1
308 is in an off state. Here, if node m of the memory cell is at high level and m is at low level, PM
A current flows through the O31306, and the voltage drop at that time is determined by the characteristics of the diode-connected PMO31306. The voltage drop of this PMOS 1306 is caused by PMOS 13 because if bl is at a high level, PMO 31311 is off.
The potential of a, which is at a high level with no current flowing through it, is supplied through the PMO 81312 which is in the on state. Therefore, the PMOS 1315 is turned off, the base of the bipolar 1324 becomes a low level, and a low level is output at 4'.

When the high and low levels of m and m are switched, PMOS13
Current flows to 0S, a becomes low level, and PMO81
315 is turned on and 4' becomes high level. That is, when ai and bl are at high level, 4' outputs a low level, and when a is at low level and bI is at high level, 4'
A high level is output. If we consider the same thing when b is low level, then a, and are high level.

It can be seen that when there is a match at a low level, 4' is at a low level, and when there is a mismatch, 4' is at a high level. In other words, if 4' is wired ○R line and OR logic is performed with similar outputs from other differential signal lines such as a++ a, then all the signals obtained by OR logic are obtained. The coincidence detection circuit is changed so that a low level is output to 4' only when there is a match (all the als and bIs are the same). Here, PMO51301, 1303 is a
This is provided to maintain the high level of l + a l' at a constant value. PMO31301 is 1305.130
6, the gate width is set sufficiently large and the gate width is diode-connected, and a voltage is generated by passing a small current through the NMO81327. The circuit 1350 is al,
This is a circuit for receiving the signal of al' and outputting the stored data.PMO813], 4.1313 is a circuit that, like 1315, turns on and off depending on the level of am and ai' to obtain an output 1320. Here, V L e is a constant voltage supply terminal for flowing a constant current to the NMOs 31325, 1326, and 1327.

According to this circuit, matching signal detection requires NMO3132
Since only the current flows to 5,1326, power consumption is significantly reduced.

In the data writing state, PMO51304゜1303
A write operation is performed by turning off the transistors and lowering the potentials of al and at to a predetermined potential.

FIG. 14 shows another embodiment that operates similarly to FIG. 13. Since signals are exchanged using the differential data line al, the load circuit is simplified. Since the operation is clear from the explanation of the operation of the circuit shown in FIG. 13, the explanation will be omitted. Here, NPN bipolar transistors may be used in place of the NMOs 81401-1404.

In the above embodiment, a circuit using a bipolar transistor as a sense amplifier and an NMO3 as a current source has been described, but it goes without saying that each may be replaced with an NMO3 or NPN bipolar transistor. especially,
When bipolar transistors are used in low current circuits, it is possible to reduce the amplitude of control signals, which has the effect of realizing a circuit suitable for high-speed operation. It is also possible to realize a circuit using the same concept by configuring the memory cell with PMO8 and a high resistance and inverting the voltage of the peripheral circuit and the polarity of the MOS transistor, or it is also possible to use a CMOS cell. It is.

〔Effect of the invention〕

According to the present invention, ordinary memory cells can be used in the storage data section, which includes several memory cells, so that one large-capacity memory cell array can be integrated on one chip. In addition, when comparing the memory cell data with the search data, it is possible to output -number of data without using the sense circuit to read the data line through which the memory cell outputs data, so the delay time until the output of -number of data is This has the advantage of short length, simple configuration, and low power consumption.

[Brief explanation of drawings]

1 and 5 are system configuration diagrams to which the present invention is applied, FIG. 2 is a circuit diagram of an embodiment relating to the directory storage unit 14 of FIG. 1 and the match detection circuit, and FIG. 3 is a circuit diagram of an embodiment of the circuit of FIG. Operation waveform diagram, FIG. 4 is a circuit diagram showing the reference voltage generation circuit of FIG. 1, FIGS. 6 to 15 are circuit diagrams showing embodiments of the present invention, and FIG. 16 corresponds to FIG. 5. It is a conventional system configuration diagram. 1...Data line load circuit, 12...Logic circuit, 3...
Current conversion circuit, 4 wired ○R output line 1M memory cell, ai, at''' differential data line, b l +
b i'...Differential search data, Ct, Ct' -I
Ex-OR. T j fig'Vj5 fig. 15 Figure

Claims (1)

[Claims] 1. In an associative memory that detects a match between stored data and search data and outputs the matched data, a first memory that stores data essential for detecting a data match and a data Separate the second memory that stores the data required after a match is detected, and select a sense amplifier for reading data from the second memory based on the output of the detection circuit regarding the match. A semiconductor memory with a built-in associative memory that is characterized by reduced power consumption by operating in a consistent manner. 2. The semiconductor memory according to claim 1, in which the output of the associative memory is used to control the data output of a third large-capacity memory incorporated on the same chip, wherein the sense amplifier of the third memory is associative. A semiconductor memory with a built-in associative memory characterized by reduced power consumption by selectively operating based on the output of the memory. 3. In a data match detection circuit of a semiconductor memory that compares stored data read out to a differential data line connected to a plurality of memory cells with search data and outputs predetermined information when both data match, The signal of the differential data line is connected to the bases of two pairs of bipolar differential amplifiers, and the current of the differential amplifier pair is switched based on the search data, and when the read stored data and the search data match, The output of the differential amplifier pair is set to a low level, and when there is a mismatch, the output is set to a high level. This output signal and the output signal from the other data line are wired ORed and then amplified to a predetermined signal amplitude. A data coincidence detection circuit for a semiconductor memory, characterized in that it outputs data as follows. 4. A reading circuit for the stored data read out to the differential data line to which a plurality of memory cells are connected compares the stored data with the search data and outputs predetermined information when both data match. In a semiconductor memory equipped with a data coincidence detection circuit, the current of two differential amplifier pairs whose inputs are connected to the differential data line or the common data line that transmits the signal, and whose output terminals are cross-connected. a circuit that generates Exclusive OR and Exclusive NOR signals between the search data and the signal on the differential data line by switching according to the search data;
1. A semiconductor memory having a built-in data coincidence detection circuit, characterized in that it includes a circuit that amplifies a comprehensive NOR signal as a differential signal, and a wired OR circuit that outputs a logical sum of the amplification circuit.