JP3094159B2 - Cache memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device, and more particularly to a cache memory device suitable for an associative memory used for a large-capacity, high-speed cache memory or the like by a semiconductor integrated circuit. . 2. Description of the Related Art A large-scale computer system has a cache memory which functions as a high-speed buffer memory by storing a part of a program in a main memory between a central processing unit and a main memory in order to increase the speed. Is placed. The cache memory has two memory arrays. The first memory array uses an associative memory, and stores physical address data of storage data (part of the program) to be called from the main memory, and the second memory array stores the storage data itself to be called. Is stored. In the search, the search data and the address data are collated or compared, and if they match, the corresponding storage data is output from the second memory array. Now, since the associative memory calls the storage information not by specifying the address but by comparing the stored contents, it is necessary to detect the match between the search data and the storage data in the associative memory. Is required. With regard to this coincidence detection circuit, a conventional associative memory is known which has a coincidence detection circuit for each memory for comparing search data with stored data (Japanese Patent Laid-Open No. 59-231789). No.). Further, as another example, there is known a device provided with a circuit for comparing data with search data by a sense circuit for reading data from a memory cell (Japanese Patent Application Laid-Open No. 60-117495). [Problems to be Solved by the Invention] In the above-mentioned prior art, in the former case, a match detection circuit for detecting the match between the search data and the storage data of the memory cell is provided for each memory cell. However, there is a problem that the memory cell area is large and large-capacity data cannot be held. In the latter case, first, in the case of using a normal memory cell without having a coincidence detection circuit for each cell, first,
Since the coincidence is detected after the contents of the memory cell are read by the sense circuit, there is a problem that the delay time is long and high-speed operation cannot be performed. JP-A-61-113191 and JP-A-58-212698 disclose those provided with a coincidence detection circuit. This is a method of arranging a match detection circuit for detecting an error in a memory array, and cannot be applied to a method of arranging a match detection circuit outside a memory cell array. SUMMARY OF THE INVENTION It is an object of the present invention to provide a cache memory device capable of realizing a large-capacity and high-speed associative memory capable of performing matching between stored data and search data outside a memory cell array. [Means for Solving the Problems] In order to achieve the above object, a representative embodiment of the present invention includes two inverters (M ₁₁ , M ₁₂ , M
₂₁ , M ₂₂ ), a plurality of flip-flop type memory cells (M) in which inputs and outputs are cross-connected are arranged in a row direction and a column direction, and a pair of input / output nodes of each flip-flop type memory cell are arranged in a column direction. A plurality of complementary data line pairs (ai,
) And a plurality of control nodes of each flip-flop type memory cell connected to a plurality of word lines (Wi) arranged in the row direction, respectively, and a search data (bi). , ▲ ▼) and a match detection circuit (15) for detecting a match between read data from each memory cell read via the complementary data line pair (ai, ▲ ▼) of the memory cell array (14). The match detection circuit (15) includes a complementary signal input pair (ai, ▲ ▼) and a complementary search input pair (b
i, ▲ ▼) and a complementary output pair (ci, ▲ ▼) are arranged for each complementary data line pair (ai, ▲ ▼), and the complementary data line pair of the memory cell array (14) is provided with the complementary data line pair. The signal input pair (ai, ▲ ▼) is connected, the positive-phase signal input (ai) of the complementary signal input pair (ai, ▲ ▼) and the positive-phase output (ci) of the complementary output pair (ci, ▲ ▼). And a first MOS transistor (201) having a source / drain path connected between the first and second MOS transistors (201), and an inverted-phase signal input (a) of the complementary signal input pair.
a second MOS transistor (202) having a source / drain path connected between i) and the opposite-phase output (▲) of the complementary output pair; and the positive-phase signal input (ai) of the complementary signal input pair. ) And the opposite phase output of the complementary output pair (▲ ▼)
Third MOS with source / drain path connected between
A fourth MOS transistor having a source / drain path connected between the transistor (203) and the negative-phase signal input (▲) of the complementary signal input pair and the positive-phase output (ci) of the complementary output pair; A transistor (204), the first MOS
The gate of the transistor (201) and the second MOS transistor (202) and the third MOS transistor (203)
The gate of the fourth MOS transistor (204) and a plurality of logic circuits (bi,,) driven in opposite phases by the complementary search input (bi, bi) as the search data supplied to the complementary search input pair. 2), a first bipolar transistor (301) and a second bipolar transistor (30) whose emitters are commonly connected.
2), the bases of the first bipolar transistor (301) and the base of the second bipolar transistor (302) are arranged for each complementary data line pair (ai, ▲ ▼). A plurality of differential transistor pairs (3) connected to the positive phase output (ci) and the negative phase output (▲ ▼) of the complementary output pair (ci, ▲) of the logic circuit (2); A wired OR that outputs a logical sum of a signal of a collector of one (302) of the first bipolar transistor (301) and the second bipolar transistor (302) of the plurality of differential transistor pairs (3). And a circuit (5). [Operation] According to the present invention, the original object can be achieved for the following reasons. That is, the detection of coincidence between the search data (bi, ▲ ▼) and the read data from the memory cell read via the complementary data line pair (ai, ▲ ▼) of the memory cell array (14) is performed by the memory cell array (14). A pair of complementary data lines (a, ▲) provided separately outside the memory cell array (14).
▼) is performed by the coincidence detection circuit (15) connected to each memory cell array (14), so that the coincidence detection is performed inside each memory cell (M) of the memory cell array (14). Occupied area can be greatly reduced. Further, when detecting a match between the search data (bi, ▲ ▼) and the read data from the memory cell (M), the data read out via each complementary data line pair (ai, ▲ ▼) of the memory cell array (14). The read data from the memory cell to be read is directly supplied to the complementary signal input pair (ai, ▲ ▼) of each coincidence detection circuit (15) without voltage amplification by the sense circuit as in the related art. For this reason, even when the match between the search data (bi, ▲ ▼) and the read data from the memory cell (M) is detected, it is necessary to set each complementary data line pair (ai, ▲ ▼) of the memory cell array (14). The output data and the search data (bi, ▲ ▼) are collectively detected, and the detection result can be output at high speed via the wired OR circuit (4). Moreover, the complementary output pair (ci, ▲) from which the coincidence detection signal of the coincidence detection circuit (15) is obtained is a differential transistor pair (3) using bipolar (301, 302) having a voltage / current conversion function with high sensitivity. Are connected, the differential transistor pair (3) using the bipolars (301, 302) effectively executes the voltage amplification function of the conventional sense circuit.
As a result, the delay time can be reduced and a high-speed operation can be realized as compared with the conventional case where the voltage read out from the memory cell is amplified by the sense circuit prior to the match detection. Next, an embodiment of the present invention will be described with reference to the drawings. First Embodiment (First Invention) FIG. 2 shows an embodiment according to the first invention. In FIG. 2, reference numeral 14 denotes a memory cell array of the associative memory;
Indicates a coincidence detection circuit. Here, the second memory array in the cache memory is not shown. In the memory cell array 14, 1 terminating resistor, M memory cells, W ₁ to _W-m word lines for selecting the memory cell M, a _{i, i} is for outputting the stored data in the memory cell M, The complementary data lines are shown. In the match detection circuit 15, reference numeral 2 denotes a logic circuit composed of EX-OR (exclusive OR) or EX-NOR (match logic).
Is a current conversion circuit for converting the output of the logic circuit 2 into a current output, b _i , _i are complementary search data, c _i , _i are complementary outputs of the logic circuit 2, and 4 is a logical sum of current outputs of the respective current conversion circuits 3 Reference numeral 5 denotes an output circuit for converting the wired OR output into a logical amplitude output 6. Next, FIG. 1 shows a detailed configuration of the memory cell M and the coincidence detecting circuit 15 shown in FIG. In FIG. 1, a terminating resistor 1 is composed of diode-connected NMOS transistors (hereinafter abbreviated as NMOST) 101 and 102, and the complementary data lines a _i and _i are pulled up to a power source. The memory cell M is a PMOS transistor (hereinafter abbreviated as PMOST) M.
₁₁ and NMOST-M _12, and stores the complementary data m by cross connecting inputs and outputs of the two inverter circuits by the PMOST-M ₂₁ and NMOST-M _22, is controlled by the word line W _j NM
Complementary data m stored in OST-M _13, M _23, and the complementary data line
a _i and _i are connected to each other. Logic circuit 2, the complementary data lines a _i in NMOST201,202 controlled by the search data b _i,
i and the complementary outputs c _i , _i are connected to each other, and the complementary data lines a _i , _i are connected to the complementary outputs _i , c _i via NMST-203, 204 controlled by the inverted search data _i . The current conversion circuit 3 is constituted by a differential pair of bipolar transistors 301 and 302 and a constant current source 303 having complementary outputs c _i and _i as complementary inputs, one connected to a power supply, and the other connected to an output line 4 that performs wired OR. . Next, the operation of this embodiment will be described with reference to FIG. As shown in FIG. 3, the voltage level at each point is represented by V. When the word line _Wj goes to the logic level "H", the NMOS
T-M ₁₃ and M ₂₃ are turned on, and the voltage level of the complementary data lines a _i and _{i is} the voltage level of data m = “H” stored in the memory cell M, V _m , ＶV ^- _m ▼ (V _m> ▲ V ^- _m ▼) to Hikitsu path is by the complementary data voltage V _ai> ▲ V ^- _a ▼ become. Search data b
_{If i} = "H", NMOST 201 and 202 are turned on,
_{i =} because it is "L", NMOST203,204 is turned off, the complementary outputs c _i, the voltage level of the _i complementary data voltages VA _i, V _i
To Hikitsu path is to be complementary output voltage VC _i> V _i. bipolar transistor 3 having c _i , _i as complementary inputs
In the differential pair 01 and 302, 301 is turned on and 302 is turned off, and the current of the wired OR output 4 is stopped. Search data b _i
= "L", NMOSTs 201 and 202 are off, 203 and 204
Is turned on, the voltage level of the complementary output c _{i, i} is the complementary data voltage V _i, the complementary output voltage path is Hikitsu to Va _i Vc _i <V
_i , and a current flows through the output line 4. In the above, the case where the storage data m = “H” is shown, but when the storage data m = “L”, the complementary data voltage is Va _i <V
The operation is the reverse of the case of _i . Aspects of the complementary output voltage is considered four cases the logic value of the stored data m and retrieval data b _i. (1) m = _{"H", b i = Va i> V} i when "H", 201, 202 on _{→ Vc i> V i (2} ) m = "H", b _i = Va _i when "L"> V _i , 203,204 on → Vc _i <V _i (3) When m = “L”, b _i = “H” Va _i <V _i , 201,202 on → Vc _i <V _i (4) m = “L” "when b _i =" L "Va _i> V _i, where 203 and 204 on → Vc _i> V _i, the complementary data lines a _i, a logical value of a complementary output c _i, a _i = a" H " Va _i > V _i , and C _i = “H”, V c _i > V
When defined as _i, the logic circuit 2 is an output of the complementary output c _i the EX-NOR logic complementary output b _i and the complementary data line a _i.
When current conversion circuit 3 is a complementary output voltage Vc _i> V _i, turns off the current of the output line 4, and electric current when Vc _i <V _i reversed. That is, if the stored data m of the memory cell M and the search data b _i match, the wired OR output current is turned off, current flows if a mismatch. Therefore, if the output line 4 of the current conversion circuit 3 is wired-ORed,
As long as the data m and the search data b _i of the stored memory cells M does not match all the current flows through the wired-OR output line 4, and operate as coincidence detection circuit. As described above, according to the present embodiment, since a normal memory cell can be used for the storage data unit for detecting the coincidence, a large-capacity memory cell can be held. Further, in comparing the data of the memory cell with the search data, there is no need to read out the data of the memory cell using the sense circuit, so that there is an effect that the delay until the match detection is small and the configuration is simple. FIG. 4 is a configuration example of the coincidence detection output circuit 5. The wired OR output line 4 is connected to a resistor 501 through a cascode of a bipolar transistor 500, performs current-voltage conversion, and performs a level shift by a bipolar transistor 507 and a constant current source 508, and a level conversion circuit by MOS transistors 509 to 512. Input. Diodes 502 and 503 clamp node 513 to provide a voltage amplitude of 2V _BE . This causes the level-shifted node 514 to be two
The center voltage under V _BE, with amplitudes of the upper and lower V _BE. The series circuit of the diodes 504 and 505 and the constant current source 506
It becomes a bias of 0 and a reference voltage of the level conversion circuits 509 to 512. If there is no current on wired OR output line 4, node 513
Is pulled up to the power supply by the resistor 501, and the potential of the node 514 is lower than the power supply by V _BE . Node 515 is 2V from power supply
_{Since the} potential is lower than _BE, the output 6 of the level conversion circuits 509 to 512 becomes “L”. Conversely, when a current flows through the output 4, a voltage drop occurs due to the resistor 501, the node 513 is clamped by the diodes 502 and 503, and the node 514 is 3V _BE from the power supply.
The lower potential is set. Therefore, the level conversion circuit 509
The outputs 6 to 512 become “H”, and the current of the wired OR output 4 can be output as a logic amplitude output. Next, FIG. 5 shows a configuration example of a cache memory using the coincidence detection circuit of this embodiment. 10 is an address bus, 11 is an address register, 14 is a directory storage unit, 16 is a data storage unit, 15 is a match detection circuit, 17 is a sense circuit, 18 is a data register, 19 is a data bus, and 20 is a cache hit. Is a signal indicating the following. In the cache memory, since the speed is determined by the delay of the coincidence detection between the address stored in the directory storage unit 14 and the address input from the address bus, the use of this embodiment makes it possible to implement a high-speed access cache memory. . [Effects of the Invention] According to the present invention, matching between storage data and search data is performed outside the memory cell array, so that the memory cell array can be configured with a large capacity, and the storage data and search data can be stored. Even when comparing
The match between the data output for each complementary data line pair and the search data is detected collectively, and the detection result is output at high speed by a wired-OR circuit. This can contribute to an improvement in data processing speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an overall configuration diagram of FIG. 1, FIG. 3 is an operation waveform diagram of the circuit of FIG. FIG. 4 is a circuit diagram showing the output circuit of FIG. 2, and FIG. 5 is a system configuration diagram to which the present invention is applied. , 1 ... Terminating resistor, 2 ... Logic circuit, 3 ... Current conversion circuit, 4 ... Wired OR output line, M ... Memory cell,
a _i , _i ... differential data line, b _i , _i ... differential search data, c _i , _i .

Continuation of front page       (56) References JP-A-61-120244 (JP, A)                 JP-A-58-165424 (JP, A)                 JP-A-61-113191 (JP, A)                 JP-A-61-3389 (JP, A)                 JP-A-53-33 (JP, A)                 JP-A-61-133096 (JP, A)

Claims (1)

(57) [Claims] A plurality of flip-flop type memory cells in which inputs and outputs of two inverters are cross-connected to store data are arranged in a row direction and a column direction, and a pair of input / output nodes of each flip-flop type memory cell are arranged in a column direction. A memory cell array connected to a plurality of paired complementary data lines, and a plurality of control nodes of each flip-flop type memory cell connected to a plurality of word lines arranged in a row direction; A match detection circuit for detecting a match with read data from each memory cell read via the complementary data line pair of the cell array, wherein the match detection circuit comprises: A pair, a complementary search input pair, and a complementary output pair, each memory cell array being arranged for each of the complementary data line pairs. A complementary data line pair having the complementary signal input pair connected thereto, and a source / drain path connected between a positive phase signal input of the complementary signal input pair and a positive phase output of the complementary output pair. A MOS transistor, a second MOS transistor having a source / drain path connected between a reverse phase signal input of the complementary signal input pair and a reverse phase output of the complementary output pair, and A third MOS transistor having a source / drain path connected between a phase signal input and the opposite phase output of the complementary output pair, and a third MOS transistor having the opposite phase signal input of the complementary signal input pair and the complementary output pair of the complementary output pair; Fourth MO with source / drain path connected to positive-phase output
And a gate of the first MOS transistor and the second MOS transistor and a gate of the third M transistor.
The gates of the OS transistor and the fourth MOS transistor are connected to a plurality of logic circuits driven in opposite phases by the complementary search input as the search data supplied to the complementary search input pair, and the emitters are commonly connected. Each of the complementary data line pairs includes a first bipolar transistor and a second bipolar transistor, and is disposed for each of the complementary data line pairs. The base of the first bipolar transistor and the base of the second bipolar transistor are respectively A plurality of differential transistor pairs connected to the positive phase output and the negative phase output of the complementary output pair of each logic circuit; a first bipolar transistor of the plurality of differential transistor pairs; And a wired OR circuit for outputting a logical sum of a signal of one collector and two bipolar transistors. Cache memory device that. 2. 2. The device according to claim 1, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are MOS transistors having the same conductivity type channel. A cache memory device according to claim 1. 3. 3. The transistor according to claim 2, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are N-channel MOS transistors. 3. A cache memory device according to claim 1. 4. 4. The method according to claim 1, wherein data of a data storage unit is obtained via a sense circuit in response to an output of the wired OR circuit of the coincidence detection circuit.
The cache memory device according to any one of the preceding items.