JPH0418336B2 - - Google Patents

Info

Publication number
JPH0418336B2
JPH0418336B2 JP59276259A JP27625984A JPH0418336B2 JP H0418336 B2 JPH0418336 B2 JP H0418336B2 JP 59276259 A JP59276259 A JP 59276259A JP 27625984 A JP27625984 A JP 27625984A JP H0418336 B2 JPH0418336 B2 JP H0418336B2
Authority
JP
Japan
Prior art keywords
basic cell
adder
carry
bit
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59276259A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61156433A (ja
Inventor
Makoto Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP59276259A priority Critical patent/JPS61156433A/ja
Priority to DE19853545433 priority patent/DE3545433A1/de
Publication of JPS61156433A publication Critical patent/JPS61156433A/ja
Publication of JPH0418336B2 publication Critical patent/JPH0418336B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP59276259A 1984-12-28 1984-12-28 並列乗算器 Granted JPS61156433A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59276259A JPS61156433A (ja) 1984-12-28 1984-12-28 並列乗算器
DE19853545433 DE3545433A1 (de) 1984-12-28 1985-12-20 Parallelmultiplizierschaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59276259A JPS61156433A (ja) 1984-12-28 1984-12-28 並列乗算器

Publications (2)

Publication Number Publication Date
JPS61156433A JPS61156433A (ja) 1986-07-16
JPH0418336B2 true JPH0418336B2 (pt) 1992-03-27

Family

ID=17566932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59276259A Granted JPS61156433A (ja) 1984-12-28 1984-12-28 並列乗算器

Country Status (2)

Country Link
JP (1) JPS61156433A (pt)
DE (1) DE3545433A1 (pt)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4864529A (en) * 1986-10-09 1989-09-05 North American Philips Corporation Fast multiplier architecture
US4958312A (en) * 1987-11-09 1990-09-18 Lsi Logic Corporation Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults
US5638313A (en) * 1995-01-30 1997-06-10 Cirrus Logic, Inc. Booth multiplier with high speed output circuitry
US5734601A (en) 1995-01-30 1998-03-31 Cirrus Logic, Inc. Booth multiplier with low power, high performance input circuitry
DE19528210C1 (de) * 1995-08-01 1996-12-19 Siemens Ag Halbleiter-Baustein mit mindestens einer Schaltungsanordnung zur eingeschränkten Bearbeitung von an Eingangsanschlüssen des Bausteins anliegenden Eingangsgrößen
US7401110B1 (en) * 2004-09-09 2008-07-15 Sun Microsystems, Inc. System, method and apparatus for an improved MD5 hash algorithm

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114941A (en) * 1978-02-13 1979-09-07 Burroughs Corp Binary multiplying circuit
JPS55105732A (en) * 1979-02-08 1980-08-13 Nippon Telegr & Teleph Corp <Ntt> Multiplier

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4130878A (en) * 1978-04-03 1978-12-19 Motorola, Inc. Expandable 4 × 8 array multiplier
JPS57141753A (en) * 1981-02-25 1982-09-02 Nec Corp Multiplication circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114941A (en) * 1978-02-13 1979-09-07 Burroughs Corp Binary multiplying circuit
JPS55105732A (en) * 1979-02-08 1980-08-13 Nippon Telegr & Teleph Corp <Ntt> Multiplier

Also Published As

Publication number Publication date
DE3545433A1 (de) 1986-07-03
JPS61156433A (ja) 1986-07-16
DE3545433C2 (pt) 1992-10-01

Similar Documents

Publication Publication Date Title
Takagi et al. High-speed VLSI multiplication algorithm with a redundant binary addition tree
US4168530A (en) Multiplication circuit using column compression
US5790446A (en) Floating point multiplier with reduced critical paths using delay matching techniques
US4594678A (en) Digital parallel computing circuit for computing p=xy+z in a shortened time
US7275076B2 (en) Multiplication logic circuit
Mehta et al. High-speed multiplier design using multi-input counter and compressor circuits
US6708193B1 (en) Linear summation multiplier array implementation for both signed and unsigned multiplication
US4866656A (en) High-speed binary and decimal arithmetic logic unit
US5920498A (en) Compression circuit of an adder circuit
Gnanasekaran A fast serial-parallel binary multiplier
JPH0555894B2 (pt)
US5257218A (en) Parallel carry and carry propagation generator apparatus for use with carry-look-ahead adders
US4864528A (en) Arithmetic processor and multiplier using redundant signed digit arithmetic
JPH0456339B2 (pt)
US4441158A (en) Arithmetic operation circuit
JPH0375901B2 (pt)
Oklobdzija High-speed VLSI arithmetic units: Adders and multipliers
US4748584A (en) Parallel multiplier utilizing Booth&#39;s algorithm
US4730266A (en) Logic full adder circuit
US5944776A (en) Fast carry-sum form booth encoder
US5734599A (en) Performing a population count using multiplication
US4700325A (en) Binary tree calculations on monolithic integrated circuits
JP3556950B2 (ja) 高速算術演算装置のけた上げ先見加算器段の数を減少させる構造及び方法
JPH0418336B2 (pt)
US20040010536A1 (en) Apparatus for multiplication of data in two&#39;s complement and unsigned magnitude formats

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees