JPH0418334B2 - - Google Patents

Info

Publication number
JPH0418334B2
JPH0418334B2 JP57077066A JP7706682A JPH0418334B2 JP H0418334 B2 JPH0418334 B2 JP H0418334B2 JP 57077066 A JP57077066 A JP 57077066A JP 7706682 A JP7706682 A JP 7706682A JP H0418334 B2 JPH0418334 B2 JP H0418334B2
Authority
JP
Japan
Prior art keywords
input
circuit
signal
output
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57077066A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58195250A (ja
Inventor
Shunsuke Yoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57077066A priority Critical patent/JPS58195250A/ja
Publication of JPS58195250A publication Critical patent/JPS58195250A/ja
Publication of JPH0418334B2 publication Critical patent/JPH0418334B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/504Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942Significance control
    • G06F7/49947Rounding

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP57077066A 1982-05-08 1982-05-08 デイジタル加算回路 Granted JPS58195250A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57077066A JPS58195250A (ja) 1982-05-08 1982-05-08 デイジタル加算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57077066A JPS58195250A (ja) 1982-05-08 1982-05-08 デイジタル加算回路

Publications (2)

Publication Number Publication Date
JPS58195250A JPS58195250A (ja) 1983-11-14
JPH0418334B2 true JPH0418334B2 (en:Method) 1992-03-27

Family

ID=13623416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57077066A Granted JPS58195250A (ja) 1982-05-08 1982-05-08 デイジタル加算回路

Country Status (1)

Country Link
JP (1) JPS58195250A (en:Method)

Also Published As

Publication number Publication date
JPS58195250A (ja) 1983-11-14

Similar Documents

Publication Publication Date Title
US6687722B1 (en) High-speed/low power finite impulse response filter
US5402012A (en) Sequentially clocked domino-logic cells
JPH0215088B2 (en:Method)
EP0077912B1 (en) Fet adder circuit
CA1229172A (en) Logic adder circuit
US5875125A (en) X+2X adder with multi-bit generate/propagate circuit
US5357457A (en) Adder with carry look ahead circuit
JP3412878B2 (ja) 不等桁上げ方式(varied carry scheme)を用いた高速加算器とそれに関連する方法
US6484193B1 (en) Fully pipelined parallel multiplier with a fast clock cycle
JPH0418334B2 (en:Method)
JPH0424729B2 (en:Method)
US7349938B2 (en) Arithmetic circuit with balanced logic levels for low-power operation
US5777907A (en) Processor for selectively performing multiplication/division
US7085796B1 (en) Dynamic adder with reduced logic
CN101258464A (zh) 全加器模块和使用该全加器模块的乘法器装置
US4471455A (en) Carry-forming unit
US5944777A (en) Method and apparatus for generating carries in an adder circuit
JPS62184534A (ja) 演算回路
US6301597B1 (en) Method and apparatus for saturation in an N-NARY adder/subtractor
JPH0368412B2 (en:Method)
US6272514B1 (en) Method and apparatus for interruption of carry propagation on partition boundaries
US6041341A (en) Method and circuit for adding operands of multiple size
JPH0218727B2 (en:Method)
JP2508041B2 (ja) インクリメント回路
KR100373367B1 (ko) 가산기를이용한스퀘어로직회로