JPH041821A - Pipeline type microinstruction control system - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by simplifying the field constitution of a microinstruction and furthermore reducing the bit width of a microcode register at each stage of a pipeline. CONSTITUTION:A microcode 10 corresponding to each microinstruction is divided into plural fields 1 corresponding to the stages A - W of a pipeline. Then a certain stage of the pipeline is controlled by a bit pattern of the specific one of fields 1 of the microcode 10. The microcode registers 3A - 3W set at the stages A - W of the pipeline respectively hold the number of fields 1 corresponding to a relevant stage and its subsequent ones. In such a constitution, the bit widths of the registers 3A - 3W can be reduced in accordance with progress of the stages of the pipeline. As a result, the hardware quantity can be reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a microinstruction control method in a central processing unit (CPU) configured with a pipeline and controlled by a microprogram, the field structure of the microinstruction is simplified and the The aim is to reduce the bit width of the microcode register and save the amount of hardware.The microcode is divided into multiple fields corresponding to each stage of the pipeline, and the control of each stage of the pipeline is , is performed using the data in field ■ corresponding to each stage above, and the microcode register present in each stage is configured to hold the number of bits in field ■ that controls that stage and subsequent stages. .

[Industrial application field]

The present invention relates to a microinstruction control system in a central processing unit (CPU) configured with a pipeline and controlled by a microprogram.

With the recent diversification of data processing, the configuration of each field of a microinstruction has become more complex, and in a central processing unit (CPU) controlled by a pipeline, the bit width of the microcode register at each stage of the pipeline has become more complex. is on the rise.

Additionally, as the configuration of the above-mentioned fields of microinstructions has become more complex, programming of microinstructions has become more difficult, and coding has become more man-hour-consuming.
There is a need for a method of structuring microinstructions that can reduce the amount of hardware for microcode registers at each stage of the pipeline and that can facilitate microprogramming.

[Prior Art and Problems to be Solved by the Invention] FIG. 3 is a diagram for explaining a pipeline control system, and FIG. 4 is a diagram for explaining a conventional pipeline type microinstruction control system.

FIG. 3 is a diagram showing the concept of data processing using general pipeline control.

In this example, execution of one macroinstruction is completed in six stages of the DW stage, for example.

First, in the D stage, the control memory (C5
) The microcode 10 is read from 1 and its operating section (OPC) is analyzed.

In the next A stage, the address of the operand is calculated, and in the next T stage, an address translation buffer (TLB) (not shown) converts the logical address calculated in the above A stage into a real address.

Then, in the next B stage, based on the real address,
For example, the buffer memory (BS) is accessed to fetch an operand, the E stage performs an operation using the fetched operand data, and the W stage stores the result of the operation in a general register (GR) (not shown). ) to complete the execution of a series of microinstructions.

In the conventional method described above, the microinstructions that control each stage of the pipeline are in a complex format, such as an arithmetic control field (ALU), a register control field (GR), etc.
), branch instruction control field (BRN), etc. The arithmetic control field (ALU) needs to be used, for example, in the A stage and E stage, and the register control field (GR) also takes the form of A stage and E
Control memory (C5) for use on stage, etc.
As shown in FIG. 4, the microcode read from 1 had to be passed to each stage A to W of the pipeline with its bit width unchanged.

For this reason, as mentioned above, with the diversification of data processing,
As microinstructions become more complex, the bit width of microcode registers 3A to 3- at each stage of the pipeline also increases.
- This has caused a problem in that the amount of hardware increases.

In view of the above-mentioned drawbacks of the conventional art, the present invention has been developed by a central processing unit (CPU) configured with a pipeline and controlled by a microprogram.
The purpose of this project is to provide a method that can save hardware by simplifying the field configuration of microinstructions in CPUs (PUs) and reducing the bit width of microcode registers at each stage of the pipeline. It is.

[Means for Solving the Problems] Fig. 1 is a diagram for explaining the present invention in detail, in which (a) shows an example of microcode division, and (b) shows an example of how microcode registers are divided at each stage. A configuration example is shown.

The above problems are solved by a pipelined microinstruction control system configured as follows.

In a central processing unit (CPU) configured with a pipeline and controlled by a microprogram, the microcode 10 is divided into a plurality of fields corresponding to each stage of the pipeline, and the control of each stage of the pipeline is controlled. The microcode register 3 present in each stage is configured to hold the number of bits in the field ■ that controls stage 1 and subsequent stages. do.

[Effect]

That is, according to the present invention, the microcode 10 is structured in a pipeline and corresponds to each macro instruction executed by a central processing unit (CPU) controlled by a microprogram.
is divided into a plurality of fields (2) corresponding to each stage (A stage to W stage) of the pipeline, as shown in FIG. 1(a).

A certain stage of the pipeline is controlled by the bit pattern of one particular field (2) of the microcode 10.

The microcode registers 3A to 3- in each stage A to W of the pipeline are configured to hold only the field 0 corresponding to that stage and subsequent stages, as shown in FIG. 1(b). Configure.

Therefore, in programming a microprogram, each field can be independently coded, which increases the flexibility of the microinstruction and makes it easier to understand and code. Further, the bit width of the microcode registers 3A to 3- can be reduced as the stages of the pipeline progress, which has the effect of reducing the amount of hardware.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram for explaining the present invention in detail, and FIG.
The figure shows an embodiment of the present invention, in which the microcode IO is divided into a plurality of fields corresponding to each stage of the pipeline, and the control of each stage of the pipeline is controlled by each of the above fields. This is done using the data in the field ■ corresponding to the stage, and the microcode registers 3^ to 3- present in each stage have means for holding only the number of bits in the field ■ that controls that stage and subsequent stages. These are the means necessary to carry out the present invention.

Hereinafter, the pipeline type microinstruction control system of the present invention will be explained with reference to FIG. 2 while referring to FIG.

First, in the D stage, the necessary microcode 10 is read out from the control memory (CS) 1. Among the read microcodes, the NA field is sent to the control storage address register (CSA) 2 after undergoing processing such as branch control in order to read the next microcode.

Fields other than the NA field (NA) are stored in the A stage microcode register 3A, and of these, the A stage control field (^) ■ is based on the general register (GR) instruction information indicated by the operand field of the macro instruction. The operand address generation circuit (ADD)
) 4 and generates addresses.

Fields other than the A stage control field (A) ■ are sent to the T stage microcode register 3T.

The T stage control field (T) (2) controls the address translation buffer (TLB) 5 and determines whether or not to perform address translation and the method. If address translation is required,
The real address (RA) is obtained from the effective address (EA) of the operand calculated in the A stage.

Fields other than the T stage control field (T) ■ are sent to the B stage microcode register 3B.

B stage control field (B) ■ is buffer memory (BS)
6, and controls access destinations and data storage destinations.

Fields other than the B stage control field (B) ■ are sent to the E stage microcode register 3E.

E stage control field (E)■ is the arithmetic unit (ALU)
7a and shifter (SFT) 7b, and determines and executes various calculations.

Fields other than the E stage control field (E) ■ are sent to the microcode register 3- of the W stage.

The W stage control field (S) controls the storage location of the calculation results at the E stage.

As described above, the present invention provides a central processing unit (CPU) configured with a pipeline and controlled by a microprogram, in which the microcode 10 is made to correspond to each stage of the pipeline. ) ■, and each stage A to W of the pipeline is controlled by the data in the field (8 to W) ■ corresponding to each stage, and the microcode register 3 present in each stage is The feature is that only the number of bits in the field (2) that controls that stage and subsequent stages is held.

Since they can be coded independently, the microinstructions are more flexible and easier to understand, making them easier to code. Also, the bit width of the microcode register can be reduced as the pipeline stages progress.
This has the effect of reducing the amount of hardware.

[Effects of the Invention] As explained above in detail, the pipeline type microinstruction control method of the present invention is configured by a central processing unit (CPU) that is configured with a vibe line and is controlled by a microprogram.
In this step, the microcode is divided into a plurality of fields (■) corresponding to each stage of the vibration line, and each stage of the vibration line is controlled by the data in the field (■) corresponding to each stage. The existing microcode register is designed to hold the number of bits of the field ■ that controls that stage and subsequent stages, so the microcode registers the field ■ in units of fields.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the present invention in detail, and FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram explaining the pipeline control method. FIG. 4 is a diagram illustrating a conventional pipeline-type microinstruction control system. It is. In the drawing, 1 is control memory (C5). 10 is the microcode. 3 is a microcode register. 3A-3W are microcode registers corresponding to the vibration line stages. 4 is an operand address generation circuit (ADD). 5 is an address translation buffer (TLB). 6 is buffer memory (BS), 7a is arithmetic unit (ALU)
7b is shifter (SFT). ■ is a field corresponding to the microcode stage (A)
~(-). are shown respectively. Figure 1

Claims (1)

[Claims] In a central processing unit (CPU) configured with a pipeline and controlled by a microprogram, the microcode (10) is divided into a plurality of fields ([1]) corresponding to each stage of the pipeline, and Each stage of is controlled by the data in the field ([1]) corresponding to each stage, and the microcode register (3) present in each stage controls that stage and subsequent stages. A pipelined microinstruction control system characterized by holding the number of bits of a field ([1]) to be processed.