JPH04181416A - Radial bus - Google Patents

Radial bus

Info

Publication number
JPH04181416A
JPH04181416A JP30884790A JP30884790A JPH04181416A JP H04181416 A JPH04181416 A JP H04181416A JP 30884790 A JP30884790 A JP 30884790A JP 30884790 A JP30884790 A JP 30884790A JP H04181416 A JPH04181416 A JP H04181416A
Authority
JP
Japan
Prior art keywords
transmission
bus
lines
matching circuit
bus wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30884790A
Other languages
Japanese (ja)
Other versions
JPH0619693B2 (en
Inventor
Norihei Takashima
高島 徳平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GURAFUIKO KK
Original Assignee
GURAFUIKO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GURAFUIKO KK filed Critical GURAFUIKO KK
Priority to JP2308847A priority Critical patent/JPH0619693B2/en
Priority to US07/774,812 priority patent/US5210682A/en
Priority to IL99739A priority patent/IL99739A0/en
Priority to AU85908/91A priority patent/AU8590891A/en
Priority to CA002053562A priority patent/CA2053562A1/en
Priority to EP91309574A priority patent/EP0481779A1/en
Priority to NZ240286A priority patent/NZ240286A/en
Priority to KR1019910018400A priority patent/KR920008611A/en
Publication of JPH04181416A publication Critical patent/JPH04181416A/en
Publication of JPH0619693B2 publication Critical patent/JPH0619693B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits

Landscapes

  • Small-Scale Networks (AREA)
  • Structure Of Printed Boards (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To transmit signals at high speed by making the lengths of transmission lines in a twisted state respectively equal and respectively connecting one end of each transmission line to a matching circuit. CONSTITUTION:A bus wiring board 5 radially arranges a front side signal line 6 composed of a conductor pattern and a rear side signal line 7 on the front and rear sides of an insulated panel with the central common connecting point of the insulated panel as a center so that the signal lines can cross through the insulated panel, these relative front side and rear side signal lines 6 and 7 are alternately connected while interposing a conducting hole 8, and the plural transmission lines having the equal length are radially formed. Further, one end of each transmission line is respectively connected to a matching circuit 9, and the other end of each matching circuit 9 is electrically connected to the external connection part of each processing element 13 arranged toward the outside along the periphery of each bus writing board 5. Thus, signals are transmitted at high speed and further, the transmission error of the signals is hardly generated.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、コンピュータを構成するCPUやメモリなど
の各構成要素を電気的に接続するバスの改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a bus that electrically connects components such as a CPU and a memory that constitute a computer.

(従来の技術) 従来、コンピュータのハードウェアの構成の一例として
は、第8図に示すようにCPUやメモリなどの各構成要
素をプリント基板1.上に実装し、その各プリント基板
1を各実装面が平行になるようにコネクタ2にそれぞれ
接続し、各コネクタ2はさらに相互に電気的に接続して
データ・バス、制御バス、アドレス・バスなどからなる
バス3を平面的に形成したものが知られている。
(Prior Art) Conventionally, as an example of the hardware configuration of a computer, as shown in FIG. 8, each component such as a CPU and memory is mounted on a printed circuit board 1. The printed circuit boards 1 are connected to the connectors 2 with their mounting surfaces parallel to each other, and the connectors 2 are further electrically connected to each other to form a data bus, a control bus, and an address bus. It is known that the bus 3 is formed in a planar manner.

(発明が解決しようとする課題) このように、従来はバス3を平面的に形成し、このバス
3の長さ方向に複数のプリント基板1を平行に配置する
ので、CPUやメモリなどの各構成要素が多くてプリン
ト基板1の個数が多い場合には、プリント基板1の間の
距離の格差が拡大する上に、その距離もまちまちとなる
(Problem to be Solved by the Invention) In this way, conventionally, the bus 3 is formed in a planar manner, and a plurality of printed circuit boards 1 are arranged in parallel in the length direction of the bus 3, so that each of the CPU, memory, etc. When there are many components and the number of printed circuit boards 1 is large, the difference in distance between the printed circuit boards 1 increases and the distances also vary.

そのため、従来のバスでは、CPUやメモリなどの各構
成要素間の伝送距離の違いにともない伝送時間がまちま
ちとなってその時間差制御が必要になり、伝送制御が複
雑化して信号の高速伝送化が困難となり、データの高速
処理化が困難であるという問題が生じていた。
Therefore, with conventional buses, transmission times vary due to differences in transmission distance between each component such as the CPU and memory, making it necessary to control the time difference. This complicates transmission control and makes it difficult to transmit signals at high speed. The problem has arisen that it is difficult to process data at high speed.

そこで、本発明は、誤伝送がなく信号の高速伝送を実現
でき、しかも外部雑音の影響と信号の漏洩とをそれぞれ
防止できるバスを提供することを目的とする。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a bus that can realize high-speed signal transmission without erroneous transmission, and can prevent both the influence of external noise and signal leakage.

(課題を解決するための手段) かかる目的を達成するために、本発明は以下のように構
成した。
(Means for Solving the Problems) In order to achieve the above object, the present invention was constructed as follows.

すなわち、本発明は、表側信号線と裏側信号線とを絶縁
板を介して交差するように共通接続点を中心に絶縁板の
表裏に放射状に配列し、これら関連する両信号線を導通
孔を介在して交互に接続して長さの等しい伝送線路を複
数個放射状に形成し、当該複数個の各伝送線路の各先端
を整合回路の一端にそれぞれ接続したバス配線板を同一
軸線上に重ねて複数個配置し、 前記各整合回路の各他端を、前記各バス配線板の周縁に
沿って外方に向けて配列した各処理要素の外部接続部に
電気的に接続することを特徴とする。
That is, in the present invention, front side signal lines and back side signal lines are arranged radially on the front and back sides of an insulating plate with a common connection point as the center so as to intersect with each other through an insulating plate, and both related signal lines are connected through conductive holes. Bus wiring boards in which a plurality of transmission lines of equal length are formed radially by intervening and alternately connected, and each end of each of the plurality of transmission lines is connected to one end of a matching circuit are stacked on the same axis. A plurality of matching circuits are arranged, and each other end of each of the matching circuits is electrically connected to an external connection portion of each processing element arranged outward along the periphery of each of the bus wiring boards. do.

(作用) このように構成する本発明では、同一軸線上に重ねたバ
ス配線板に形成される関連するツイスト状態の伝送線路
の集合の単位が並列バスを形成し、その関連する各伝送
線路をデータ線、アドレス線、制御線などにそれぞれ割
り当てる。
(Function) In the present invention configured as described above, a unit of a set of related twisted transmission lines formed on bus wiring boards stacked on the same axis forms a parallel bus, and each of the related transmission lines is Assign each line to data lines, address lines, control lines, etc.

また、本発明では、ツイスト状態の伝送線路はその長さ
がそれぞれ等しく、しかもその各伝送線路の各一端を整
合回路にそれぞれ接続するので、各処理要素の間はいず
れも電気的に等距離となり全ての処理要素間の伝送距離
が均一化する上に、伝送線路で信号の反射が起こりにく
い。従って、本発明では、信号の高速伝送が実現でき、
しかも信号の伝送誤りが生じにくい。
Furthermore, in the present invention, the lengths of the twisted transmission lines are equal, and each end of each transmission line is connected to a matching circuit, so that the distance between each processing element is electrically equal. In addition to equalizing the transmission distance between all processing elements, signal reflection is less likely to occur on the transmission line. Therefore, in the present invention, high-speed signal transmission can be realized.
Furthermore, signal transmission errors are less likely to occur.

さらに本発明では、各伝送線路をツイスト状態とするの
で、静電誘導や磁気誘導がなくなって外部雑音に強くな
るうえに伝送線路からの不要輻射が生じない。従って、
本発明では外部雑音の影響と信号の漏洩とを防止でき、
これは上述の信号の高速伝送化や、信号の伝送誤りの低
減化の向上に寄与できる。
Furthermore, in the present invention, since each transmission line is twisted, there is no electrostatic induction or magnetic induction, which increases resistance to external noise and eliminates unnecessary radiation from the transmission line. Therefore,
The present invention can prevent the influence of external noise and signal leakage,
This can contribute to the above-mentioned high-speed signal transmission and reduction of signal transmission errors.

(実施例) 以下、図面を参照して本発明実施例について説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

バス配線板5は、第1図に示すように絶縁板の表裏に後
述する形態で導体パターンを形成した両面プリント基板
からなる。
The bus wiring board 5, as shown in FIG. 1, is a double-sided printed circuit board on which conductor patterns are formed on the front and back sides of an insulating board in a form to be described later.

すなわち、バス配線板5は、導体パターンからなる表側
信号線6と裏側信号線7とを、絶縁板を介して交差する
ように絶縁板の中央の共通接続点を中心に絶縁板の表裏
に放射状に配列し、これら関連する表側信号線6と裏側
信号線7とを導通孔8を介在して交互に接続し、長さの
等しい伝送線路を複数個放射状に形成する(第1図参照
)。
That is, the bus wiring board 5 connects the front side signal line 6 and the back side signal line 7, which are made of a conductive pattern, in a radial pattern on the front and back sides of the insulating plate, centering on a common connection point at the center of the insulating plate so as to intersect with each other through the insulating plate. The related front side signal lines 6 and back side signal lines 7 are connected alternately through conductive holes 8 to form a plurality of transmission lines of equal length radially (see FIG. 1).

各伝送線路を形成する終端の表側信号線6と裏側信号線
7の各一端は、整合回路9を形成する絶縁板の表側の抵
抗R1と絶縁板の裏側の抵抗R1との各一端にそれぞれ
接続する(第2図および第3図参照)。抵抗R1として
は、印刷抵抗やチップ抵抗などが好適である。
One end of each of the front side signal line 6 and back side signal line 7 at the end forming each transmission line is connected to one end of each of the resistance R1 on the front side of the insulating plate and the resistance R1 on the back side of the insulating plate forming the matching circuit 9. (See Figures 2 and 3). As the resistor R1, a printed resistor, a chip resistor, etc. are suitable.

絶縁板の表側の抵抗R1の他端は、導体10を介してバ
ス配線板5の表側外周部に等間隔に設けた接続端子11
と接続する。絶縁板の裏側の抵抗R1の他端は、導通孔
12を介在して絶縁板の表側に配置する抵抗R2の一端
と接続し、抵抗R2の他端を接続端子11と接続する。
The other end of the resistor R1 on the front side of the insulating plate is connected to connection terminals 11 provided at equal intervals on the outer periphery of the front side of the bus wiring board 5 via the conductor 10.
Connect with. The other end of the resistor R1 on the back side of the insulating plate is connected to one end of a resistor R2 disposed on the front side of the insulating plate through the conduction hole 12, and the other end of the resistor R2 is connected to the connecting terminal 11.

抵抗R2としては、抵抗R1と同様に印刷抵抗やチップ
抵抗などが好適である。
Like the resistor R1, a printed resistor, a chip resistor, or the like is suitable as the resistor R2.

このように構成するバス配線板5は、第4図に示すよう
に上下方向の同一軸線上に等間隔隔てて、かつ各バス配
線板5の各信号線6.7がそれぞれ同位相になるように
、所定の個数を配置する。従って、これら同位相に配置
される関連のある信号線6,7の集合の単位が、並列バ
スをそれぞれ形成する。この並列バスを形成する各信号
線6.7は、データ線、アドレス線、制御線などにそれ
ぞれ割当てる。
As shown in FIG. 4, the bus wiring boards 5 configured in this manner are arranged at equal intervals on the same axis in the vertical direction, and so that the signal lines 6.7 of each bus wiring board 5 are in the same phase. A predetermined number of pieces are placed in . Therefore, each unit of a set of related signal lines 6 and 7 arranged in the same phase forms a parallel bus. Each signal line 6.7 forming this parallel bus is assigned to a data line, an address line, a control line, etc., respectively.

そして、このように配置したバス配線板5の周縁に沿っ
て処理要素13を実装したプリント基板14を直立させ
て放射状に配列する(第5図参照)。各プリント基板1
4に設けた外部接続端子15は、コネクタ(図示せず)
を介在してバス配線板5の対応する各接続端子11に電
気的に接続する。
Then, the printed circuit boards 14 on which the processing elements 13 are mounted are erected and arranged radially along the periphery of the bus wiring board 5 arranged in this way (see FIG. 5). Each printed circuit board 1
The external connection terminal 15 provided in 4 is a connector (not shown).
It is electrically connected to each corresponding connection terminal 11 of the bus wiring board 5 via the .

なお、バス配線板5の各接続端子11には、第2図に示
すように上記のコネクタの各接続ピンを着脱自在なソケ
ット16を取り付けておく。
Incidentally, a socket 16 is attached to each connection terminal 11 of the bus wiring board 5, as shown in FIG. 2, to which each connection pin of the above connector can be attached and detached.

各プリント基板]−4に搭載する処理要素13としては
、プロセッサ(CPU)や各種のメモリのほかに、キー
ボードや表示装置などの入出力装置を制御する入出カプ
ロセッサがある。
The processing elements 13 mounted on each printed circuit board]-4 include a processor (CPU), various types of memories, and an input/output processor that controls input/output devices such as a keyboard and a display device.

次に、上記のように構成するバス配線板5の中心から半
径方向に信号線6,7により構成される一つの伝送線路
の高周波信号における等価回路は、第6図に示すように
なる。
Next, an equivalent circuit for a high frequency signal of one transmission line constituted by signal lines 6 and 7 in the radial direction from the center of the bus wiring board 5 constructed as described above is shown in FIG.

第6図において、C1は抵抗R1の両端における静電容
量、C2は信号線6.7間などで形成される静電容量で
ある。そして、これら静電容量C1および静電容量C2
は、抵抗R1および抵抗R2と組み合わさって図示のよ
うな整合回路9を形成する。
In FIG. 6, C1 is the capacitance at both ends of the resistor R1, and C2 is the capacitance formed between the signal lines 6 and 7. And these capacitance C1 and capacitance C2
forms a matching circuit 9 as shown in the figure in combination with resistor R1 and resistor R2.

次に、整合回路9を形成する抵抗R1、抵抗R2の各値
の決定方法について説明する。
Next, a method of determining each value of the resistor R1 and the resistor R2 forming the matching circuit 9 will be explained.

いま、バス配線板5に信号線6,7により形成される放
射状の伝送線路をN本とすると、このバスは第6図で示
すような等価回路の伝送線路に、(N−1)本の同様の
等価回路の伝送線路が分岐接続したものと考えられる。
Now, assuming that the number of radial transmission lines formed by the signal lines 6 and 7 on the bus wiring board 5 is N, this bus has (N-1) transmission lines in the equivalent circuit as shown in FIG. It is thought that transmission lines with similar equivalent circuits are branched and connected.

従って、抵抗R1、抵抗R2の各値の決定に際しては、
上記の点を考慮するとともに、伝送線路の特性インピー
ダンスの値などを考慮し、伝送系全体でインピーダンス
の整合ができる最適値を求めればよい。
Therefore, when determining the values of resistance R1 and resistance R2,
In addition to considering the above points, the value of the characteristic impedance of the transmission line and the like may be taken into consideration to find an optimal value that allows impedance matching in the entire transmission system.

そして、このようにして決定した抵抗R1、抵抗R2の
各値により各伝送線路の各整合回路9を形成すれば、伝
送線路における信号の不要な反射を抑制でき、各処理要
素13間では誤伝送なくデータの高速転送か可能となる
By forming each matching circuit 9 of each transmission line using the respective values of the resistor R1 and the resistor R2 determined in this way, unnecessary reflection of signals on the transmission line can be suppressed, and erroneous transmission between each processing element 13 can be suppressed. This makes it possible to transfer data at high speed.

また、信号線路は表側信号線6と裏側信号線7とで形成
されるツイスト状態とするので、静電誘導や磁気誘導か
なくなって外部雑音に強くなるうえに伝送線路からの不
要輻射を抑制できる。
In addition, since the signal line is in a twisted state formed by the front side signal line 6 and the back side signal line 7, there is no electrostatic induction or magnetic induction, making it resistant to external noise and suppressing unnecessary radiation from the transmission line. .

さらに本実施例のバスは、長さの等しいツイスト状態の
伝送線路を絶縁板の中心から放射状に複数個形成し、そ
の複数個の各伝送線路に整合回路9をそれぞれ接続した
バス配線板5を、同一軸線上に重ねて複数個配置して形
成した。従って、このバスを使用して第5図で示すよう
なコンピュータシステムを構成すると、接続する処理要
素13が多数であっても、バスの長さが全体的に短縮し
てコンパクト化できる。
Furthermore, the bus of this embodiment includes a bus wiring board 5 in which a plurality of twisted transmission lines of equal length are formed radially from the center of an insulating board, and a matching circuit 9 is connected to each of the plurality of transmission lines. , were formed by arranging a plurality of them one on top of the other on the same axis. Therefore, if this bus is used to construct a computer system as shown in FIG. 5, even if a large number of processing elements 13 are connected, the overall length of the bus can be shortened and the computer system can be made more compact.

次に、バス配線板の他の実施例について第7図を参照し
て説明する。
Next, another embodiment of the bus wiring board will be described with reference to FIG.

このバス配線板17は、第1図で示すバス配線板5を2
枚使用し、L下方向において上側のバス配線板5の各信
号線6の中間に下側のバス配線板5の信号線6か位置す
るように、プリプレグ18を介在して両者を一体に積層
したものである。
This bus wiring board 17 has two bus wiring boards 5 shown in FIG.
They are laminated together with a prepreg 18 interposed between them so that the signal line 6 of the lower bus wiring board 5 is located between each signal line 6 of the upper bus wiring board 5 in the L downward direction. This is what I did.

このように構成するバス配線板17は、2枚のバス配線
板5の各接続端子11が千鳥状に配置されるので、接続
ピンが千鳥状に配置されたコネクタを用いて第5図のよ
うなコンピュータシステムを形成できる。
In the bus wiring board 17 constructed in this way, since the connection terminals 11 of the two bus wiring boards 5 are arranged in a staggered manner, a connector with connecting pins arranged in a staggered manner is used to connect the bus wiring board 17 as shown in FIG. A computer system can be created.

(発明の効果) 以上のように、本発明では、ツイスト状態の伝送線路は
その長さがそれぞれ等しく、しかもその各伝送線路の各
一端を整合回路にそれぞれ接続するので、各処理要素の
間はいずれも電気的に等距離となり全ての処理要素間の
伝送距離が均一化する上に、伝送線路で信号の反射が起
こりにくい。
(Effects of the Invention) As described above, in the present invention, the twisted transmission lines have the same length, and each end of each transmission line is connected to a matching circuit, so that the distance between each processing element is Both are electrically equidistant, which equalizes the transmission distance between all processing elements, and makes it difficult for signal reflection to occur on the transmission line.

従って、本発明では、信号の高速伝送が実現でき、しか
も信号の伝送誤りが生じにくいという効果が得られる。
Therefore, according to the present invention, it is possible to realize high-speed signal transmission, and it is also possible to achieve the effect that signal transmission errors are less likely to occur.

また本発明では、各送線路をツイスト状態とするので、
静電誘導や磁気誘導がなくなって外部雑音に強くなるう
えに伝送線路からの不要輻射が生じない。従って、本発
明では外部雑音の影響と信号の漏洩とを防止できるとい
う効果が得られ、これは上述の信号の高速伝送化や、信
号の伝送誤りの低減化の向上に寄与できる。
In addition, in the present invention, each transmission line is twisted, so
Electrostatic induction and magnetic induction are eliminated, making it resistant to external noise and eliminating unnecessary radiation from the transmission line. Therefore, the present invention has the effect of being able to prevent the influence of external noise and signal leakage, which can contribute to the above-mentioned high-speed signal transmission and reduction of signal transmission errors.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はバス配線板の一例を示す平面図、第2図はその
主要部を示す断面図、第3図は第2図の導体パターンと
抵抗の接続関係を示す斜視図、第4図はバス配線板の配
置例を示す図、第5図はバス配線板を使用してコンピュ
ータシステムを構成した斜視図、第6図はバス配線板の
中心から半径方向に構成される一つの伝送線路の高周波
信号における等価回路、第7図はバス配線板の他の実施
例を示す分解斜視図、第8図は従来の技術を説明する図
である。 5.17はバス配線板、6.7は信号線、9は整合回路
、13は処理要素である。 特許出願人  株式会社 ゲラフィコ 代理人  牧 舌部 (他3名) 第1図 第2図 第4図 第5図
Fig. 1 is a plan view showing an example of a bus wiring board, Fig. 2 is a sectional view showing its main parts, Fig. 3 is a perspective view showing the connection relationship between the conductor pattern and the resistor in Fig. 2, and Fig. 4 is a plan view showing an example of the bus wiring board. Figure 5 is a perspective view of a computer system configured using a bus wiring board; Figure 6 is a diagram showing an example of the arrangement of a bus wiring board; Figure 6 is a diagram showing one transmission line configured radially from the center of the bus wiring board; An equivalent circuit for a high frequency signal, FIG. 7 is an exploded perspective view showing another embodiment of the bus wiring board, and FIG. 8 is a diagram illustrating a conventional technique. 5.17 is a bus wiring board, 6.7 is a signal line, 9 is a matching circuit, and 13 is a processing element. Patent applicant Gerafico Co., Ltd. Agent Tobe Maki (3 others) Figure 1 Figure 2 Figure 4 Figure 5

Claims (2)

【特許請求の範囲】[Claims] (1)表側信号線と裏側信号線とを絶縁板を介して交差
するように共通接続点を中心に絶縁板の表裏に放射状に
配列し、これら関連する両信号線を導通孔を介在して交
互に接続して長さの等しい伝送線路を複数個放射状に形
成し、当該複数個の各伝送線路の各先端を整合回路の一
端にそれぞれ接続したバス配線板を同一軸線上に重ねて
複数個配置し、 前記各整合回路の各他端を、前記各バス配線板の周縁に
沿って外方に向けて配列した各処理要素の外部接続部に
電気的に接続することを特徴とするラジアル・バス。
(1) The front side signal line and the back side signal line are arranged radially on the front and back of the insulating plate with a common connection point as the center so as to intersect with each other through the insulating plate, and both of these related signal lines are connected through a conduction hole. A plurality of bus wiring boards are stacked on the same axis, in which a plurality of transmission lines of equal length are connected alternately to form a radial pattern, and each end of each of the plurality of transmission lines is connected to one end of a matching circuit. and each other end of each of the matching circuits is electrically connected to an external connection portion of each processing element arranged outward along the periphery of each of the bus wiring boards. bus.
(2)前記整合回路は、複数の抵抗、および前記伝送線
路間で形成される静電容量により形成してなることを特
徴とする請求項1に記載のラジアル・バス。
(2) The radial bus according to claim 1, wherein the matching circuit is formed by a plurality of resistors and a capacitance formed between the transmission lines.
JP2308847A 1990-10-19 1990-11-16 Radial bus Expired - Lifetime JPH0619693B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2308847A JPH0619693B2 (en) 1990-11-16 1990-11-16 Radial bus
US07/774,812 US5210682A (en) 1990-10-19 1991-10-11 Radial type of parallel system bus structure having pairs of conductor lines with impedance matching elements
IL99739A IL99739A0 (en) 1990-10-19 1991-10-14 Radial and parallel bus structure
AU85908/91A AU8590891A (en) 1990-10-19 1991-10-16 Radial-and-parallel bus structure
CA002053562A CA2053562A1 (en) 1990-10-19 1991-10-16 Radial-and-parallel bus structure
EP91309574A EP0481779A1 (en) 1990-10-19 1991-10-17 Radial and parallel bus structure
NZ240286A NZ240286A (en) 1990-10-19 1991-10-18 Radial and parallel bus structure with impedance matching elements between printed radial conductor pairs
KR1019910018400A KR920008611A (en) 1990-10-19 1991-10-18 Radial bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2308847A JPH0619693B2 (en) 1990-11-16 1990-11-16 Radial bus

Publications (2)

Publication Number Publication Date
JPH04181416A true JPH04181416A (en) 1992-06-29
JPH0619693B2 JPH0619693B2 (en) 1994-03-16

Family

ID=17985992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2308847A Expired - Lifetime JPH0619693B2 (en) 1990-10-19 1990-11-16 Radial bus

Country Status (1)

Country Link
JP (1) JPH0619693B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6600790B1 (en) 1996-10-30 2003-07-29 Hitachi, Ltd. Gap-coupling bus system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5488038A (en) * 1977-12-24 1979-07-12 Fujitsu Ltd Data processor
JPS6037268U (en) * 1983-08-20 1985-03-14 富士通株式会社 Mounting structure of printed wiring board
JPH01224820A (en) * 1988-03-04 1989-09-07 Fujitsu Ltd Method for constituting bus and bus circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5488038A (en) * 1977-12-24 1979-07-12 Fujitsu Ltd Data processor
JPS6037268U (en) * 1983-08-20 1985-03-14 富士通株式会社 Mounting structure of printed wiring board
JPH01224820A (en) * 1988-03-04 1989-09-07 Fujitsu Ltd Method for constituting bus and bus circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6600790B1 (en) 1996-10-30 2003-07-29 Hitachi, Ltd. Gap-coupling bus system

Also Published As

Publication number Publication date
JPH0619693B2 (en) 1994-03-16

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