JPH04181409A - Pipeline processor - Google Patents

Abstract

PURPOSE:To reduce energy consumption by providing a clock control circuit to stop and control the supply of a clock to a first stage not participated in a processing. CONSTITUTION:This processor is composed of plural stages 10-1, 10-2... 10-N and a clock control circuit 12. The stages 10-1, 10-2... 10-N are respectively composed of elements, which energy consumption depends on a clock frequency, and apply the outputs to rear steps, and the clock control circuit 12 stops and controls the supply of the clock to the first stage 10-1 not participated in the pipelined processing. Thus, energy consumption can be reduced so as to more reduce the capacity of a power source and further, the device can be made light and compact.

Description

[Detailed Description of the Invention] [Table of Contents Outline Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention CW1 Required] Pipe for performing calculations in pipeline processing With regard to line processing equipment, the aim is to provide equipment that can reduce power consumption.The aim is to provide equipment that is not involved in processing by having multiple stages each consisting of elements whose power consumption depends on the clock frequency and providing output to subsequent stages. In addition, a plurality of stages each consisting of an element whose power consumption depends on the clock frequency and providing an output to the subsequent stage are used for processing. The present invention is constructed by having a clock control circuit that controls the termination of the clock supply to the first stage that is no longer involved, and providing the recursive stage with a selector that selects the output of the previous stage and then continues to select the recursive input.

[Industrial Field of Application] The present invention relates to an apparatus for performing pipeline processing operations.

In a vector processor, vector operations are performed by pipeline processing.

[Prior Art] This type of device is constructed by connecting circuits in each stage in series, and the circuits in each stage include elements whose power consumption depends on a clock.

In the past, the clock was always supplied to all stages, and power was consumed even in stages that did not contribute to the pipeline operation [Problem to be solved by the invention] Therefore, in the past, Power is wasted, which increases the capacity of the power supply and results in a larger device.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a device that can reduce power consumption.

[Means for Solving the Problems] In order to achieve the above object, the device according to the present invention has the following features:
It is configured as shown in the figure.

The apparatus according to the first invention includes a plurality of stages 10-1.
10-2@・010-N and the clock control circuit 12 Stage 10-1.10-2・・@10-
N is composed of elements whose power consumption depends on the clock frequency, and provides an output to the subsequent stage, and the clock control circuit 12 is not involved in the pipeline processing in the first stage 10-
Controls to stop the clock supply to 1.

Further, the apparatus according to the second invention includes a plurality of stages 10-1.
．． 10-2...10-N and a clock control circuit 12 Stage 10-1゜10-2 @...
10-N is composed of elements whose power consumption depends on the clock frequency, and provides an output to the subsequent stage, and the clock control circuit 1
2 controls to stop the clock supply to the first stage 10-1 which is no longer involved in pipeline processing, and the stage 10-1. Of to-2-@-10-N, the stage 10-K that performs recursive operation is provided with a selector 14 that selects the previous stage output and then continuously selects the recursive input.

[Operations] In the present invention, the clock supply to the stage 10-1 that no longer contributes to the pipeline operation is controlled to stop.This reduces power consumption.

[Embodiments] Hereinafter, preferred embodiments of the apparatus according to the present invention will be described based on the drawings.

FIG. 2 shows a device that performs repeated division operations, and FIG. 3 explains its operation using a time chart.

In this example, partial quotients are calculated at regular time intervals and the final quotient is determined by combining the partial quotients.

In FIG. 2, operand register 2 of preprocessing section 20
2. The dividend and divisor set in 24 are selector 2.
6 to the preprocessing circuit 28. A single precision/double precision switching instruction is given to the preprocessing circuit 28 from the outside.

The single-precision or double-precision dividend and divisor obtained by the preprocessing circuit 28 are sent to the operand register 301 and the partial quotient prediction circuit 32
The output of the operand register 30 is given to the partial quotient prediction circuit 32.

In general, the output of the operand register 30 is sent to the recursive operation unit 3.
The output of the partial quotient prediction circuit 32 is applied to the selector 40 of the recursive calculation section 34.

In this recursive operation section 34, the output of the selector 36 is given to a dividend register 42, and the output of the dividend register 42 is given to an adder 44.

Further, the adder 44 is supplied with the output of the multiplier 46, and the multiplier 46 is supplied with the output of the operand register 30 via a divisor register 38.48 (for timing adjustment).

Furthermore, the output of the selector 40 is given to a partial quotient register 50, and the output of the partial quotient register 50 is fed to a multiplier 46.
is given to.

The output of the adder 44 is given to the adder 52 and the carry look-ahead circuit 54, the output of the adder 52 is given to the remainder creation circuit 56, and the output of the carry look-ahead circuit 54 is given to the remainder creation circuit 561 for partial quotient prediction. circuit 58.

Of these, the output of the remainder generation circuit 56 is given to the selector 36 and the partial quotient generation circuit 60, and the output of the partial quotient generation circuit 60 is sent to the outside via a partial quotient register 62.

Further, the output of the partial quotient prediction circuit 58 is output from the selector 40.
The selector output is provided to a partial quotient generating circuit 60 via a partial quotient register 50.

Pre-processing section 20. The recursive calculation unit 34 has the same figure and the third
As can be understood from the figure, a normal clock and a half clock are each supplied.

Operand registers 22 and 24 of the preprocessing unit 20
A clock control circuit 64 controls the supply and stop of the normal clock to the operand register 2.
2. The normal clock for 24 is supplied to the preprocessing unit 2.
Stop control is performed when 0 no longer contributes to pipeline operation.

Further, the selectors 36 and 4.0 of the recursive calculation unit 34 are controlled by the bus switching control circuit 66, and the selectors 36 and 4.0 are controlled by the bus switching control circuit 66.
In the first cycle of operation, the output of the operand register 309 and the partial quotient prediction circuit 32 is selected t'k 2
After the cycle, the output of the remainder generation circuit 561 and the partial quotient prediction circuit 58 is selected.

Note that the selector 26 of the preprocessing section 20 is also controlled by the bus switching control circuit 66, and the operand registers 22, 24
The value of is switched and output to the preprocessing circuit 28, and by fixing the output of the selector 26 while the clock is stopped,
This prevents output changes from occurring in later stages.

In this embodiment, from the operand register 301 of the preprocessing section 20 to the partial quotient prediction circuit 32 to the recursive operation section 34,
receives those outputs, and from the next cycle the selector 36.40 outputs the remainder generation circuit 564 and partial quotient prediction circuit 58.
Continue to select output.

Therefore, after that, the remainder and the partial quotient (the output of the remainder generation circuit 561 and the partial quotient prediction circuit 58) are
Recurse within 4 and calculate the dividend in the next operation.

Used as a partial quotient.

That is, once the recursive calculation unit 34 receives the output of the preprocessing unit 20, it will no longer receive the output of the preprocessing unit 20.

For this reason, the preprocessing unit 20 only performs data transfer operations and does not contribute to pipeline processing.

Therefore, as shown in FIG. 3, a lock (Tl) is required before the recursive operation unit 34 receives and receives the data of the first cycle.
After that, the supply of normal clocks to the operand registers 22 and 24 of the preprocessing section 20 is controlled to stop.

This stops the output change of the preprocessing section 20, and therefore the power consumed by the preprocessing section 20 can be reduced.

Specifically, the power consumption of the device can be reduced by about 20%, and therefore, according to this embodiment, it is possible to construct a lighter and more compact device by using a power source with a smaller capacity.

[Effects of the Invention] As explained above, according to the present invention, power consumption can be reduced by stopping the supply of clocks to stages that no longer contribute to pipeline operation, and as a result, the power supply can be made smaller in capacity and lighter in weight. It becomes possible to provide a compact device.

[Brief explanation of drawings]

Figure 1 explains the principle of the invention. Figure 2 shows the configuration of the embodiment. FIG. 3 is a time chart explaining the operation of the embodiment; It is. 20...Pre-processing section 22.24... Operand register 26...Selector 28.11 fist preprocessing circuit 30/1111 operand register 3211... Partial quotient prediction circuit 34.--Recursive operation section 36...Selector 38...Modification number register 40@-[phase] selector 42・Fist・Dividend register 44... Adder 4611@book multiplier 48...Divisor register 50...Partial quotient register 52φ...adder 54.1111 carry look ahead circuit 56・φ・Remainder creation circuit 58...Φ partial quotient prediction circuit 60...Φ partial quotient generation circuit 62...0 partial quotient register 64Φ...Clock control circuit 66...Bus switching control circuit Agent Patent Attorney Gifu Ito

Claims (2)

[Claims] (1) A plurality of stages (10-1, 10
-2...10-N), the pipe is characterized by having a clock control circuit (12) for controlling the stop of clock supply to the first stage (10-1) that is no longer involved in pipeline processing. Line processing equipment. (2) A plurality of stages (10-1, 10
-2...10-N), which has a clock control circuit (12) that controls the stop of clock supply to the first stage (10-1) that is no longer involved in pipeline processing;
A pipeline processing device characterized in that a selector (14) that selects a previous stage output and then continuously selects a recursive input is provided in a recursively operating stage (10-K).