JPH04178993A - Semiconductor dynamic memory device - Google Patents

Abstract

PURPOSE:To prevent a decline in operating speed of the title memory device at the refreshing time by transferring the plurality of outputs of a plurality of address buffer circuits as the input signals of a decode circuit and the plurality of outputs of the decode circuit to a row-decode circuit. CONSTITUTION:An address Ai is once inputted to an address buffer 101 and the buffer 101 outputs internal address signals AXi and the inverse of AXi and the signals are transferred to a pre-decode circuit 103. A decoder input stage circuit 104 is controlled by means of a refresh controlling signal REF and, during the refreshing operations of the circuit 104, the output AXPi of the circuit 103 becomes a signal of the same level as that of the refresh address RFAi and, during ordinary operations, the output AXPi becomes a signal of the same level as that of the internal address AXi. Therefore, this semiconductor dynamic memory device is prevented from declining in the operating speed at the time of refreshing operations and at the time of ordinary operations following a delay in the speed of the refreshing operations.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor dynamic memory device with a self-refresh function operated by a chip-embedded counter.
(abbreviated as AM) (Yo For example, U.S. Patent No. 4.071.8
01 or as illustrated in U.S. Pat. No. 4,293,993.
Data is stored in capacitors and must be refreshed periodically due to leakage current (°C). According to the method, as shown in FIG. 11, the address An input from the outside and the refresh address RFAn, which is the output of the refresh counter 1101 and is the address at the time of refresh, are sent to the address buffer circuit 1102.
Address buffer input stage 1 receives external address An in address buffer circuit 1102.
103, and a counter stage 1104 which receives a refresh address RFAn as input, and the respective output signals are connected to a first transfer means 1105 and a second transfer means 1106 controlled by a refresh control signal RFE. The outputs of the transfer means 1105 and 1106 of No. 2 are combined and inputted to the address buffer output stage 1107 from the address buffer output stage 1107 to the internal address AXn.
, /AXn are output.

When a chip is constructed using this conventional method, it becomes as shown in FIG. Configuration of Figure 12+, LIM bit DRAM
As an array circuit, the memory cell array 1201 of 128 bits is 8 blocks long, and the sense amplifier row and column decoder row 1202 are 4 blocks long.
There are eight blocks of row decoder arrays 1203.As peripheral circuits, there are a pad and input protection circuit 1204, an address buffer 1205 having the above-described configuration, a refresh control circuit 1206, a refresh counter 1207, and a row predecoder 1208.

The address buffer circuit 1205 is placed near the pad and the input protection circuit 1204 because of the need to suppress the input capacitance of the input pins of the chip.Also, the address bins are distributed around the chip for mounting efficiency. Ru. Therefore, refresh counter 1207
Output RFA i and output RFEC table of refresh control circuit 1206 Distributed address buffers 12
The output AXii table of the address buffer 1205 is also routed and inputted to the row predecode circuit 1208, which is essential for large-capacity DRAM. Although the output of the row pre-decode circuit 1208 is transferred to the row decode circuit 1203, the problem to be solved by the invention is that in the above configuration, however, the wiring for the refresh address RFAi becomes large.The wiring capacity for the refresh address RFAi increases. As a result, the refresh operation speed decreases, and the normal operation speed decreases due to the refresh operation speed delay.
However, the configuration shown in Fig. 12 has the problem of increasing current consumption due to an increase in wiring capacitance.However, the configuration shown in Fig. 12 is related to the above-mentioned problem, but it is not so much of a problem at the IM bit DRAM level. Reference S, 5aito et al, 'AI-
Mbit CMO3DRAM with Fast
Page Mode and 5tatic
Column Mode”, IEEE Jou
rnalof 5olid-state circ
uits (I-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-E-I-D-State Sakift) Sakift)”, vol. 5c-2
0, No, 5. Oct, 1985 pp903-9
As seen in 08, the refresh counter and address buffer are adjacent in layout, so
The wiring capacity of the refresh address RFAi is at a level that does not pose a problem. However, if the capacity of i-h DRAM reaches the 16 Mbit level or higher, the chip size will increase, and the number of address bins will increase, which will affect many areas within the chip. It is obvious that the above-mentioned problems become more serious because of the distributed arrangement.The present invention takes this into consideration and provides a semiconductor dynamic memory device that can prevent an increase in the wiring capacity of refresh addresses. The present invention (1) It has a pre-decode circuit existing between a path between a row decode circuit that operates a drive circuit directly connected to a word line and an address buffer; The input stage circuit of the decoding circuit receives the plurality of outputs of the plurality of address buffer circuits and the plurality of outputs of the refresh counter as inputs, and uses the refresh control signal to input the plurality of outputs of the plurality of address buffer circuits and the plurality of outputs of the counter. Either one is transferred from the input stage circuit as an input signal to a decoding circuit in the predecoding circuit.
The semiconductor dynamic memory device is characterized in that the decoding circuit receives the input signal and transfers a plurality of output signals to the row decoding circuit or any other circuit within the same chip. :t, an input stage of the pre-decoding circuit is a first decoding circuit whose inputs are the plurality of outputs of the plurality of address buffer circuits;
A second decoding circuit receives a plurality of outputs of the refresh counter as input, and an output stage of the predecoding circuit receives a plurality of outputs of the first decoding circuit and a plurality of outputs of the second decoding circuit. The refresh control signal causes one of the plurality of outputs of the first decoding circuit and the plurality of outputs of the second decoding circuit to be sent from the output stage circuit to the row decoding circuit or any circuit within the same chip. In a semiconductor dynamic memory device characterized in that the semiconductor dynamic memory device transfers data, the present invention (3) it is further characterized in that the plurality of address buffer circuits include one circuit per stage of refresh counter for any one address buffer circuit. and an address switching circuit configured to output either the output of the address buffer circuit or the output of the counter according to a refresh control signal. A semiconductor dynamic memory device characterized in that the output of the address switching circuit is transferred to an address buffer output stage circuit, and the address buffer output stage circuit transfers an address signal to the predecoding circuit or to any circuit within the same chip. Owing to the above-described structure, the present invention can minimize the wiring of the refresh address line RFAi in a large-capacity DRAM, thereby preventing a decrease in the operating speed during refresh and increasing the speed of the refresh operation. Preventing normal operating speed from decreasing due to delays.
It becomes possible to prevent an increase in current consumption due to an increase in wiring capacitance.

Embodiment (Embodiment 1) FIG. 1 shows a configuration diagram of a semiconductor dynamic memory device according to a first embodiment of the present invention. 4 In FIG. 1, 101 is an address buffer, 102
103 is a predecode circuit i; 104 is a decoder input stage circuit in the predecode circuit 103; and 105 is a decoder in the predecode circuit 103. Ai is the address AXi input from the outside, /AXi, AXj, /AXj is the internal address RF which is the output amplified by the 7-dress buffer 101.
Ai and RFAj are refresh address counters 102
Reflation/assurance input generated by AXPi, /
AXPi, AXPj, /AXPj are the outputs of the decoder input stage circuit 104, RFE is the refresh control signal, RP
O, RPI, RP2. RPn is a predecode circuit 103
The operation of the first embodiment of the present invention will now be explained with reference to FIG. Address signals AXi and /AXi are output, and these signals are transferred to the predecode circuit 103 and ar#J.

The predecode circuit 103 is a recent megabit class DRA.
M is a circuit that is always provided to simplify the layout of the row decoding circuit directly connected to the next stage word line drive circuit. The refresh address counter 102 operates and the refresh address RF
Conventionally, this refresh address RF
A i is the input signal input to the address buffer 101. In this embodiment, the internal address signals AX i , /AX i are transferred to the predecode circuit 103 .
, AX j , /AXj and refresh address signals RFAi, RFAj are input. The internal address signal is a complementary signal, and the refresh address signal is not a complementary signal (it goes without saying that the refresh address signal may be a complementary signal (the decoder input stage circuit 104 is controlled by the refresh control signal RFE).
During refresh operation (RFE=H), the output AXP i of the decoder input stage circuit 104 becomes a signal at the same level as the refresh address RFAi, and during normal operation (RFE
E=L) is the output AXP1 of the decoder input stage circuit 104.
becomes a signal at the same level as the internal address AXi.

FIG. 2 shows a specific circuit example of the decoder input stage circuit 104,
FIG. 3 shows the timing chart of FIG. 2. FIG. 2 shows a CMO3 type signal selection circuit.

It is composed of two tristate gates 201 and 202, a control signal inverter 203, and an output inverter 204.If the control signal RFE is at the same level, the tristate gate 202 is activated and the refresh address RF is activated.
Ai is transferred to output AXPi, and conversely, when refresh control signal RFE is at L level, tristate gate 201 is activated and internal address signal AXi is transferred to output A
This operation is also clear from the timing chart in FIG.
is transferred to the decoder 105 and the predecode signal PRO
, PRI, PR2, and PRn. If there are 3 addresses input, there are 8 predecode signals (=2
3), and if the number of input addresses is 4, the number of predecode signals is 16 (=24>.This predecode signal is transferred to the row decode circuit.If the above configuration is configured on an actual chip, , it will look like the layout diagram shown in Figure 4.Layout diagram 1 shown in Figure 4;
t, is a layout diagram of a 16M bit DRAM level. MA is a memory cell array, 16M bit DRAM
In the case of 256 bits, L SA is a sense amplifier and 110 switch circuits L RD is a row decoding circuit and a word line drive circuit, 401 is an address input pad and an input protection circuit, 402 is an address buffer, and 403 is a refresh circuit. addresskaranku 404
is a refresh control circuit 405 is a predecode circuit
406 is a control signal input pad and an input protection circuit.As shown in FIG. Although the decoding circuit 405 is placed in the center of the chip in FIG. 4, it does not affect the effects of the present invention, which will be described later, even if it is placed in the periphery of the chip. Switching between the refresh address RFAi and the internal address AXi is not performed on the address buffer 402 side as in the conventional case, but on the predecode circuit 405 side.Even though the output RPi of the predecode circuit 405 is transferred to the row decode circuit RD, switching control is still performed. , the signal CNT is transferred from the external control signal pad 406 to the refresh control circuit 404.
Refresh control signal RFE and refresh counter control signal RC are generated.Refresh control signal R
FE is the predecode circuit 405 area. Refresh counter control signal RC is the refresh address counter 403.
will be forwarded to.

If the predecode circuit 405 and the refresh address counter 403 are placed adjacent to each other as shown in FIG. 4, the wiring of the refresh address line RFAi can be easily routed.
As a result, it is possible to prevent a decrease in operating speed during refresh, to prevent a decrease in normal operating speed due to a delay in refresh operation, and to prevent an increase in current consumption due to an increase in wiring capacitance. Also, since the number of routing of the refresh address line RFAi is reduced, the wiring layout is simplified and the chip size can be reduced (Embodiment 2) FIG. 5 shows the second embodiment of the present invention. In FIG. 5, which shows a configuration diagram of the semiconductor dynamic memory device in the embodiment, 501 is an address buffer, 502
503 is a predecode circuit, 504 is a normal decoder in the predecode circuit 503, 505 is a refresh decoder in the predecode circuit 503, 506 is a decoder output stage circuit in the predecode circuit 503, and Ai and Aj are the decoder output stage circuits in the predecode circuit 503. Address input from outside AXi, /
AXi, AXj, /AXjl address buffer 50
Internal address RF A i which is the output amplified by 1
, RF A j j & Refresh address RP generated by refresh address counter 502
IO, RP I 1. RP I 2. RP Ik
is the output of the normal decoder 504, IIJ, REF is the refresh control signal RPRO, RPRl, RPR2, R
PRk is the output of the refresh decoder 505 RPO
, RPl, RP2. RPn is a predecode signal that is the output of the predecode circuit 503.The operation of the second embodiment of the present invention will be explained with reference to FIG. 501 and outputs high potential level internal address signals AXi, /AXi, AXj, /AXj. These signals are transferred to the predecode circuit 503, and the refresh operation is controlled from the 4-X refresh address counter 502. In this case, the refresh address counter 5゜2 operates and outputs refresh addresses RFAi and RFAj. Conventionally, this refresh address RFAi was input to the address buffer 501, so it is not exchanged. In this embodiment, it is transferred to the predecode circuit 5゜3. Also, the internal address signals AXi, / are sent to the normal decoder 504 inside the predecode circuit 5o3.
AXi, AXj, /AXjM 'J71z flash decoder 505 receives refresh address signals RFAi, R
FAj is input at 4 points.The internal address signal is a complementary signal, and the refresh address signal is not a complementary signal.It goes without saying that a complementary signal may be used. The functions of the normal decoder 504 and the refresh decoder 505 are completely the same.The normal decoder 504 and the refresh decoder 505 in FIG. Yes, the same decoded output is produced for the same input combination.

Decode output RPIO, RPI of normal decoder 504
1. RPI2. RPIk and refresh decoder 5
05 decode output RPRO, RPRI.

RPR2 and RPRk are input to the decoder output stage circuit 506. It is also possible to operate only the refresh decoder 504 during the refresh operation, and operate only the refresh decoder 505 during the refresh operation.

Decoder output stage circuit 506il Controlled by refresh control signal RFE during refresh operation (RF
E=H), the output RPO of the decoder output stage circuit 506,
RP 1. RP 2. RPni& Decoded outputs of refresh decoder 505 RPRO, RPRI, RP
The signal becomes the same level as R2 and RPRn, and during normal operation (
RFE=L) is the output RP of the decoder output stage circuit 508.
O,RP 1. RP2. RPn1 friend normal decoder 50
4 decode output RPIO, RPI 1. RPI 2.
No signal at the same level as RPI k Decoder output stage circuit 5064; L In the circuit shown in Figure 2, the input AX
i is normal decoder output RP I > L input RFA
This can be realized by replacing i with the refresh decoder output RPRi.

If the configuration of the second embodiment is configured on an actual chip, the layout will be exactly the same as the layout diagram shown in FIG.
As a result, it is possible to prevent a decrease in operating speed during refreshing. It is also possible to prevent a decrease in normal operating speed due to a delay in refresh operation. Furthermore, it is possible to prevent an increase in current consumption due to an increase in wiring capacitance. 4 and refresh address line RFA
This also has the effect of simplifying the wiring layout and making it possible to reduce the chip size because the number of i lines is reduced.

(Embodiment 3) FIG. 6 shows a configuration diagram of a semiconductor dynamic memory device according to a third embodiment of the present invention. In FIG. 6, 601 is an address buffer input circuit, and the input signal is an external address. AO, AI, An, output signal is AI O, AI 1. A, I n de Muro 02
is a counter unit which is a circuit for one stage of the refresh address counter, and the input signals are the refresh clock RCK and the refresh address signals RAO and RAI of the previous stage.

RAn-1, output signal is refresh address signal RA
O,RA 1. It is RAn. 603 is an address switching circuit whose input signals are AIO, AIL, AIn, and a refresh address signal RAO.

RAI, RAn, output signals are AX I O, AX I
1. AXln 604 is an address buffer output circuit, and input signals are AX I O, A, X I 1 .
AX In, output signal is internal address signal AXO, /A
XO, AX l , /AX 1 , AX n, /AX
It is n.

Switching between the refresh address and the normal address is performed by an address switching circuit 603. The address switching circuit 603 is controlled by the refresh control signal RFE, and during the refresh operation (RFE=H), the outputs of the address switching circuit 603 AX I O, AX I 1. A
L to X I n Refresh address RAO, RA
The signal is at the same level as I and RAn, and during normal operation (RF
E=L) usually has addresses AIO, A, 11. Address switching circuit 603 for a signal at the same level as AIn
To! This can be realized by replacing the input AXi with the normal address AIi and the input RFAi with the refresh address RAi in the circuit shown in FIG.

First Embodiment Unlike the second embodiment, the third embodiment switches between refresh addresses and normal addresses in the address buffer as described above. Differences from the conventional example A refresh address counter is taken into the address buffer.The configuration is such that 1 bit of the counter is taken into any 1-bit address, and the output of the counter unit is sent to the next stage counter in the next stage address buffer. In other words, adjacent address buffers are connected between built-in counter units, and the address buffer as a whole constitutes a refresh counter. For example, the circuit can be configured with logic as shown in Figure 7.It is also configured with a tristate gate 701 and an inverter 702, with an input terminal IN and an output terminal O.
The tri-state gate 701 is controlled by the logic level of LIN with UT, and it is determined whether the output OUT retains the state of the previous cycle or inverts the state of the previous cycle and outputs it. With the configuration shown in Figure 7, IN goes to L level as shown in the timing chart of Figure 8. Output OUT goes to the inverse level of the previous cycle. In Figure 8, it is assumed that the previous cycle was at L level. It goes without saying that the method of implementing the counter unit is not limited to that shown in FIG.
The second stage is the output RAO1 of the previous stage, and the final stage is the output RAn-1 of the previous stage.The output terminals in FIG. The stage is the refresh address RAn. FIG. 9 shows a timing chart of the refresh clock RCK, refresh addresses RA O, RA 1 and RAn. As is clear from FIG. 9, the counter unit 602 outputs an address for counter operation Ln bits in synchronization with the refresh clock RCK.
When using the circuit shown in Figure 7, as mentioned above, all the addresses of the first clock will not necessarily go to the L level (because n-bit addresses are always output, there will be no problem with the refresh operation). If a configuration of 1,% or more is configured on an actual chip, as shown in the layout diagram shown in Fig. 10, 4 MA is a memory cell array, and 4 SA is a sense amplifier, which corresponds to 256 bits in the case of a 16 Mbit DRAM. The song and I10 switch MRD are a row decode circuit and a word line drive circuit.
1001 is address input pad and input protection port K
1002 is an address buffer, l003 is a refresh control area, 1004 is a pre-decoding circuit, and 1005 is a control signal input pad and an input protection circuit.As shown in FIG. According to the present invention, the refresh operation lines and control signal pads 100 are arranged evenly around the periphery of the chip.
5 to the refresh control circuit 1003.
The refresh clock RCK and the refresh switch RFE are input to each address buffer 1002 and transferred to the refresh clock RCK.
CK is address buffer 1 for the first stage address AO
Similarly, the refresh address signal is transferred to the address buffer 1002 for address AO (ABO) to the address buffer 1002 (ABI) for address AO. In this way, each address buffer 1002 generates a refresh address RAi corresponding to that address, and the refresh address RAi and normal address Ai are switched by the refresh switching signal RFE. The internal address AXi is input to the predecode circuit 1004, and the predecode circuit 1
Even if the predecode signal RPn is transferred from 004 to the row decode circuit RD, if it is arranged as shown in Fig. 10, the wiring of the refresh address line RFAi will be as follows. The number of wiring lines for RFA i is reduced compared to before, which prevents a decrease in operating speed during refresh.
This has the effect of preventing a decrease in normal operation speed due to a delay in refresh operation speed, and also prevents an increase in current consumption due to an increase in wiring capacitance.4 Also, the number of routing of refresh address lines RFAi is reduced. This also has the effect of simplifying the wiring layout and reducing the chip size.

41 In this embodiment, it is possible to use the refresh address itself as an increment signal for the counter. There is no change in the effectiveness of the invention.

As described in detail, according to the present invention, the number of wiring lines for the refresh address line RFAi is reduced compared to the conventional method, and as a result, reduction in operating speed during refresh is prevented. Further, it has the effect of preventing an increase in current consumption due to an increase in wiring capacitance.In addition, the wiring layout is simplified because the refresh address line RFAi is routed less, and the chip size is reduced. It also has the effect of making it possible

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a semiconductor dynamic memory device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of a decoder input stage circuit in a predecoder circuit according to a first embodiment. 4 is a chip layout block diagram of the first embodiment. FIG. 5 is a circuit block diagram of the semiconductor dynamic memory device according to the second embodiment of the present invention. FIG. 6 is a circuit block diagram of the semiconductor dynamic memory device according to the second embodiment of the present invention. FIG. 7 is a circuit block diagram of the semiconductor dynamic memory device in the second embodiment. FIG. 8 is a timing chart diagram of the counter unit in the third embodiment. 6 is a timing chart showing the operation of the counter unit group. FIG. 10 is a chip layout block diagram in the third embodiment.
Figure 1 is a circuit block diagram of a refresh counter and address buffer in a conventional example. Figure 12 is a chip layout block diagram in a conventional example.
01.1002...address buffer, 102,4
03,502...Refresh address Karankyu 1
03,405,503.1004...Pre-decode circuit 104...Decoder input stage circuit 105...Decoder, 401,406,1001.1005...Input pad and protection port! 404.1003... Refresh control same section 504... Normal decoder, 505
... Decoder for refresh 506 ... Decoder output stage same section 601 ... Address buffer input port [%
, 602... counter unit, 603...
Address switching time! 8.604... Name of address buffer output stage visiting agent Patent attorney Akira Okaji Haka 2 people Figure 2 Figure 3 fiXpi A person' - JP, Figure 6 Q: 3rd ward ■ Mateni

Claims (6)

[Claims] (1) A row that can accept multiple address inputs, has an address buffer circuit that receives each of the multiple addresses as input, and a counter that has multiple output stages, and operates a drive circuit that is directly connected to the word line. A semiconductor dynamic memory device having a predecode circuit between a path between a decode circuit and the address buffer, wherein an input stage circuit of the predecode circuit includes a plurality of outputs of the plurality of address buffer circuits and a plurality of outputs of the counter. The output is input, and one of the plurality of outputs of the plurality of address buffer circuits and the plurality of outputs of the counter is transferred from the input stage circuit as an input signal to a decoding circuit in the predecoding circuit according to a refresh control signal. The semiconductor dynamic memory device is characterized in that the decoding circuit receives the input signal and transfers a plurality of output signals to the row decoding circuit or any other circuit within the same chip. (2) A row that can accept multiple address inputs, has an address buffer circuit that receives each of the multiple addresses as input, and a counter that has multiple output stages, and operates a drive circuit that is directly connected to the word line. A semiconductor dynamic memory device having a pre-decoding circuit between a decoding circuit and the address buffer, wherein an input stage of the pre-decoding circuit has a first input stage receiving a plurality of outputs of the plurality of address buffer circuits. a decoding circuit; and a second decoding circuit that receives a plurality of outputs from the counter;
A plurality of outputs of the decoding circuit and a plurality of outputs of the second decoding circuit are input, and a refresh control signal determines which of the plurality of outputs of the first decoding circuit or the plurality of outputs of the second decoding circuit. A semiconductor dynamic memory device characterized in that one of the output stage circuits is transferred to the row decode circuit or any other circuit within the same chip. (3) A row that can accept multiple address inputs, has an address buffer circuit that receives each of the multiple addresses as input, and a counter that has multiple output stages, and operates a drive circuit that is directly connected to the word line. A semiconductor dynamic memory device having a pre-decoding circuit between a path between a decoding circuit and the address buffer, wherein the plurality of address buffer circuits include a pre-decoding circuit for each address buffer circuit, and an address switching circuit that receives the output of the address buffer and the output of the counter as input, and outputs either the output of the address buffer circuit or the output of the counter in response to a refresh control signal. , an output of the address switching circuit is transferred to an address buffer output stage circuit, and the address buffer output stage circuit transfers a signal to the predecode circuit. (4) In the semiconductor dynamic memory device according to claim 3, the input signal of the circuit for each stage of the arbitrary one counter is a refresh clock signal, and the input signal for the circuit for each stage of the arbitrary one counter is A semiconductor dynamic memory device characterized in that an output signal of the circuit is transferred to the arbitrary address switching circuit and the circuit per stage of the arbitrary other counter. (5) In the semiconductor dynamic memory device according to claim 3, one of the counters of the arbitrary plurality of counters.
The input signal of the circuit per stage is the output signal of the circuit per stage of the other arbitrary counter, and the output signal of the circuit per stage of one of the arbitrary counters. A semiconductor dynamic memory device characterized in that a signal is transferred to the arbitrary one address switching circuit and the circuit per stage of the other arbitrary counter. (6) In the semiconductor dynamic memory device according to claim 3, the input signal of the circuit per stage of the arbitrary one counter is the output signal of the circuit per stage of the arbitrary one counter. A semiconductor dynamic memory device, wherein an output signal of a circuit per stage of the arbitrary one counter is transferred to the arbitrary one address switching circuit.