JPH04178775A - Verification method for integrated circuit mask pattern - Google Patents

Abstract

PURPOSE:To cope with even noncoincidence between a mask pattern and a circuit diagram with respect to a clocked inverter by correcting second connection information and comparing first corrected connection information with second corrected connection information. CONSTITUTION:A circuit is designed, and an original circuit diagram is generated, and the mask pattern is designed based on this original circuit diagram. After circuit connection information are extracted from the circuit diagram and the mask pattern independently of each other, and parts corresponding to clocked inverters existing in these connection information are recognized, and all of these parts are corrected to connection information of combinational circuits of inverters and transfer gates, and thereafter, both connection information are compared and collated with each other. Thus, decision of noncoincidence due to clocked inverters is avoided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for verifying integrated circuit mask patterns, particularly regarding clocked inverters, and is capable of dealing with cases where a mismatch occurs between the mask pattern and the circuit diagram. The present invention relates to a method for verifying integrated circuit mask patterns.

[Conventional technology]

When designing an integrated circuit, first an integrated circuit mask pattern is designed from a circuit diagram. However, as the degree of integration of integrated circuits increases, the integrated circuit mask patterns also become extremely complex, making it extremely difficult to manually verify whether the pattern is equivalent to the original circuit diagram. Have difficulty. Conventionally, methods using computers have been used for such verification. That is, the designed mask pattern is digitized and imported as mask pattern data (or vector data), and graphic operations are performed on this to extract connection information between elements. On the other hand, information on connections between elements is captured based on the circuit diagram, and the two are compared and verified to check for any discrepancies.

[Invention or problem to be solved]

When designing an integrated circuit mask pattern from a circuit diagram, elements having the same logical function may be designed in different ways. For example, the same logic function as a clocked inverter can also be achieved by a combination of an inverter and a transfer gate. For this reason, a clocked inverter in a circuit diagram can be replaced with a combination of an inverter and a transfer gate on an integrated circuit mask pattern, or conversely, a combination of an inverter and a transfer gate in a circuit diagram can be replaced with a combination of an inverter and a transfer gate on an integrated circuit mask pattern. In some cases, the pattern may be designed by replacing it with a built-in inverter. Even if such a replacement is performed, no harm will occur to the logical operation of the element. However, when verifying the designed mask pattern, a mismatch occurs between the circuit diagram and the mask pattern because the connection relationship of the transistor elements is different in such a replaced portion. Conventionally, it has been necessary to perform verification work on such mismatched locations after modifying the circuit diagram to match the actual mask pattern.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit mask pattern verification method that can deal with the case where a mismatch occurs between a mask pattern and a circuit diagram regarding a clocked inverter.

[Means to solve the problem]

The first invention of the present application is a method for verifying an integrated circuit mask pattern for verifying whether an integrated circuit mask pattern is newer than a circuit diagram, including the step of extracting connection information of each element from the circuit diagram as first connection information. and extracting the connection information of each element from the integrated circuit mask pattern as second connection information, and from the first connection information,
Extracts a connection path using transistor elements, recognizes whether or not this connection path constitutes a clocked inverter based on the properties of the transistor elements on this connection path, and configures a clocked inverter. for,
Insert this extracted connection route part! - modifying the first connection information so as to replace it with the connection information of an equivalent circuit consisting of a transfer gate and a transfer gate, extracting a connection path using a transistor element from the second connection information, and adding a connection path on this connection path. It is recognized whether or not this connection path constitutes a clocked inverter based on the properties of the transistor elements of modifying the second connection information so as to replace it with the connection information of an equivalent circuit consisting of Inno Kuichiyo and the transfer gate; and replacing the modified first connection information with the modified second connection information. The comparison stage and the following steps are performed.

The second invention of the present application provides that in the above method, if all the transistors connected to one node are of the same type, the node is classified as class 1, and in other cases, the node is classified as class 2. A step of extracting a first path starting from the first power source, passing through only nodes of the first type, and ending at a node of the second type; A step of extracting a second path that passes through only nodes of type 1 and reaches the end point of a node of type 2, and forming a set of paths with a common end point between the extracted first path and second path. The step of extracting them as a pair involves checking the multiple input signals of the transistors on the connection path consisting of the extracted pair of paths, and determining whether there is the same signal or only one pair between both paths, and other signals are between both paths. When a logically inverted pair is formed in the connecting path, the step of recognizing that this connection path constitutes a clocked inverter is performed.

[For production]

According to the present invention, after replacing a clocked inverter with a logically equivalent combination of an inverter and a transfer gate on both the circuit diagram and the integrated circuit mask pattern, the two are compared and verified. . Therefore, even if a clocked inverter circuit and a combination circuit of an inverter and a transfer gate coexist in a circuit diagram or a mask pattern, no mismatch will occur between the two.

〔Example〕

The present invention will be described in detail below based on illustrated embodiments. 1st
The figure is a diagram showing the procedure of a method for verifying an integrated circuit mask pattern according to an embodiment of the present invention.

First, in step S1, a circuit is designed and an original circuit diagram is created. Step S2 based on this original circuit diagram
A mask pattern is designed in . The purpose of the verification method described here is to check whether the circuit diagram created in step S1 and the mask pattern designed in step S2 are equivalent.

Before explaining the actual verification procedure, a specific example where a mismatch occurs between a circuit diagram and a mask pattern regarding a clocked inverter will be explained. The circuit shown in FIG. 2 includes two MOS transistors Tl.

This is an inverter circuit made up of T2. A P-type transistor T1 and an N-type transistor T2 are connected to a power supply V.
It is connected in series between DD and GND, and the input signal I
It has a function of outputting an output signal Out which is an inversion of n.

On the other hand, the circuit shown in FIG. 3 includes two MOS transistors T3. This is a transfer gate circuit composed of T4. P-type transistor T3 and N-type transistor T
4 are connected in parallel, and the first clock signal CLK is applied to the gate of the transistor T3, and the second clock signal CLK is applied to the gate of the transistor T4. This circuit has a function as a gate that outputs the input signal In as it is as an output signal Out, or does not output it, in synchronization with the cycle of the clock signal. The circuit shown in FIG. 4 is a circuit that combines the inverter shown in FIG. 2 and the transfer gate shown in FIG. It has a function to output as . Now, in the circuit shown in FIG. 4, if each node is named a, b, b', c, and d as shown in the figure, and only the connection relationships between the nodes are extracted, the result will be as shown in FIG. 5. Here, the letters in the circles correspond to the respective nodes, and the lines connecting these correspond to the respective transistors T1 to T4. Node b'
is merged with node S because it is equipotential with node S.

The circuit shown in FIG. 6 consists of four MOS transistors T5~
This is a clocked inverter circuit composed of T8. P-type transistors T5, T6 and N-type transistors T7. T8 are connected in series between the power supply VDD and GND, and the transistors T5. A human input signal In is applied to the gate of T8, and a first clock signal CLK and a second clock signal CLK are applied to the gates of transistors T6 and T7, respectively. The function of this circuit is exactly the same as that of the circuit shown in FIG. Fourth
A circuit consisting of a combination of an inverter and a transfer gate shown in the figure is shown on a circuit diagram as shown in FIG. 7, and the circuit shown in FIG.

The quad inverter circuit is shown on a circuit diagram as shown in FIG. And these can be replaced with each other. Therefore, in the flowchart shown in FIG.
Based on the circuit diagram created in 1.
When designing the mask pattern in step 2, the designer may replace the circuit consisting of the combination of an inverter and transferate shown in Fig. 7 with the clocked inverter circuit shown in Fig. 8, or vice versa. It is also possible, and such substitutions are often made.

When the above-mentioned replacement is performed, no problem occurs in the logic operation of the circuit. However, when verifying the mask pattern designed in step S2, a mismatch will occur due to the replacement. Verification of the mask pattern involves comparing and comparing the circuit connection information extracted from the circuit diagram created in step S1 and the circuit connection information extracted from the mask pattern designed in step S2 to see if they match. carried out by. If the above-mentioned replacement is performed, the circuit connection information of both will show a mismatch. Let me show this concretely.

Now, in the circuit of Fig. 6, each node has e as shown in the figure.
If you name it -i and extract only the connections between the nodes, the result will be as shown in Figure 9. Here, the alphabet in the circle corresponds to each node, and the line connecting these corresponds to each transistor T5 to T8.

If this connection information in FIG. 9 is compared with the connection information in FIG. 5, it will be clear that the two are different and do not match. In this way, the combination circuit of an inverter and transfer gate shown in FIG. 4 and the clocked inverter circuit shown in FIG. 6 are completely equivalent in terms of logical operation, and can be replaced in terms of circuit design. . However, when these connection information are extracted, the former becomes as shown in FIG. 5, and the latter becomes as shown in FIG. 9, resulting in a mismatch between the two. Therefore, if replacement has been performed, a mismatch will occur between the circuit diagram and the mask pattern, and an error will occur as a result of verification. It is an object of the present invention to provide a verification method that does not cause such unreasonable errors. This verification method will be explained in detail below.

The basic principle of the verification method of the present invention is to extract circuit connection information from each of the circuit diagram and mask pattern separately, and then recognize the part corresponding to the clocked inverter that exists in this connection information. All parts are replaced with connection information of a combination circuit of an inverter and a transfer gate, and then both connection information is compared and verified. That is, verification is performed by the following procedure.

First, in step S3, the mask pattern is digitized. This involves importing the designed mask pattern into a computer as digital data. Subsequently, in step S4, connection information is extracted based on this digital data. This is done by performing graphic operations on graphic information expressed in digital data and recognizing each element and the phase relationship between each node. In order to recognize each element, it is necessary to set conditions such as, for example, a region consisting only of a certain diffusion layer is a resistor element, and a region where a polysilicon layer overlaps with a certain diffusion layer is a transistor. Since this type of graphical operation is well known, a detailed explanation will be omitted here. In this way, the connection information shown in FIG. 5 is extracted for the mask pattern of the circuit shown in FIG. 4, and the connection information shown in FIG. 9 is extracted for the mask pattern of the circuit shown in FIG. . In short, information indicating the phase relationship between each element and the node is extracted from the circuit diagram. Similarly, in step S5, connection information is extracted based on the circuit diagram created in step S1. The connection information extracted in step S4 and the connection information extracted in step S5 should originally be the same, but if the above-mentioned replacement has been performed, a mismatch will occur.

The circuit diagram and mask pattern connection information extracted in this way are modified in steps 86 to S8, respectively. The procedure is exactly the same for both. This modification procedure will be explained in order below.

First, in step S6, a connection path using a transistor element is extracted. This is a process of extracting a serially connected portion of a series of transistor elements that may be connection information for a clocked inverter. 6th
As is clear from the circuit diagram in the figure, the clocked inverter is constructed by connecting a plurality of transistors in series between the power supply VDD and GND. Therefore, if such transistor connection paths are extracted, the clocked inverter will definitely be included therein. The following step S7 is a process of recognizing only clocked inverters from the extracted connection paths. Even if a plurality of transistors are connected in series between the power supply VDD and GND, it is not necessarily a clocked inverter. In step S7, the extracted connection path is checked to see if it has the characteristics specific to a clocked inverter, and processing is performed to recognize only clocked inverters.

Once the clocked inverter has been recognized in this manner, in the subsequent step S8, the connection information regarding this clocked inverter is corrected. That is, a process is performed to modify the connection information regarding the locked inverter as shown in FIG. 9 to the connection information regarding the combination of the inverter and transfer gate as shown in FIG. In this way, the connection information for the circuit diagram and the connection information for the mask pattern,
When steps 86 to S8 are performed for both of the connection information, both connection information does not include connection information regarding the clocked inverter. Therefore, a comparison between the two is performed in step S9. There are no longer any discrepancies regarding clocked inverters. The above are the basic steps of the integrated circuit mask pattern verification method according to the present invention. Hereinafter, step S6 in this basic procedure. 7.8 will be explained in detail with specific examples.

FIG. 10 is a flowchart showing the specific procedure of the connection path extraction process using the transistor elements in step S6 described above, and FIG. 11 is a flowchart showing the specific procedure of the clocked inverter recognition process in step S7 described above. FIG. Hereinafter, it will be shown that the clocked inverter can be recognized by applying the procedures of steps S6 and S7 to the clocked inverter circuit shown in FIG. First, with reference to FIG. 10, a procedure for extracting connection paths using transistor elements will be described. First, in step 561, the type of transistor connected to one node is determined. The type determination here refers to determining whether it is a P type or an N type, and if something other than a transistor is connected, it is a third type (referred to as a 0 type here) that does not have any of the transistors. I will decide.

In the following step S62, branching is performed based on the determination result in step S61. That is, if all the types of transistors connected to one node are the same type, the process proceeds to step 563, and the node is classified as the first type.

In other cases, the process proceeds to step S64, and the node is classified as the second class. In step S65, the above-described classification process is repeated for all nodes.

The above classification process will be explained with reference to the specific circuit shown in FIG. That is, let us classify each of the nodes e - i of this circuit. One side of node e is connected to the power supply VDD (O
The other type is connected to the transistor T5 (P type), and it is of the second type because different types, O type and P type, are connected. One side of node f is transistor T5 (P type)
, the other is connected to the transistor T6 (P type), and since both are connected to the P type, they are of the first class. The node g is connected to the transistor T6 (P type) on one side and the transistor T7 (N type) on the other side, and is in the second class because the different types, P type and N type, are connected. One of the nodes is connected to the transistor T7 (N type) and the other to the transistor T8 (N type), and since both nodes are connected to the N type, they are in the first class. Node 1 is connected to the power supply GND (0 type) on one side and to the transistor T8 (N type) on the other side, and is of the second type because different types, 0 type and P type, are connected. The results of such classification are shown in FIG. Here, indicate a white circle or a node of the first class,
Black circles (hatched circles) indicate nodes of the second class.

In the following step S66, a first path is extracted that starts from the first power supply VDD, passes through only the first class nodes, and reaches the second class node as the end point.

Here, since the first power supply VDD is always connected to the node of the second class, it is different from the above-mentioned first path.
The path starts from a node connected to the power supply VDD (black circle), passes through one or more first class nodes (white circles), and ends again at a second class node (black circle).

In the example of FIG. 12, as shown in the figure, the node e −f =
The path g is extracted as such a first path.

In the subsequent step S67, a second path is extracted that starts from the second power supply GND, passes through only the first class nodes, and reaches the second class node as the end point.

Here, the second power supply GND is always connected to the node of the second class, so in other words, it is different from the above-mentioned second path.
The path starts from a node connected to the power supply GND (black circle), passes through one or more first class nodes (white circles), and ends again at a second class node (black circle).

In the example of FIG. 12, the nodes i −h −
The path g is extracted as a second path such as 2.

In the final step 568, the extracted first path and the second
The path is extracted as a path pair, whether it is an end point or a common path. In the above example, since the node g that is the end point of the first path and the node g that is the end point of the second path are common, these paths are extracted as a path pair. In this way, the connection route finally extracted as a path pair has multiple transistors connected in series between the power supply VDD and GND, and up to half of the route are P-type transistors, and the remaining half are N-type transistors. Each type of transistor is connected to the other path. A connection path for a clocked inverter is always such a path. However, the path pair extracted in this way does not necessarily become a connection path for a clocked inverter. Therefore, clocked inverter recognition processing in step S7 is required.

Then, the clocked inverter recognition procedure will be explained with reference to FIG. First, step S7
1, a plurality of input signals of transistors on a connection path consisting of a pair of paths extracted in step S68 are examined. In the example of FIG. 12, the input signal to transistors T5 and T8 is signal In, and transistor T6
The input signal to transistor T7 is signal CLK, and the input signal to transistor T7 is signal CLK. In the following step S72, it is determined whether there is only one pair of identical signals between the first path and the second path, and in step 873, the other signals form a logically inverted pair between the two paths. It is determined whether If a positive determination is made in either case, this path pair is recognized as a clocked inverter in step S74. In either
If a negative determination is made, it will not be recognized as a clocked inverter. In step S75, the same determination is repeated for all path pairs, and all clocked inverters are recognized. Let's apply the above processing to the example shown in FIG. First, in step S72, the signal In is applied to the first path, and the same signal In is applied to the second path as input signals, and since there is only one such pair of identical signals, , a positive judgment is made. In the following step 573, since the remaining signal CLK on the first path and the remaining signal CLK on the second path form a logically inverted pair,
After all, a positive judgment is made. In this way, the path pair shown in FIG. 12 will be recognized as a clocked inverter.

The specific techniques of steps S6 and S7 in the procedure of FIG. 1 have been described above, and finally, the specific technique of the connection information correction process in step S8 will be explained. This process only requires that a plurality of first class nodes on the connection paths recognized as clocked inverters be combined into one node. For example, in the example shown in FIG. 12, the nodes of the first class (white circle nodes f and h) may be combined into one node and modified as shown in FIG. 13. here,
If you compare the connection information in FIG. 13 with the connection information in FIG. 5, you will find that the two are equivalent. That is, the connection information modified as shown in FIG. 13 is connection information for a circuit consisting of a combination of an inverter and a transfer gate. In this way, the connection information for the clocked inverter circuit is all modified to the connection information for the circuit consisting of a combination of an inverter and a transferate, and in the comparison and verification in step S9 of FIG. Inconsistencies regarding inverters no longer arise.

In the above explanation, an example was given in which the method of the present invention is applied to a clocked inverter circuit using four transistors as shown in FIG. 6, but the present invention can also be applied to other clocked inverter circuits. The same can be applied. For example, a clocked inverter circuit using eight transistors T9 to T16 as shown in FIG. 14 operates using three clock pairs (CLKI to CLK3 and CLKI to CLK3, which are the inverted versions of these clock pairs). In this circuit, when nodes j-r are defined as shown in the figure and connection information is extracted, the result is as shown in FIG. 15. If the connection path extraction process using the transistor element in step S6 is performed on this, nodes j and n are obtained.

r is a class 2 node (black circle), the nodes are l, m,
o.

p and q become nodes of the first class (white circles), and as shown in the figure, a path pair consisting of a first path and a second path is extracted.

This path pair is recognized as a clocked inverter in step S7. Then, in step S8, all nodes of the first class (white circles) are combined into one,
In the end, the connection information will be modified to be equivalent to that shown in FIG.

The integrated circuit mask pattern verification method according to the present invention has been described above with reference to one embodiment, but the present invention is not limited to the method of this embodiment, and can be implemented in various other ways. .

[Effects of the Invention] As described above, according to the present invention, regarding the connection information obtained from both the circuit diagram and the mask pattern, the part corresponding to the clocked inverter circuit is replaced with a combination circuit of an inverter and a transformer 77 gate. Since they are modified to correspond and then compared and verified, there is no longer a mismatch caused by the clocked inverter.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the procedure of an integrated circuit mask pattern verification method according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an inverter circuit constituted by two MOS transistors TI and T2, and FIG. Two MOS transistors T3
．． A circuit diagram showing a transfer gate circuit configured by T4, FIG. 4 is a circuit diagram showing a circuit combining the inverter shown in FIG. 2 and the transfer gate shown in FIG. 3, and FIG. Figure 6 is a circuit diagram showing the extracted connection relationships; Figure 6 is a circuit diagram showing a clocked inverter circuit configured by four MOS transistors T5 to T6; Figure 7 is a circuit diagram of a circuit consisting of a combination of an inverter and a transferate. Figure 8 is a diagram showing the symbols on the circuit diagram of the clocked inverter circuit, Figure 9 is a diagram showing the connection relationship extracted from the circuit in Figure 6, and Figure 1O is the diagram shown in Figure 1. FIG. 11 is a flowchart showing the specific procedure of the connection path extraction process using the transistor elements in step S6 shown in FIG. Figure 12 shows the 10th circuit for the circuit shown in Figure 6.
Figure M13 is a diagram showing the result of modifying the connection information shown in Figure 12 according to the present invention, and Figure 14 is a diagram showing the result of applying the procedure shown in the figure.
FIG. 15 is a circuit diagram showing a clocked inverter circuit constructed using T16, and is a diagram showing the result of applying the procedure of FIG. 10 to the circuit shown in FIG. 14. a-r...node, T1-T16...transistor. Patent applicant: Dai Nippon Printing Co., Ltd. Applicant's agent Hiroshi Shimura Figure 1 ND Figure 4 DD GND Vo. GND Figure 6 LK Figure 9 Figure 10 Figure 11 DO GND Figure 12 Figure 13 Figure 14 Figure 15

Claims (2)

[Claims] (1) In an integrated circuit mask pattern verification method for verifying whether an integrated circuit mask pattern is equivalent to a circuit diagram, the step of extracting connection information of each element from the circuit diagram as first connection information; a step of extracting the connection information of each element from the integrated circuit mask pattern as second connection information; extracting a connection path by the transistor element from the first connection information; It is recognized whether the connection path of the lever constitutes a clocked inverter, and if it constitutes a clocked inverter, the extracted connection path is converted into an equivalent circuit consisting of an inverter and a transfer gate. modifying the first connection information so as to replace it with circuit connection information; extracting a connection path using transistor elements from the second connection information; It is recognized whether the connection path of the lever constitutes a clocked inverter, and if it constitutes a clocked inverter, the extracted connection path is converted into an equivalent circuit consisting of an inverter and a transfer gate. modifying the second connection information so as to replace it with circuit connection information; and comparing the modified first connection information with the modified second connection information. Featured integrated circuit mask pattern verification method. (2) In the method according to claim 1, if all the transistors connected to one node are of the same type, that node is classified as class 1; otherwise, the node is classed as class 2. A step of extracting a first path starting from the first power source, passing through only nodes of the first type, and ending at a node of the second type; a step of extracting a second path that passes through only nodes of type 1 and reaches the end point of a node of type 2, and a path that has a common end point between the extracted first path and second path is combined into a set of paths. The step of extracting them as a pair involves examining the multiple input signals of the transistors on the connection path consisting of the extracted pair of paths, and determining whether there is only one pair of identical signals between both paths, and other signals between both paths. A method for verifying an integrated circuit mask pattern, comprising: recognizing that the connection path constitutes a clocked inverter when the connection path forms a logically inverted pair.