JPH09274621A - Function extracting method for lsi sequential circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extract the function of a circuit even in the case of a JK-FF having complicated loop configuration or a circuit having a shift register, etc., by finding a stable state by replacing sequential circuit with a combination circuit, and performing signal tracking. SOLUTION: First of all, a loop is detected (a) while making an LSI sequential circuit to perform function extraction into a directed graph. Next, all the loops of the sequential circuit are cut off (b) so as to decrease the number of cutting points as much as possible. Afterwards, stable conditions are made into logics (c) so as to provide the stable state of letting no signal change occur at any node of the circuit and based on the stable conditions made into logics, the solution is found (d). While using the pair of provided stable states, the original input is changed, the state transition in the output value from the circuit excluding excessive gates from the combination circuit is extracted (c) and the state transition table of the output value is prepared. Then, reach possibility is tested and the reach disable stable state is removed from the state transition table (f). Thus, the function is extracted from the transition table.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to verification of LSI operation, and more particularly to extraction of circuit function (logic).

[0002]

2. Description of the Related Art In recent years, various LSIs represented by ASICs have been required to have higher integration and higher functions due to the trend toward higher performance and lighter and smaller electronic devices. That is, there is a demand for an IC such as an ASIC to realize a high function by minimizing the chip size as much as possible. The production of ICs such as the ASICs described above is based on functions, logic design,
After the circuit design and layout, etc., the pattern for the photo mask pattern is produced, the photo mask is produced using this, and the photo mask pattern is transferred onto the wafer by reduction projection exposure, etc. Is to do. Conventionally, when there is a design change at the stage of layout design, the operation is returned from the transistor level to the logic circuit, and the operation is verified here. In this operation verification, the sequential circuit is regarded as the holding circuit at the logic level at the logic level, and the processing is performed by paying attention to the data signal and the control signal entering therein. Then, the operation (circuit function) of the LSI is obtained from a series of input data signals and output data signals, that is, the operation (circuit function) of the LSI is obtained from the process of fitting the form (of the input data signal). JK-F with complicated loop structure like 18
In the case of a circuit including F, a shift register, a counter, etc., this has a problem that the operation (circuit function) cannot be obtained.

[0003]

As described above, in the case of a circuit having a JK-FF having a complicated loop structure, a shift register, a counter, etc., the operation of the LSI (circuit It was difficult to specify (function), and it was necessary to deal with it. Under such circumstances, the present invention intends to provide a method for extracting the function (operation) of a circuit even in the case of a circuit having a JK-FF having a complicated loop configuration, a shift register, a counter, or the like. To do.

[0004]

A method for extracting a function of an LSI sequential circuit according to the present invention is a method for extracting a circuit function from a sequential circuit given by an effective graph including a loop to which logic gates are connected. In order, (A) a step of detecting all loops of the sequential circuit, (B) a step of disconnecting all loops of the sequential circuit so that the number of disconnection points is minimized, and (C) a signal value at each disconnection point P _i . _Is defined as a state variable Q _i, and the disconnection point P _{i is set} so that, after disconnection, a stable state where no signal change occurs in any node of the circuit.
To the node on the feedback input side of the feedback side logic gate of the corresponding original loop of
and to have an input terminal _i to the node for all loop, 'the steps of equal and _i, (D) state variables Q _i and the state variable Q' state variable Q _i and state variables Q and _i Are logically expressed by an exclusive OR, and the output value of the OR of all the obtained output values of the exclusive OR is set to 0, and finally, the original input which is not the feedback input and the above-mentioned In the combinational circuit with all state variables Q ′ _{i of (1)} as an input, a stable state is obtained by formulating and solving the logical formula, and (E) based on the stable state obtained in (D) above. , The operation of tracing the signal change when the input of the circuit is changed to obtain the final state is repeated for the required data signal pattern of the original input, and one axis is in the stable state and the other axis is in the input pattern. Represents the final state matrix with Creating a state transition table, (F) further testing reachability and removing unreachable stable states, (G) state transition table obtained in (E) and (F) above In the sequence of input patterns to extract the function of the circuit, and (H)
And a step of preparing a function table of the circuit from the function (logic) obtained in the above (G). Then, when the function (logic) table of the circuit in the step (H) is produced, a step of compressing the obtained function (logic) is included.

[0005]

The function extracting method of the LSI sequential circuit according to the present invention has such a configuration that even in the case of a circuit having a JK-FF having a complicated loop configuration, a shift register, a counter, etc. It is possible to provide a method for extracting a function (operation). Even in a sequential circuit having a complicated loop that does not depend on the shape of the circuit, it is possible to extract the circuit function (operation) by the approach of replacing with a combinational circuit to obtain a stable state and performing signal tracking. Specifically, (A) a step of detecting all loops of the sequential circuit, (B) a step of disconnecting all loops of the sequential circuit so that the number of disconnection points is minimized, and (C) each of the disconnection points P _i
The signal value at is defined as the state variable Q _i , so that, after disconnection, a stable state where no signal change occurs in any node of the circuit is performed so that the feedback side logic gate of the corresponding original loop of the disconnection point P _i is Replacing the node on the feedback input side with an input terminal of a node for changing the state variable Q ′ _i, and making the state variable Q _i equal to the state variable Q ′ _i for all loops; D) The condition variable Q _i and the condition variable Q ′ _i are logically expressed by an exclusive OR, and the output values of all the obtained output values of the exclusive OR are set to 0, Finally, a step of obtaining a stable state by formulating a logical expression and solving the logical expression with a combinational circuit using the original input which is not a feedback input and the above-mentioned all state variables Q ′ _i , and (E) the above The stable state obtained in (D) In addition, the work of tracing the signal change when the input of the circuit is changed to obtain the final state is repeated for the necessary data signal pattern of the original input, and one axis is set to the stable state and the other axis is set. Creating a state transition table representing a matrix of final states with the input pattern as a parameter; (F) further testing reachability to remove unreachable stable states; and (G) said (E). ), A step of extracting the function of the circuit by checking the state transition table obtained in (F) in the column of the input pattern, and (H) a function table of the circuit from the function (logic) obtained in (G) above. This is achieved by comprising the steps of making. In addition, by including the step of compressing the obtained function, the function is easier to understand and there are few mistakes.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a function extracting method for an LSI sequential circuit according to the present invention will be described with reference to the drawings. FIG. 1 shows an LSI of the embodiment
It is a flow chart of a function extraction method of a sequential circuit, and this embodiment will be described below with reference to FIG. First, the LSI sequential circuit whose function is to be extracted is made into a directed graph, and a loop is detected. (FIG. 1A) The directed graph is represented by logic gates such as AND, OR, and NAND and the nodes connecting the logic gates, and the signal direction is represented by the direction of the arrow of the node. A loop is a part that forms a closed route when a signal is followed along this arrow. For example, in the case where the directed graph is represented as shown in FIG. 2A, the signals are visiting from the gate A to the gates B, C, D to the gate E by following the order of the arrows. The signal enters gate C, but goes through the same gate that has already been passed to gates D and E. That is, a closed route is formed between the gates C, D, and E, and this is a loop. In the actual processing, a depth-first round is performed from the input terminal in the direction of output, the gate and the node are stacked on the stack when the gate is visited, and the stack is unloaded on the return. Here, returning refers to when no further progress is made or when a loop is detected. If the visiting gate is stacked on the stack, it is determined that the loop is up to that point, and the stack refers to the corresponding node to obtain the note set that constitutes the loop. In the case of FIG. 2A, as shown in FIG. 2B, the gate and the node are sequentially stacked in the stack, and the gate C and the node c are stacked after the gate E and the node e. It is already on the stack and it is determined that a loop has been formed. In this way, all loops of the sequential circuit are detected.

Next, all the loops of the sequential circuit are cut so that the number of cut points is reduced as much as possible. (Figure 1
(B)) The reason for reducing the number of cutting points as much as possible is to reduce the number of calculation points described later as much as possible by reducing the number of cutting points as much as possible. A method of minimizing the number of disconnection points will be described with reference to the sequential circuit in the form of a directed graph having four loops shown in FIG. In addition, in FIG. 3, Q1, −
Q1, Q2, -Q2, Q3, Q4, Q5, Q6, Q7 are node names, and L1, L2, L3, L4 are loop names.
Extracting the constituent nodes for each loop is shown in FIG.
The frequency that appears in the loop of each node is
It becomes as shown in FIG. In FIG. 4B, it is clear that if the node with the highest frequency (-Q4) is disconnected, more loops can be disconnected at once, and if the node (-Q4) is disconnected first, the loops L2, L3, L4 are cut.
Is cut. Next, the same processing is performed on the loops that have not been cut, until all the loops are cut. In this case, as shown in FIG. 4C, the only loop that is not broken is L1, and the constituent nodes are -Q2 and Q2. As shown in FIG. 4D, the frequency of each constituent node is It becomes 1, and -Q2 or Q2 may be cut off. As described above, in the case of the directed circuit in the directed graph shown in FIG. 3, by disconnecting the node -Q4 and -Q2 or Q2, all loops are disconnected,
Moreover, the number of cuts can be minimized. Separately, loop L
1 for Q2, loop L2 for Q4, loop L3 for Q
6. In the loop L4, even if Q7 is cut, the whole loop can be cut, but in this case, the total is cut at 4 points, which is not the minimum. Actually, the operation of minimizing the number of disconnections is performed by expressing the above frequency by the value of the counter, and its flow is shown in FIG.

Next, after the disconnection, the stability condition is logically expressed (logical diagram) so that any node of the circuit is in a stable state in which no signal change occurs. (FIG. 1 (c)) For example, in the case of a sequential circuit having a loop shown in FIG. 6 (a) and having a signal value at P point defined by a state variable Q, the loop is cut at P point. In order to achieve a stable state in which no signal change occurs at any node in the circuit,
As shown in FIG. 6B, instead of the feedback input side node of the feedback side logic gate shown in FIG.
When expressed as a (combination) circuit having an input terminal of a node whose state variable is Q ', it is necessary that Q and Q'be equal. That is, when the signal value at each cutting point P _i to be processed is defined as the state variable Q _i , the cutting point P _i
To the node on the feedback input side of the feedback side logic gate of the corresponding original loop of
It is a stable condition of the disconnected combinational circuit that the state variable Q _i is equal to the state variable Q ′ _i for all loops by providing the input terminal of the node for _i . The total cut point P _i, the exclusive OR is 0 and Q _i and Q _'i, and was obtained with respect to the total cutting point P _i, the output of the logical sum of the output values of all of the exclusive OR The value becomes 0. That is, for each cutting point P _i , the logical expression (logical diagram) shown in FIG. 7 is established, and the logical expression (logical diagram) shown in FIG. 8 is established.

Next, a solution is obtained for the stability condition thus logically formulated (logical diagram). (Figure 1
(D)) In the end, as shown in FIG. 9, in the combinational circuit, the input pattern with the output z of 0 is obtained. In other words, a set [qi] that makes a stable state is obtained. The number of disconnections is n1, the number of original input terminals is n2, and n = n1.
In the case of + n2, it can be obtained by a method of selecting a combination having an output value of 0 out of 2 ⁿ combinations.

Next, using the obtained set of stable states [qi], the original input is changed, and an extra gate (Ex added to obtain the stable state is obtained from the combination circuit shown in FIG. 9).
-OR gate, OR gate) is used to extract the state transition of the output value of the circuit. (FIG. 1E) Then, a table showing the state transition of the output value (hereinafter referred to as a state transition table) is created as shown in FIG. FIG. 10 shows a matrix M in which rows are stable state sets [qi] and columns are input patterns. The element Mij of the matrix M indicates the final state when the signal value of the original input terminal is changed from the stable state [qi] to Xj. Further, depending on the circuit, there is a constraint that the synchronous circuit does not change the input and the clock at the same time, and in such a case, only the required Mij is obtained. Hereinafter, such Mij is referred to as a valid transition. The flow of state transition table creation is shown in FIG.
The process is briefly shown below. Briefly, the procedure for initializing the circuit by the stable state set [qi], changing the input terminal (to Xj which is a valid transition), and tracking the signal change in time series is performed for all stable states. This is repeated for the set [qi].

Since the set of stable states [qi] is represented by the original input terminal and the original feedback input side state variable (Q ' _i ), this is set as an input variable in the circuit after the loop break. , Spread throughout the circuit. Since this circuit is a combinational circuit, it is not particularly difficult. This is called circuit initialization. After this, after temporarily restoring the broken loop of the circuit, change the input terminal to Xj,
The signal is traced, and when the final state is obtained, it is described in the matrix, and the restored loop is returned to the disconnected state.
The circuit status is expressed as a set of values for all nodes, but it is inefficient to represent the status in the middle with all nodes, so
The circuit state in the middle of each process is represented only by the node changed from the initial circuit state. Also, when the input terminal is changed to Xj and the signal is traced, if the circuit is in a transitional period, that is, if the same circuit state has not existed in the past,
The output, that is, the value of the node is obtained and set for the gate of the input change, and the circuit state is registered. Specifically, the output value of the gate of the input change is once obtained for each work area, and when all the evaluations of the target gate are completed, the work area is set to the corresponding node. When the input terminal is changed to Xj and the signal is traced, if the circuit is not in the transitional period, that is, if the same circuit state has existed in the past, does it converge as shown in FIG. , Fig. 12
It either oscillates as shown in (b). The convergence shown in FIG. 12A indicates that a certain stable state (S3) has been reached. The oscillation shown in FIG. 12 (b) is
It is a case where a circuit state is not determined to be a certain state and a plurality of states are repeated. Note that, in FIG. 12, Si indicates a circuit state, and as described above, the circuit state is expressed as a set of values of all nodes. The circuit state of is the initial circuit state S
Only the nodes changed from 1 will be represented. That is, in FIG. 13, Si indicates a circuit state, and the initial circuit state of S1 is nodes a1, a2, a3, a4,
a5 is a state having respective values of 0, 1, 0, 1, 1. The values of the nodes a1 and a2 from S1 are 1 and 0, respectively.
The state changed to S2 is S2, and the state where the values of the nodes a2 and a3 are changed from S2 to 1 and 1 respectively is S3.
Regarding 3 as well, only the difference from the initial S1 is shown, and the values of the nodes a1 and a3 are changed from S1 to 1 and 1, respectively. As an actual procedure, the difference between S2 and S2 is obtained by merging. Incidentally, the merging is a process of excluding a common node and leaving the other nodes as they are. When the circuit state is represented by Sj, the difference dj-1 between Sj and Sj-1.
If is empty, it can be determined to be converged. If no, the same state in the past can be determined to oscillate, and if not, the transition can be determined to be the same.

Next, reachability is tested to remove unreachable stable states from the state transition table. (FIG. 1 (f)) The state transition table is nothing but the transition from one stable state to another stable state except oscillation. In FIG. 14A, the stable state [q1] is unreachable because there is no transition source.
Even in (b), the stable state [q1] cannot be reached because there is no transition source, and the stable states [q2] and [q5] are also chained. The flow for testing reachability is illustrated in FIG. When this is applied to FIG. 14B, stable states [q1], [q2], [q3], [q4], [q5]
Respectively have in-degrees of 0, 2, 2, 1, 2. First, since the in-degree of the stable state [q1] is 0, that is, it is unreachable because there is no transition source, the in-degrees of the stable states [q2] and [q5] are reduced. As a result, the stable state [q5]
However, since the in-degree becomes 0 and becomes impossible, the in-degree of the stable state [q2] is further reduced, and the in-order of [q2] becomes 0 and becomes impossible.

Next, the state transition table is examined in the column corresponding to a certain input pattern Xj, and it is determined whether the value is a fixed value of 0 or 1, is held, or is inverted. The state transition table shown in FIG. 16A will be described. The state transition table shown in FIG. 16A is a state transition table related to the D latch circuit having inputs Id and Ic and outputs Q and Q ′ shown in FIG. 16B. In FIG. 16A, the horizontal axis is the original input pattern, which is 00, 01, 10, 11 in this case. The vertical axis represents the stable state, and in this case, six are obtained. As described above, the stable state is represented by a set of the original input terminal and the original state variable of the feedback input side, and in this case, it is a set of two original input terminals and one state variable of the feedback input side. . In the first line, there is 00:00 [01], but the first 00 is the pattern of the input terminal and the next 0 after: is the value of the original state variable on the feedback input side. Although 01 in [01] is a table of output terminal Q and Q'values, this is a value before transition and is obtained by initialization of the circuit as described above. The elements [..] in the table are the values of the output terminals Q and Q'after the transition. First, input pattern 00
In the case of the output value column (first column), the first output terminal Q is examined. It is a portion B in FIG. When B is viewed from the top to the bottom, it is 010011, and the value is not fixed, but the value before the transition (portion A in FIG. 16).
When compared with A, A is also 010011. That is,
The output terminal Q at the input 00 holds the state before the transition and is judged to be held. The same applies to the second output terminal Q '. Next, regarding the column of output values (second column) in the case of the input pattern 01, the first output terminal Q is examined. It is a portion C in FIG. When C is viewed from the top to the bottom, the value is 000000, and the value is the fixed value 0. That is, the output terminal Q is determined to be 0 regardless of what is before the transition. In this way, by comparing the state before the transition and the state after the transition, the function shown in FIG. 17A is extracted from the transition table of FIG. 16A. Then, a table obtained by compressing this function table becomes a function table shown in FIG.

Function interpretation (judgment) from the state transition table
If the result is uncertain at the stage, check the possibility of shift register and counter. First, a certain output terminal Q
The comparison before and after the transition of _i is performed with another output terminal Q _j .
That is, it is fixed at Q _i after the transition and Q _j before the transition.
If it is judged to be held at a certain Q _j , the output terminal Q
_It is determined that the value of _j is shifted to the value of the output terminal Q _i , and it is determined that the value is a shift register. The result is
If uncertain, check the possibility of the counter. However, this processing is performed only when this circuit from the outside is a counter and which output terminal group is a word as a counter is given. Since words are usually several bits, it is not very efficient to detect words automatically from the output terminals (processing is possible), and it is easy to give such auxiliary information. So I'm doing this. The process compares before and after the transition in word units. This comparison looks at the word as a binary integer and sees if it is incremented or decremented.

[0015]

As described above, the method for extracting the function of the LSI sequential circuit of the present invention enables the function extraction of the circuit without being influenced by the complexity of the circuit state. Specifically, even in the case of a JK-FF having a complicated loop configuration, a circuit having a shift register, a counter, etc., the function (operation) of the circuit can be extracted, and the function extraction processing can be performed as compared with the conventional method. Expanding the circuit range. As a result, the LSI circuit design can be reworked with reliability, and the operation verification work of the circuit can be made more accurate.

[Brief description of drawings]

FIG. 1 is a schematic process diagram showing a method of extracting a function of an LSI sequential circuit according to an embodiment.

FIG. 2 is a diagram for explaining loop detection.

FIG. 3 is a diagram of a sequential circuit represented by a directed graph having four loops.

FIG. 4 is a diagram for explaining a method of minimizing the number of cutting points.

FIG. 5 is a flow chart of a method for minimizing the number of cutting points.

FIG. 6 is a diagram for explaining loop cutting.

FIG. 7 is a diagram of a logical expression (logical diagram) using Ex-OR.

FIG. 8 is a diagram of a logical expression (logical diagram) using OR.

FIG. 9 is a diagram of a logical expression (logical diagram) of a combinational circuit.

FIG. 10 is a diagram of a state transition table

FIG. 11 is a flowchart for creating a state transition table.

FIG. 12 is a diagram for explaining a circuit state.

FIG. 13 is a diagram for explaining circuit state management.

FIG. 14 is a diagram for explaining reachability.

FIG. 15: Reachability test flow diagram

FIG. 16 is a diagram of a state transition table

FIG. 17: Function table diagram

FIG. 18 is a logical diagram showing JK-FF.

[Explanation of symbols]

L1, L2, L3, L4 loop Q1, -Q1, Q2, -Q2, Q3, Q4, Q5, Q
6, Q7 node name

Claims (2)

[Claims] 1. A method for extracting a circuit function from a sequential circuit given by an effective graph including a loop to which logic gates are connected, the method comprising: (A) detecting all loops of the sequential circuit; (B) A step of disconnecting all loops of the sequential circuit so that the number of disconnection points is minimized, and (C) a signal value at each disconnection point P _i is a state variable Q _i.
And, after disconnection, change to a node on the feedback input side of the feedback side logic gate of the original loop corresponding to the disconnection point P _i so that any node of the circuit is in a stable state where no signal change occurs, the state variable 'made to have an input terminal _i to the node for all loop state variables Q _i and the state variable Q' Q the steps of equal and _i, (D) state variables Q _i and state The variables Q ′ _i and the same condition are logically expressed by exclusive OR, and the output value of the logical OR of all the obtained output values of exclusive OR is set to 0, and finally, it is not a feedback input. an input, a combination circuit that receives the total state variable Q _'i of the, logical formalized, by solving the formulas, determining a stable state, stability obtained in (E) above (D) Based on the state, change the input of the circuit By repeating the work of tracing the signal change at the time to obtain the final state by the necessary amount of the original data signal pattern of the input, one axis is used as a stable state and the other one axis is used as a parameter for the final state matrix. Creating a state transition table as shown, (F) further testing reachability and removing unreachable stable states, (G) states obtained in (E) and (F) above (H) a step of examining the transition table with the columns of the input pattern and extracting the function of the circuit;
LS, which comprises a step of creating a circuit function table from the function (logic) obtained in (G) above.
Function extraction method of I sequential circuit. 2. The function (logic) obtained when the function (logic) table of the circuit in step (H) of claim 1 is prepared.
A method of extracting a function of an LSI sequential circuit, which comprises the step of compressing