JPH04177907A - Input circuit - Google Patents

Abstract

PURPOSE:To attain the normal operation even when a DC bias at an input terminal is fluctuated by connecting an output of a 1st switching FET in a couple of switching FETs to a gate of a 2nd switching FET via a capacitor. CONSTITUTION:A capacitor C1 is arranged between a drain electrode of a switching FET 101, that is, an output 119 and a gate electrode of a FET 102. The capacitor C1 delivers a potential change in the drain electrode 119 to a gate electrode of the FET 102. Since a potential change at a node 119 is opposite phase to a potential change fed to a gate of the FET 101, the FETs 101, 102 are operated at an opposite phase, that is, the FETs act like biphase drive type FETs. Thus, even when a DC level at the input terminal is fluctuated due to any cause, the two output DC levels opposite to each other in the differential amplifier circuit are prevented from being parted, the overlapped waveform is kept large and the operation of the differential amplifier circuit is kept normal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to input circuits, and more particularly to single-phase drive input circuits.

[Conventional technology]

There are two types of conventional differential input circuits: single-phase and dual-phase.
A double-phase type is preferable because it can increase the circuit gain and reduce the input amplitude accordingly, but the input signal is usually single-phase, and it is not possible to create an opposite-phase signal from the input signal to make it dual-phase. , (1) The circuit becomes complicated, (2)
As the input frequency increases, it becomes difficult to create completely opposite phases, so single-phase input circuits are currently used.

FIG. 3 shows a conventionally used single-phase drive type input circuit. In FIG. 3, FETs (field effect transistors) 101 and 102 constitute a differential circuit with load resistors 103 and 104, respectively, and FET 105 is a constant current source thereof. The FETs 106 and 108 and the two level shift diodes 107 form a first source follower type bias generation circuit, and the gate bias of the source follower FET 106 is supplied from dividing resistors 110 and 111, and the output of this bias generation circuit is Terminal 109 is FETl0I
is applied to the differential circuit via the RF multiplier signal terminal 109 connected to the gate electrode of and applied to the input terminal 118,
Performs single-phase operation.

Further, the second bias generation circuit includes FET112°114
and 2 (1) level shift diode 113, and the gate bias of FET 112 is set by dividing resistor 11.
The output 115 of the bias generating circuit is connected to the gate electrode of FET 102 and serves as a reference (comparison standard) voltage. Here, V DD +
V5s is the respective power supply voltage.

FIGS. 4(a) to 4(c) show the results of the computer simulation shown in FIG. 3 as characteristic diagrams.

In FIGS. 4(a), (b), and (c), the voltage at the input terminal 118, the voltage at the input 109 of the differential circuit, and the output 11
5 (reference voltage), and the waveforms of the voltages at outputs 119 and 120 are shown using only arithmetic numerals.

Problem to be Solved by Invention C] However, in the conventional differential circuit described above, if a deviation of, for example, ±200 mV occurs in the DC bias value of the input terminal 118, the difference as shown in FIGS. 4(b) and 4(c) occurs. Just like that,
The DC components of the waveforms of outputs 119 and 120 are distorted,
This has the disadvantage that the symmetry of the output waveform is lost. According to the experimental results using the device manufactured by the present inventors, the overlapped portions of the output waveforms (Fig. 4(b), Fig. 4(c))
It was found that when the voltage (shaded area) below 400 mV, normal operation was no longer exhibited.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input circuit which solves the above-mentioned drawbacks and which operates normally even if the DC bias value of the input terminal fluctuates.

[Means to solve the problem]

The configuration of the input circuit of the present invention includes a bias generation circuit composed of a source follower FET, a level shift diode, and a constant current source, a pair of loads, and a single-phase circuit in which an input signal is applied to the gates of a pair of switching FETs. a drive differential circuit, the first of the pair of switching FETs
The output of the switching FET is connected to the second switching FET via the capacitor.
It is characterized in that it is connected to the gate of the switching FET.

〔Example〕

Next, the present invention will be explained using the drawings.

FIG. 1 is a circuit diagram showing an input circuit according to an embodiment of the present invention.

In FIG. 1, this embodiment differs from the conventional circuit diagram shown in FIG. 3 in that the capacitor C1 is a switching FET 10.
This example is the same as the conventional example shown in FIG. 3, except that the second bias generating circuit shown in FIG.

Now, the capacitor C1 transmits the potential change of the drain electrode 119 of the FET 101 to the gate electrode of the FET 102. Here, since the potential change at the contact 119 is in opposite phase to the potential change applied to the gate of the FET 101, the FE
T1ol and 102 operate in opposite phases, that is, the operating state is the same as that of the dual-phase drive type.

To explain the operation of FIG. 1, reference is made to FIG.

First, consider the case where the second bias generation circuit is not removed. FIG. 5 is its circuit diagram. First, it is preferable that the magnitude of the potential change appearing at the electrode of the FET 102 via the capacitor C1 is large, since this becomes close to a perfect dual-phase drive type. It can be said that the larger the value of the capacitor C1 is, the smaller the loss in the capacitor C1 becomes, and the magnitude of the potential change becomes larger. Therefore, it is preferable that the value of the capacitor C1 is large. However, from the viewpoint of high-speed operation, that is, when considering the time constant at node 115, it is preferable that the value of capacitor C1 be small. From the above, it can be seen that there is an upper limit value for the value of the capacitor C1. Load resistance 1
The value of 03,104 is 750Ω, and the gate width of FET10I, 102 is 20 μm.

Mutual contactance 360m5/mm, threshold voltage -0,
6(a), (b), and (c) show the results of a computer simulation performed using a differential circuit of 1.0 mm and a value of 0.1 pF for the capacitor C1. Figure 6(a),
(b).

In (C), it can be seen from the waveforms of the inputs 109 and 115 of the differential circuit that it operates in a dual-phase drive type, but the amplitude of the input 115 is small and the amplitude of the output 119 is shown in Figure 4 (b). , is smaller than the case of (c), so the DC bias value of input terminal 118 ±200 m
The size of the overlapping part of the output waveforms 119 and 120 (shaded areas in Figures 6(b) and (c)) when V is shifted is as follows from the case of Figures 4(b) and (c). I can't see any significant improvements. This is due to the large impedance at the bias point where node 115 is located.

Next, consider the case (FIG. 1) in which the second bias generating circuit of the embodiment of the present invention is removed from this circuit. At this time, the DC component of node 119 is cut by capacitor C1, so node 115 is in a floating state. The AC component of node 119 is input to node 115 via capacitor C1, which turns FET 102 ON and OFF.
At the same time, the DC bias of the node 115 is brought closer to the DC bias of the node 109. Furthermore, since the load from the second bias generation circuit is removed, the potential at the node 115, in other words, the gate potential of the FET 102 of the differential circuit becomes more likely to change.

Actually, the results of a computer simulation performed on the circuit shown in FIG. 1 with the capacitor C1 set to 0.1 pF are shown in FIGS. 2(a), (b), and (c). As is clear from Figure 2 (a), (b), and (c),
The potential change at the node 115 has been greatly improved compared to the case shown in FIG. The shaded areas in b) and (c) have also been improved. As an example, if we look at the case where the DC bias value of the input terminal 118 is shifted by +200 mV, the overlap of the outputs 119° and 120 is as shown in Fig. 4 (c
) is 480 mV, and is 440 mV in the circuit shown in FIG. 6(c) in which the capacitor C1 is loaded and the second bias generating circuit is not removed. However, in the circuit in which the capacitor C1 is added and the second bias generation circuit is removed, the value of the overlapped portion is 11 as shown in the result shown in Fig. 2(c).
00 mV, which shows that it has been improved by 620 mV.

〔Effect of the invention〕

As is clear from the above explanation, the present invention provides input D
It is resistant to fluctuations in C level, and the DC level of the input terminal is internal.
Even if it fluctuates due to some external factor, it suppresses the deviation in the DC level of the two specific forces that are in opposite phases to each other in the differential circuit,
This has the effect of keeping the overlap of waveforms as large as possible, thereby maintaining normal operation of the differential circuit placed in the next stage.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an input circuit of an embodiment of the present invention, FIGS. 2(a) to 2(c) are characteristic diagrams showing computer simulation results of the embodiment of FIG. 1, and FIG. 5 and 5 are circuit diagrams of conventional input circuit examples, and FIGS. 4(a) to 4(c) and 6(a) to 6(c) are circuit diagrams of conventional input circuits. FIG. 3 is a characteristic diagram showing computer simulation results. 101, 102-- Differential circuit FET, 10
3゜104...Differential circuit load, 105...mark...
Differential circuit constant current source FET, 110, 111, 116, 1
17-river-divided resistor, 107, 113... Level shift tie f-, 106, 112... source follower FET, 108, 114-song/constant current source F
ET, 118... Input terminal, 119, 120.
...Pressure terminal, 109°115...Bias circuit output, VDD, V, ...Power supply voltage,
CI...Capacitor. Agent Patent Attorney Susumu UchiharaffTF-(V)

Claims (1)

[Claims] Source follower FET and level shift diode,
A bias generation circuit configured with a constant current source, a pair of loads, and a single-phase drive differential circuit in which an input signal is applied to the gates of the pair of switching FETs, and the first one of the pair of switching FETs. An input circuit characterized in that an output of a switching FET is connected to a gate of a second switching FET via a capacitor.