JPH04177878A - Heterojunction field-effect transistor - Google Patents

Abstract

PURPOSE:To achieve matching to high-speed operation by setting a GaAs layer or AlGaAs layer as a lower insulation layer, a nitrogen oxide germanium film as an upper insulation layer, and then a Ge layer as a channel layer. CONSTITUTION:A non-doped GaAs layer 2 and an N-type Ge layer 3 are allowed to grow on a Cr-doped GaAs substrate 1 in sequence, a nitrogen oxide Ge layer 4 is formed, and then a Ge nitride layer 5 is deposited. Then, the Ge nitride layer 5 and the nitrogen oxide GE layer 4 are selectively etched, thus forming a two-layer resist 14 covering a gate-scheduled region. Further, boron ions are implanted for forming a source/drain 10, a silicon oxide film 6 is deposited, a two-layer resist 14 is eliminated, a nitrogen oxide Ge layer 4a is formed, a contact of source - drain is opened, and then a source electrode 7, a gate electrode 8, and a drain electrode 9 are formed. Therefore, since the channel layer is Ge layer, mobility of electrons and holes is larger, thus achieving a high-speed operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a heterojunction field effect transistor using germanium as a channel.

[Conventional technology]

D, J, Hymes et al.
1ournal of the Electrochem
ical 5ociety) vol, I35. no,
5, 1988゜p, 9Gl, J, J, Rosenbe
IEEE Electron Device Letters by rg et al.
ters) vol, 9. no, I2, 1987. p,
As described in G39, field effect transistors (FETs) using germanium (Ge), which has higher electron and hole mobility than Si, are being studied.

A germanium field effect transistor according to the prior art will be explained with reference to FIG.

First, a Ge oxynitride layer 4 and a G nitride layer are formed on an N-type Ge substrate 13.
Form e layer 5. Next, the Ge nitride layer 5 in the element region is selectively etched using phosphoric acid.

Next, a two-layer resist (not shown) covers the area where the gate is planned.
is formed and boron ions are implanted to form the source-drain 10.

Next, a silicon oxide film 6 is deposited, and then the two-layer resist is removed (lift-off method).

Next, source-drain contacts are opened, and a source electrode 7, a gate electrode 8, and a drain electrode 9 are formed to complete the element section.

In this way, an N-channel heterojunction field effect transistor is obtained in which the Ge layer with P-type conductivity serves as an electron channel.

[Problem to be solved by the invention]

However, Ge FETs use bulk Ge.

Therefore, when the gate length is reduced to submicron,
The electric field concentrates near the drain end of the gate electrode, resulting in hot electrons that cause the device to deteriorate, or a punch-through phenomenon to occur between the source and drain.

In a structure using bulk Ge, the excellent characteristics of Ge, such as high electron and hole mobility, cannot be reflected in device characteristics such as high frequency operation.

Among FETs using silicon (Si), a 5iFET having an SO■ structure is considered to be a promising structure for preventing deterioration of device characteristics when the gate length is shortened.

K, Terrjll et al published the IEDM Technical Digest.
of International Electron
Devices Meeting) 1988. p
, 294, 5iFE with So■ structure
At T, the channel layer becomes thinner. When a voltage is applied between the source and drain, the electric field strength distribution in the channel layer under the gate is different from that of a conventional FET using bulk Si.
It is made more uniform compared to . The hot electron effect caused by electric field concentration at the drain end of the gate, and the punch-through effect caused by extending to the drain depletion layer or near the source, are greatly alleviated, allowing normal operation even in devices with submicron gate lengths. It has excellent characteristics.

However, a 5iFET with an SOI structure fabricated using a silicon oxide (Si02) film as an insulating layer has an S10
゜The quality of the Si film on top is not good. It has not yet been put to practical use because the mobility of holes or electrons in the channel is inferior to that obtained in the bulk.

An object of the present invention is to provide a heterojunction field effect transistor suitable for high-speed operation, in which the mobility of electrons and holes in Ge, which is a channel layer, is equivalent to that in the bulk.

[Means to solve the problem]

In the heterostructure field effect transistor of the present invention, one of an aluminum gallium arsenide layer and a gallium arsenide layer as an insulating layer and a germanium layer as a channel layer are sequentially deposited on a gallium arsenide substrate, and a gate insulating film is deposited on top of the germanium layer. A germanium oxynitride layer and a gate electrode are formed, and a source electrode and a drain electrode are formed on the germanium layer with the gate electrode in between.

[Effect]

Co-authored by A. G. Milnes & D. L. Feucht, co-translated by Sakai, Takahashi and Izumi Mori,
erojunctions and Meta
l Sem1conductor junction
ions) As stated in p. 9, Ge and GaAs have almost the same lattice constant,
The coefficient of thermal expansion is also approximately the same over a wide temperature range centered around room temperature. Therefore, Ge and GaAs form a good heterojunction.

It is known that GaAs and AfGaAs have extremely similar lattice constants and coefficients of thermal expansion, and can form a high-quality heterostructure.

Therefore, AlGaAs and Ge form a high quality heterojunction.

A Ge film grown on GaAs without excess arsenic atoms on the surface using molecular beam epitaxial (MBE) growth exhibits P-type conductivity. Conversely, a Ge film grown on GaAs with an excess of arsenic atoms on the surface exhibits N-type conductivity. This is explained by Yochu et al. in the Workbook of the Fifth MBE International Conference.
International Conference on
Malecular Beam Epitaxy, 19
87. p. 575.

The same thing can be considered when Ge is grown on A1GaAs.

It is known that when operating as a FET, the channel layer through which electrons flow is preferably P type, and the channel layer through which holes flow is preferably N type.

Further, the interface between Ge and germanium oxynitride (G e ON) has a good mid-gap state density of 3×10 10 /Cm 2 ·eV or less.

In this way, an FET having an SOI structure can be realized in which the GaAs layer or AfGaAs layer is used as the lower insulating layer, the germanium oxynitride film is used as the upper insulating layer, and the Ge layer is used as the channel layer through which electrons or holes flow.

〔Example〕

Regarding the first embodiment of the present invention, FIGS. 1(a) to (e)
Explain with reference to.

First, as shown in Figure 1(a), NCr-doped (1
00) Non-doped G is applied to the GaAs substrate 1 by MBE method.
An aAs layer 2 and an N-type Ge layer 3 were grown one by one. N type G
The e-layer was grown at a substrate temperature of 400'C. At this temperature, excessive arsenic atoms are adsorbed on the surface of the GaAs layer.

The Ge oxynitride layer 4 was formed at 600°C and atmospheric pressure, first in an atmosphere of oxygen:nitrogen = 1:3, and then in an ammonia atmosphere.
formation. This step is to passivate the source-drain end, and a high quality N-type Ge layer 3/Ge oxynitride layer 4 interface can be obtained. Further, a Ge nitride layer 5 is deposited by the LPCVD method. Next, the Ge nitride layer 5 and the Ge oxynitride layer 4 in the element region are selectively etched using phosphoric acid.

Next, as shown in FIG. 1(b), a two-layer resist 14 is formed to cover the intended gate area.

Next, boron ions are implanted at an acceleration energy of 10 keV and a dose of I.times.10@15 cm@-2 to form the source-drain 10.

Next, as shown in FIG. 1C, a silicon oxide film 6 with a thickness of 1500 Å is deposited, and then the two-layer resist 14 is removed (lift-off method).

Next, as shown in Fig. 1(d), Ge oxynitride, which will become a gate insulating film with a thickness of 250 mm, is deposited at 600°C and 1 atmospheric pressure, first in an atmosphere of oxygen:nitrogen = 1:3, and then in an ammonia atmosphere. Layer 4 is formed.

Next, as shown in FIG. 1(e), source-drain contacts are opened, and a source electrode 7, a gate electrode 8, and a drain electrode 9 are formed to complete the element section.

In this way, an N-channel heterojunction field effect transistor is obtained in which the Ge layer with P-type conductivity serves as an electron channel.

Next, a second embodiment of the present invention will be described with reference to FIG.

First, a Cr-doped (100) GaAs substrate 1 is coated with MB.
Non-doped AfGaAs layer 2a, P-type Ge
Layers 12 were grown sequentially. The P-type Ge layer 12 has a substrate temperature of 5.
The growth was performed at 00''C. At this temperature, no excessive arsenic atoms were adsorbed on the surface of the GaAs layer 2.

Next, after forming the Ge oxynitride layer 4 and the Ge nitride layer 5,
Accelerate arsenic instead of boron using double-layer resist Energy: 50keV1 Dosage: I x 1015cm
-2 ions are implanted to form source-drain 11.

Thereafter, a silicon oxide film 6 is formed, a Ge oxynitride layer 4a is formed in a region where a gate is to be formed, and a drain electrode 7, a gate electrode 8, and a source electrode 9 are formed to complete the element section.

In this way, a P-channel heterojunction field effect transistor having a hole channel layer made of Ge having N-type conductivity is obtained.

〔Effect of the invention〕

Ge, which has electron and hole mobility three to four times higher than Si, is used as the channel layer, high-resistance non-doped GaAs or non-doped A1GaAs is used as the lower insulating layer, and a Ge oxynitride layer that forms a good interface with Ge is used. S is used as the upper insulating layer to maintain good crystallinity of the channel layer.
OI structure can be easily realized.

High mobility of electrons and holes flowing through the channel layer,
It has the advantage of being able to completely isolate elements by selectively etching the Ge layer.

Even compared to 5iFET with S○■ structure, it has become possible to operate at more than 5 times the speed.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are sectional views showing the first embodiment of the present invention in the order of steps, FIG. 2 is a sectional view showing the second embodiment of the present invention, and FIG. 3 is a sectional view according to the prior art. FIG. 2 is a cross-sectional view showing a heterojunction field effect transistor. 1. Cr-doped GaAs (100) substrate, 2...
Non-doped GaAs layer, 2a...non-doped AlGa
As layer, 3... N-type Ge layer, 4, 4a... Ge oxynitride layer, 5... Nitride Geff1.6... silicon oxide film, 7... Drain electrode, 8... Gate electrode, 9
River source electrode, 10... Boron ion-implanted source-drain layer, 11... Arsenic ion-implanted source-drain layer, 12... P-type Ge layer, 13... N-type Ge substrate, 1
4...Two-layer resist.

Claims (1)

[Claims] 1. On a gallium arsenide substrate, one of an aluminum gallium arsenide layer and a gallium arsenide layer as an insulating layer, and a germanium layer that becomes a channel layer are sequentially deposited, and a gate insulating film is formed thereon. A heterojunction field effect transistor comprising a germanium oxynitride layer and a gate electrode, and a source electrode and a drain electrode formed on the germanium layer with the gate electrode in between. 2. The heterojunction field effect transistor according to claim 1, wherein a germanium layer serving as a channel layer through which electrons flow is formed on one of the aluminum gallium arsenide layer and the gallium arsenide layer, which have no excess arsenic atoms on the surface. 3. The heterojunction field effect transistor according to claim 1, wherein a germanium layer serving as a channel layer through which holes flow is formed on one of the aluminum gallium arsenide layer and the gallium arsenide layer having an excess of arsenic atoms on the surface. .