JPH04177867A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04177867A JPH04177867A JP30747790A JP30747790A JPH04177867A JP H04177867 A JPH04177867 A JP H04177867A JP 30747790 A JP30747790 A JP 30747790A JP 30747790 A JP30747790 A JP 30747790A JP H04177867 A JPH04177867 A JP H04177867A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- lead terminal
- semiconductor device
- terminal
- poor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 229910000679 solder Inorganic materials 0.000 claims abstract description 31
- 238000004806 packaging method and process Methods 0.000 claims description 7
- 238000004381 surface treatment Methods 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 229910052759 nickel Inorganic materials 0.000 abstract description 3
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 238000009736 wetting Methods 0.000 abstract 2
- 239000012212 insulator Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- -1 this Chemical compound 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置、とくに絶縁物封止パラ従来の技
術
半導体チップと、これを内蔵する絶縁物の包装容器と、
この容器に一端を固定され他端を外に出している銅など
のリード端子とを主な構成要件とする半導体装置のパッ
ケージは広く知られている。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device, particularly a conventional semiconductor chip sealed with an insulating material, and an insulating packaging container containing the same.
A semiconductor device package whose main component is a lead terminal made of copper or the like with one end fixed to the container and the other end exposed outside is widely known.
この種の半導体装置は、リード端子全面に錫鉛はんだ層
を形成して、実装時のはんだ濡れ性を良くしている。こ
れら半導体装置は、所定のプリント基板の部品搭載ラン
ド部に、まず印刷によりペースト状のはんだ層を形成し
た後、その上に搭載され、この半導体装置を搭載したプ
リント基板は、赤外線・加熱蒸気等の雰囲気内を通過さ
せられ、ペーストはんだが溶融されプリント基板の端子
と半導体装置のリード端子が電気的に接続される。This type of semiconductor device has a tin-lead solder layer formed over the entire surface of the lead terminal to improve solder wettability during mounting. These semiconductor devices are first printed to form a paste-like solder layer on the component mounting lands of a predetermined printed circuit board, and then mounted on the solder layer. The solder paste is melted and the terminals of the printed circuit board and the lead terminals of the semiconductor device are electrically connected.
発明が解決しようとする課題
しかしなから、上記加熱時に温度プロファイルか適正で
なく、急激に加熱すると、半導体装置のリード端子部が
プリント基板の部品搭載ランド部よりも早く温度が上昇
し、部品搭載ランド上のぺ−ストはんだが溶融して、半
導体装置のリード端子上部に吸い上げられて、接合部に
はんだが残留せず、オープン状態となり接続不良が発生
するため、はんだの融点以下の温度で予備加熱を長時間
行う必要があり、作業効率が低下するという欠点があっ
た。Problem to be Solved by the Invention However, if the temperature profile is not appropriate during the above heating and it is heated rapidly, the temperature of the lead terminal portion of the semiconductor device will rise faster than the component mounting land portion of the printed circuit board, causing the component mounting to occur. The paste solder on the land melts and is sucked up to the top of the lead terminal of the semiconductor device, leaving no solder on the joint and causing an open state and a connection failure. This method has the disadvantage that heating needs to be carried out for a long time, which reduces work efficiency.
本発明の目的は、はんだ接続時のはんだ吸い上りによる
オーブン不良をな（し、予備加熱時間を短くし、もって
作業効率の良いはんだ接合が可能な半導体装置を提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that eliminates oven failure due to solder wicking during solder connection, shortens preheating time, and enables efficient solder bonding.
課題を解決するための手段
この目的を達成するために、本発明の半導体装置は、半
導体チップと、これを内蔵する絶縁物の包装容器と、こ
の包装容器に一端を固定され他端が外方に延びるリード
端子とよりなり、リード端子のうち、接合部を除く部分
の表面が、はんだの濡れ性の悪い表面となる表面処理を
ほどこされた表面となっている。また、本発明半導体装
置は、リード端子のうち、接合部を除く部分に突起を設
けている。Means for Solving the Problems In order to achieve this object, the semiconductor device of the present invention includes a semiconductor chip, an insulating packaging container containing the semiconductor chip, one end fixed to the packaging container and the other end facing outward. The surface of the lead terminal, excluding the joint portion, has been subjected to a surface treatment that makes it a surface with poor solder wettability. Further, in the semiconductor device of the present invention, a protrusion is provided in a portion of the lead terminal excluding the joint portion.
作用
上記の構成により、本発明半導体装置は、プリント基板
に実装されるとき、上記はんだの濡れ性の悪い表面部分
がはんだの運上がりを防ぎ、接続部のはんだが失われる
ことなく、予備加熱時間を短く、作業効率を高くするこ
とができる。Effect With the above configuration, when the semiconductor device of the present invention is mounted on a printed circuit board, the surface portion with poor solder wettability prevents the solder from rising, and the solder at the connection portion is not lost, and the preheating time is shortened. can be shortened and work efficiency can be increased.
実施例 本発明の実施例について、図面を引用しつつ説明する。Example Embodiments of the present invention will be described with reference to the drawings.
本発明半導体装置は、集積回路のチップ１と、これを搭
載するタブ２と、これらを内包するエポキシ樹脂モール
ドの絶縁物容器３と、この絶縁物容器３に一端を固定さ
れ他端が外方に延びているリード端子４とよりなる。リ
ート端子のＵ字状に曲げられた湾曲部は、後工程におい
て、プリント基板にはんだで接合される接合部５である
。接合部５を除く部分６の表面は、アルミニウムまたは
ニッケルのめっきがほどこされ、はんだの濡れ性の悪い
表面７，７′となっている。このようなアルミニウム、
ニッケルのめっきは、樹脂封止されたリードフレームか
ら酸化膜、樹脂のいわゆるｌくりが除去され、接合部５
に錫鉛はんだの薄層が作られた後に作られる。この後、
リードフレーム ・は、金型より所定の形状・寸法に加
工される。The semiconductor device of the present invention includes an integrated circuit chip 1, a tab 2 on which the chip is mounted, an epoxy resin molded insulator container 3 containing these, one end fixed to the insulator container 3 and the other end facing outward. It consists of a lead terminal 4 extending to. The U-shaped curved portion of the lead terminal is a joint portion 5 that is soldered to a printed circuit board in a subsequent process. The surface of the portion 6 other than the joint portion 5 is plated with aluminum or nickel, forming surfaces 7, 7' with poor solder wettability. Aluminum like this,
The nickel plating is done by removing the oxide film and the so-called lug of the resin from the resin-sealed lead frame, and
After a thin layer of tin-lead solder is made. After this,
A lead frame is processed into a predetermined shape and size using a mold.
上記のような半導体は、プリント基板８の上の部品搭載
ランド９にのせられ、赤外線炉などで加熱接続される際
、はんだ１０が接合部５の近傍にとどまり、はんだの濡
れ性の悪い表面７に進むことがない。When the above-mentioned semiconductor is placed on the component mounting land 9 on the printed circuit board 8 and heated and connected in an infrared furnace, the solder 10 remains near the joint 5 and the surface 7 has poor solder wettability. There is no way to proceed.
上記実施例におけるアルミニウムなどによるめっきにか
えて、耐熱性の樹脂で被覆してもよい。Instead of plating with aluminum or the like in the above embodiments, it may be coated with a heat-resistant resin.
また、樹脂の被覆は、薄い層でなく、突起１１となって
いた方がよい。Further, it is better for the resin coating to be in the form of protrusions 11 rather than a thin layer.
発明の効果
以上の説明のように、本発明によれば、半導体装置のリ
ード端子上部に、はんだと濡れ性の悪い処理を施したた
め、赤外線炉などではんだを融解し接続する時に、温度
プロファイルが不適切となった場合でもはんだの吸上り
現象（ウィッキング）かなくなり、修正の工程か不要と
なり、作業効率か大幅に向上する。Effects of the Invention As explained above, according to the present invention, the upper part of the lead terminal of a semiconductor device is treated to have poor wettability with solder, so that when the solder is melted and connected in an infrared oven or the like, the temperature profile is changed. Even if the solder becomes inappropriate, the phenomenon of solder wicking is eliminated, eliminating the need for correction processes and greatly improving work efficiency.
第１図は本発明実施例の半導体装置および搭載するプリ
ント基板の一部の断面図、第２図は他の実施例の要部断
面図である。
１・・・・・・チップ、２・・・・・・タブ、３・・・
・・・絶縁物容器、４・・・・・・リード端子、５・・
・・・・接合部、６・・・・・・接合部を除く部分、７
，７′・・・・・・はんだ濡れ性の悪い表面、８・・・
・・・プリント基板、９・・・・・・部品搭載ランド、
１０・・・・・・はんだ。
代理人の氏名 弁理士小鍜治明 ほか２名第１図
５−１合部 ｆＯ−１ａんだ
第２図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention and a part of a printed circuit board on which it is mounted, and FIG. 2 is a sectional view of a main part of another embodiment. 1...Tip, 2...Tab, 3...
...Insulator container, 4...Lead terminal, 5...
...Joint part, 6...Part excluding joint part, 7
, 7'...Surface with poor solder wettability, 8...
...Printed circuit board, 9...Component mounting land,
10...Solder. Name of agent: Patent attorney Haruaki Koba and two others Fig. 1 5-1 joint Fig. 2 fO-1a
Claims (2)
器と、この包装容器に一端を固定され他端が外方に延び
るリード端子とよりなる半導体装置において、リード端
子のうち、接合部を除く部分の表面が、はんだの濡れ性
の悪い表面となる表面処理をほどこされた表面である半
導体装置。(1) In a semiconductor device consisting of a semiconductor chip, an insulating packaging container containing the semiconductor chip, and lead terminals having one end fixed to the packaging container and the other end extending outward, the joint portion of the lead terminal is A semiconductor device in which the surface of the removed portion has been subjected to a surface treatment that makes it a surface with poor solder wettability.
器と、この包装容器に一端を固定され他端が外方に延び
るリード端子とよりなる半導体装置において、リード端
子のうち、接合部を除く部分に突起を設けた半導体装置
。(2) In a semiconductor device consisting of a semiconductor chip, an insulating packaging container containing the semiconductor chip, and lead terminals having one end fixed to the packaging container and the other end extending outward, the joint portion of the lead terminal is A semiconductor device with protrusions on the parts to be removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30747790A JPH04177867A (en) | 1990-11-13 | 1990-11-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30747790A JPH04177867A (en) | 1990-11-13 | 1990-11-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04177867A true JPH04177867A (en) | 1992-06-25 |
Family
ID=17969553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30747790A Pending JPH04177867A (en) | 1990-11-13 | 1990-11-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04177867A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59219946A (en) * | 1983-05-30 | 1984-12-11 | Hitachi Ltd | Solder overflow preventing device for flat pack part |
| JPS6230357B2 (en) * | 1982-04-13 | 1987-07-01 | Niigata Engineering Co Ltd | |
| JPH0113152B2 (en) * | 1987-01-26 | 1989-03-03 | Tetsudo Sogo Gijutsu Kenkyusho | |
| JPH02270359A (en) * | 1989-04-11 | 1990-11-05 | Nec Corp | Plcc package |
-
1990
- 1990-11-13 JP JP30747790A patent/JPH04177867A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230357B2 (en) * | 1982-04-13 | 1987-07-01 | Niigata Engineering Co Ltd | |
| JPS59219946A (en) * | 1983-05-30 | 1984-12-11 | Hitachi Ltd | Solder overflow preventing device for flat pack part |
| JPH0113152B2 (en) * | 1987-01-26 | 1989-03-03 | Tetsudo Sogo Gijutsu Kenkyusho | |
| JPH02270359A (en) * | 1989-04-11 | 1990-11-05 | Nec Corp | Plcc package |
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