JPH04177737A - Field effect transistor - Google Patents

Abstract

PURPOSE:To eliminate the occurrence of lattice unmatching so as to improve the enclosing efficiency and mobility of carriers by constituting a channel layer of GaInAs and gradually changing the In compositions of the layers on and below the channel layer by performing planar doping. CONSTITUTION:A cap layer 7 composed of Gax-1InxAs is formed on a channel layer. The layer 7 has an In composition ratio X of 0.15 at the interface with the channel layer and the interface is constituted so that the lattice at the interface can match the lattice of the second Ga0.85In0.15As layer 6 and the lattice matching can be reduced as going farther from the layer 6, with the lattice matching being '0' at the uppermost surface. Accordingly, the composition ratios of the layers 7 and 6 are almost equal to each other and lattice matching is realized at the interface. Therefore, the carrier enclosing efficiency and doping efficiency can be improved after carriers are moved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor, and particularly relates to a field effect transistor made of a GaAs-based compound semiconductor.

[Conventional technology]

GaAs field-effect transistors (hereinafter simply referred to as FETs) have high carrier mobility and saturation speed, and therefore various research and development efforts have been made to put them into practical use as high-frequency devices.

In order to make such an element even higher frequency,
It is necessary to increase the transfer conductance (gm) as well as improve the gate-source breakdown voltage and current drive ability by miniaturizing the device and reducing the thickness of the channel layer, and various studies are being conducted on these issues. It has been carried out and announced.

For example, JP-A-61. -166081 Publication, JP-A-6
1-276270 and the like discloses an FET in which a planar dope layer in which ionized donors are present is formed using a planar doping technique, and this serves as a channel. Furthermore, Japanese Patent Application Laid-Open No. 64-82677 discloses a structure in which a channel layer is formed by providing two planar doped layers within the mean free path of electrons.

In addition, we focused on the fact that GaInAs has higher electron mobility and saturation speed than GaAs.
Some of these are disclosed in Japanese Patent Application Laid-open No. 371 and Japanese Patent Application Laid-Open No. 64-57677. Furthermore, a method focusing on the high doping efficiency of Sl is disclosed in JP-A-63-90861. Furthermore, it is known that if GaInAs with a small band gap is provided on GaAs, leakage of carriers into the GaAs buffer layer can be suppressed.

[Problem to be solved by the invention]

However, none of the above conventional techniques has been able to realize a field effect transistor with sufficiently satisfactory characteristics. That is, in the above-mentioned conventional technology using planar doping technology, carriers cannot be sufficiently confined because a planar doped layer is provided between semiconductor layers of GaAs having a large band width. Furthermore, in the above-mentioned conventional technology that focuses on the characteristics of GaInAs,
It has various drawbacks, such as a large lattice misalignment at the interface between GaAs and GaInAs, and insufficient characteristics because a Schottky electrode is provided on the GaInAs. For this reason, field-effect transistors are superior in terms of mobility, carrier confinement efficiency, and doping efficiency, and therefore have high current drive capability, high transfer conductance, and high gate-source breakdown voltage. It had not been realized.

Therefore, the object of the present invention is to provide a field effect transistor with high mobility, high carrier confinement efficiency, and high doping efficiency.

[Means to solve the problem]

In order to achieve the above object, the field effect l.
In transistors, GalnAs has a substantially constant In composition ratio.
A channel layer consisting of a planar doped layer doped with impurities in a two-dimensional thin plane is formed inside the channel layer, and a channel layer consisting of GaInAs and provided in contact with the bottom of the channel layer with a composition ratio of In. It is characterized by comprising a buffer layer and a cap layer that are substantially the same as the channel layer at a position in contact with the channel layer, decrease as the distance from the channel layer increases, and become substantially 0 on the farthest surface.

[Effect]

In the field effect transistor of the present invention, a GaInAs channel layer is formed on the GaAs layer to improve carrier confinement efficiency. Furthermore, planar doping of impurities into the channel layer improves doping efficiency and carrier mobility. Furthermore, by gradually changing the composition ratio so that it becomes almost the same at the interface with the GaAs layer, lattice matching is made possible, and a Schottky electrode is formed on the GaAs, resulting in a good Schottky junction. It becomes possible.

〔Example〕

Embodiments of the present invention will be described below with reference to FIG.

As shown in FIG. 1(a), a compound semiconductor field effect transistor, which is an embodiment of the present invention, is made of semi-insulating Ga
It includes a non-doped GaAs layer 2 formed on an As substrate 1 to a thickness of 0.5 μm, and a GaInAs buffer layer 3 formed thereon to a thickness of 100 angstroms. This buffer layer 3 has an In composition of X=0 at the interface with the non-doped GaAs layer 2, and this composition ratio
becomes gradually larger as it moves away from the non-doped GaAs layer 2, and is configured such that X=0.15 at the top surface. Therefore, at the interface between the non-doped GaAs layer 2 and the buffer layer 3, their composition ratios are substantially the same and lattice matching is achieved.

Furthermore, a channel layer is provided above this buffer layer→. This channel layer is made of first Ga I n
As layer 4 and planar layer 0.85 0.1 on top of it
5 A planar doped layer 5 formed by doping, and a second Ga InO,850,1 provided on the second layer.
, 5 and an As layer 6. These GaInAs
The composition ratio of In in layer 4.6 is approximately constant.

Therefore, this first. G a I n A
At the interface between the s layer 40.85 0.15 and the buffer layer 3, the composition ratios of these layers are substantially the same, and lattice matching is achieved. The planar doped layer 5 is formed by thinly doping Ga InAs with an impurity such as Sl or Se, which becomes a [ ] type toner, on a two-dimensional plane.

Further, on this channel layer, a 1-X layer made of GaInAs with a thickness of 100 angstroms is formed.
An X gap layer 7 is provided. This cap layer 7 is
Contrary to the buffer layer 3, the In composition ratio X is 0.15 at the interface with the channel layer, and the second (
:, B In As layer 6 and case 0.85 0.
1.5, and is configured so that it gradually decreases away from this layer and reaches 0 at the top surface. For this reason, the second Ga I n A
In the 0.85 0.15 interface between the s layer 6 and the cap layer 7, the composition ratios of these layers are approximately the same, and lattice matching is achieved. In order to make it easier to understand the situation regarding the above-mentioned In composition, FIG. 1(b) shows a profile of the In silk composition in the depth direction.

Historically, the thickness of this cap layer 7 is 300 mm]
A ROHM non-doped GaAs layer 8 is provided. For this reason, the non-doped layer 8 and the cap layer 7 are configured to have substantially the same composition ratio at the interface, and the lattice misalignment is alleviated.

On this non-doped GaAs layer 8, a non-yotto key metal is formed to become a gate electrode 9, and an ohmic metal is further formed to become a source/drain electrode.

Here, the difference between the field effect transistor of the above embodiment and the conventional field effect transistor will be briefly explained using FIG. 2.

FIG. 2(a) shows a bandgap diagram near the channel of the field effect transistor of the above embodiment, and the second
Figure (b) shows the band gap diagram near the channel of a field effect transistor formed by planar doping impurities into the GaAs channel, and Figure 2 (C)
shows a bandgap diagram near the channel of a field effect transistor formed by uniformly doping a GaInAs channel layer with n-type impurities.

Here, when comparing Figure 2(a) and Figure 2(b),
"In Example 1, Ga In with a small band gap
Because it uses an As channel layer, carrier confinement efficiency is high, and GaAs can be used even in regions with small drain current.
It can be seen that it is difficult to seep into the buffer layer. Comparing Figure 2(a) and Figure 2(C), we can see that by performing planar doping, electrons exist in quantized energy levels as shown in Figure 2(,a). However, since it is spatially separated from the ionized donor, the influence of Crohn scattering is reduced, and the mobility in a low electric field does not decrease by 1 degree.

−〇 − = 8 − Furthermore, in the above embodiment, the In composition ratio of the buffer layer 3 and the cap layer 7 is gradually changed, and the composition ratio of the non-doped GaAs layer in contact with the upper and lower surfaces thereof and the interface thereof is approximately the same. Since they are configured to match, lattice misalignment is alleviated and carrier mobility is improved. Moreover, this makes it possible to use a GaAs layer as the junction surface of the Schottky metal that will become the gate electrode, and a good Schottky junction can be realized.

Next, a method for manufacturing the field effect transistor of the above embodiment will be briefly explained with reference to FIG.

The field effect transistor of the above embodiment is made of semi-insulating Ga
OM VPE method, MBE method, CBE method on As substrate
It is created by growing each semiconductor layer by a method or the like.

For example, the non-doped GaAs layer 2 is formed by forming a semi-insulating GaAs layer 2 while supplying a predetermined raw material by any of the above methods.
substrate] to a thickness of 0.5 μm (see Figure 3 (a))
. Next, by controlling the raw material to be supplied, the composition of In is grown on the non-doped GaAs layer 2 so that it gradually increases from X = 0, and reaches X = 0.15 at the top surface.
a1. A buffer layer of xInXAs is grown to a thickness of 100 angstroms (see FIG. 3(b)).

Next, by controlling the raw materials to be supplied, a non-doped Ga In As layer 4 having a substantially uniform composition is formed at 85°C.
0.15 Grow to a thickness of 100 angstroms.

Next, the supply of the raw materials of the group Ⅰ elements, that is, Ga and As, is stopped, and while the raw materials of the group Ⅰ element As are supplied, an impurity element that can become a donor of the [] type, such as Sl or Se, is supplied. Planar doping is performed in which doping is performed in the form of a sheet (see FIG. 3(c)). This planar doping method is well known from the above-mentioned literature, so detailed explanation will be omitted.

Next, the supply of the n-type impurity raw material f was stopped, and the supply of Group III elements Ga and As was started again.
I n As layer 6 100 on guest o, 85
Grow 0.15 0-m. In this way, a channel layer sandwiching the planar doped layer 5 is formed.

Next, a cap layer 7 of Ga In As is formed.
-X X lengthen. For this growth, the supply of In raw material is controlled in the same way as in the case of the buffer layer, and the cap layer 7 is grown so that the In composition gradually increases in the growth direction, changing from X = 0.15 to X-〇. The film is grown to a thickness of 100 angstroms (see FIG. 3(d)).

Next, a non-doped GaAs layer 8 of 300 angstroms is grown on this cap layer 7 (see FIG. 3(e)).
, a shottsuki metal is vapor-deposited thereon to form the gate electrode 9.
The source electrode and the drain electrode 10 are formed by depositing and alloying an ohmic metal (
(See Figure 3(f)).

〔Effect of the invention〕

As explained above, according to the present invention, the channel layer is
It is composed of a I nAs, and one layer is planar-doped, and the In composition in the F layer is gradually changed to eliminate lattice misalignment, so the carrier confinement efficiency is high and the movement is It is possible to realize a field effect transistor with high performance.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the structure of a field effect transistor which is an embodiment of the present invention, and FIG. 2 is a diagram showing a band gap diagram near the channel of the field effect transistor of the present invention and a conventional field effect transistor. FIG. 3 is a diagram showing the cross-sectional structure of the field effect transistor shown in FIG. 1 in each manufacturing process. ]...GaAs substrate, 2...non-doped GaAs layer, 3...derated GaInAs buffer layer, 4...
...GaInAs layer, 5...planar doped layer,
6... GalnAs layer, 7... Gelated Ga I
nAs cap layer, 8... non-doped GaAs layer,
9...Gate electrode, 10...Source, train electrode. Representative Patent Attorney Yoshiki Hasejo
Fumi Terasaki Roichi 12 - Manufacturing process (portion/j) Figure 3 (1) Manufacturing process width P) Figure 3 (2) Procedural amendment 1990 Patent application No. 305747 2 Name of invention Field effect transistor 3 Relationship with the case of the person making the amendment Patent applicant Sumitomo Electric Industries, Ltd. 4 Agent (Postal code 10I) 4th floor U-Y building, 2-7 Higashikanda, Chiyoda-ku, Tokyo 'Range' column. = 1-2, Claims A channel layer made of GaInAs with a substantially constant In composition ratio and in which a planar doped layer doped with impurities in a two-dimensional thin planar shape is formed; The composition ratio of In is approximately the same as that of the channel layer at the position in contact with the channel layer, and decreases as the distance from the channel layer increases, and the composition ratio of In is made of nAs and is provided in contact with the upper and lower sides of the channel layer. What's more, the electric field effect!・Rangista.

Claims (1)

[Claims] Consisting of GaInAs with a substantially constant In composition ratio,
a channel layer in which a planar doped layer doped with impurities in a two-dimensional thin planar shape is formed; A field effect transistor comprising a buffer layer and a cap layer, which are substantially the same in position as the channel layer, decrease as the distance from the channel layer increases, and are substantially zero on the most distant surface thereof.