JPH04176112A - Manufacture of chip type electric double layer capacitor - Google Patents
Manufacture of chip type electric double layer capacitorInfo
- Publication number
- JPH04176112A JPH04176112A JP2303440A JP30344090A JPH04176112A JP H04176112 A JPH04176112 A JP H04176112A JP 2303440 A JP2303440 A JP 2303440A JP 30344090 A JP30344090 A JP 30344090A JP H04176112 A JPH04176112 A JP H04176112A
- Authority
- JP
- Japan
- Prior art keywords
- electric double
- capacitor element
- layer capacitor
- double layer
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000465 moulding Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 238000000605 extraction Methods 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000005452 bending Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 206010041662 Splinter Diseases 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229920006351 engineering plastic Polymers 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- -1 polyphenylene sulfite Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はチップ型電気二重層コンデンサの製造方法に関
し、特にケース成形方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a chip type electric double layer capacitor, and particularly to a method for molding a case.
従来のチップ型電気二重層コンデンサは、第4図(a)
〜(C)に示すように複数個直列に積層された電気二重
層コンデンサ素子積層体の両端部に外部導出用リード端
子板2a、2bを設置し、このリード端子板2a、2b
を介し、上下方向から電気二重層コンデンサ素子積層体
を成形金型4a、4.b内に設けられた凸部4f、4g
で一定寸法に圧縮されるよう成形金型4a、4bが閉じ
られる。次に成形金型4.a、4b内に樹脂がゲート部
4cから注入され外装ケース3が成形される。A conventional chip type electric double layer capacitor is shown in Fig. 4(a).
As shown in ~(C), lead terminal plates 2a, 2b for external extraction are installed at both ends of a plurality of electric double layer capacitor element laminates stacked in series, and these lead terminal plates 2a, 2b
The electric double layer capacitor element laminate is molded from above and below through molds 4a, 4. Convex portions 4f and 4g provided in b
The molds 4a and 4b are closed so as to be compressed to a constant size. Next, molding mold 4. Resin is injected into a and 4b from the gate part 4c, and the exterior case 3 is molded.
その後、外装ケース3外部に導出されたリード端子2a
、2bを所定の形状に折り曲げ組立てられていた。After that, the lead terminal 2a led out to the outside of the exterior case 3.
, 2b were assembled by bending them into a predetermined shape.
この従来のチップ型電気二重層コンデンサの製造方法で
は、電気二重層コンデンサ素子のバラツキに無関係に一
定寸法に圧縮されてしまうため、圧縮率のバラツキによ
り製品特性の等価直列抵抗値が規格から外れたり、甚し
い場合過圧縮による破裂、圧縮率不足による電気二重層
コンデンサ素子間の接触不良が発生する問題点があった
。この為、常に一定寸法内に収まる高い寸法精度が要求
され、この要求を満たす選別作業工数と歩留り低下か発
生ずるのでコストアップの問題点もあった。In this conventional manufacturing method for chip-type electric double layer capacitors, the electric double layer capacitor elements are compressed to a fixed size regardless of variations, so the equivalent series resistance value of the product characteristics may deviate from the standard due to variations in the compression ratio. In severe cases, there were problems such as rupture due to overcompression and poor contact between electric double layer capacitor elements due to insufficient compression ratio. For this reason, high dimensional accuracy that always falls within a certain size is required, and the number of man-hours required for sorting to meet this requirement and the yield decrease, resulting in an increase in costs.
本発明の目的は、電気二重層コンデンサ素子の厚さのバ
ラツキに対し、はぼ無関係に一定圧力て加圧することが
でき、そのため均一な品質特性が得られるとともに、厚
さ選別を不要とし、コストを低下させることができるチ
ップ型電気二重層コンデンサ素子を提供することにある
。The object of the present invention is to be able to pressurize electric double layer capacitor elements at a constant pressure regardless of variations in thickness, thereby obtaining uniform quality characteristics, eliminating the need for thickness selection, and reducing costs. An object of the present invention is to provide a chip type electric double layer capacitor element that can reduce the
本発明のチップ型電気二重層コンデンサの製造方法は、
直列に複数枚積層された電気二重層コンテンザ素子積層
体の両端部に外部導出用リード端子板を設置し、リード
端子板の一部をバネを介し、電気二重層コンデンサ素子
積層体を成形金型内の一部に埋め込まれたハネにより可
動する凸部で圧縮し、成形金型内に樹脂を注型し、外装
ケースを形成した後、外装ケース側面から導出されたそ
れぞれのリード端子を同一方向に折り曲げ整形すること
を特徴として構成される。The method for manufacturing a chip type electric double layer capacitor of the present invention includes:
A lead terminal board for external extraction is installed at both ends of the electric double layer capacitor element laminate, which is a plurality of electric double layer capacitor elements laminated in series, and a part of the lead terminal plate is inserted through a spring, and the electric double layer capacitor element laminate is molded into a mold. After compressing with a movable convex part using a spring embedded in a part of the inner part and pouring resin into the mold to form an outer case, each lead terminal led out from the side of the outer case is connected in the same direction. The feature is that it can be bent and shaped.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のチップ型電気二重層コンデ
ンサの断面図である。第2図(a)〜(c)は本発明の
特徴を示すケース成形工程を表わす側面(透視)図であ
る。第3図(a)〜(c)は本発明の一実施例及び従来
例のチップ型電気二重層コンデンサの上面図(a)、側
面図(b)および底面図(c)である。第4図(a)〜
(c)は従来例のチップ型電気二重層コンデンサのケー
ス成形工程を表わす側面(透視)図である。第2図(a
)〜(c)に於いて、直列に積層された電気二重層コン
デンサ素子積層体の両端部には、外部導出用のリード端
子板2a、2bが各々接触している。このリード端子板
2a、2bには、図示した様に電気二重層コンデンサ素
子1の側面に一層毎露出している電極(図示省略)から
離間し、直列に積層された電気二重層コンデンサ素子1
の略中央部から外周方向へ折り曲げ加工が加えられてい
る。このリード端子板2a、2bが接触した状態でケー
ス3を成形する為、成形金型4a、4.b内に収納され
、樹脂がゲート部4cから注入される。成形用樹脂とし
てはチップ部品として要求される耐熱性を満足する為、
PPS (ポリフェニレンザルファイト)樹脂等の所謂
エンプラが用いられる。成形金型4a、4.b内では、
ソー1〜端子板2a、2bを介して電気二重層コンテン
ザ素子1が成形金型4a、4b内に設けられた凸部4.
d、4e(本発明では8個)にて圧縮されている。電気
二重層コンデンサの場合、電気二重層コンテンサ素子1
の圧縮状態により、等個直列抵抗値が変化するだけでは
なく、過圧縮状態になると、電気二重層コンテンサ素子
1が破壊し、圧縮不足では積層された電気二重層素子1
間の接触抵抗値が増加する為、この圧縮状態は特に管理
すl\き項目となっていた。本発明の場合、電気二重層
コンデンザ素子1を加圧する凸部4d、4eが金属コイ
ルバネを用いたスプリング5a、5bで可動する為、た
とえ電気二重層コンデンサ素子1の厚さにバラツキがあ
ってもほぼ一定圧力で加圧される為、均一で安定した等
個直列抵抗値が得られるだけでなく、従来必要とされて
いた電気二重層コンデンサ素子1の厚さ選別が無くなる
為、コストダウンの効果もある。電気二重層コンデンサ
素子1の素子直径が1.1. m m 、積層枚数が6
枚。FIG. 1 is a sectional view of a chip type electric double layer capacitor according to an embodiment of the present invention. FIGS. 2(a) to 2(c) are side (perspective) views illustrating the case forming process, which characterizes the present invention. FIGS. 3(a) to 3(c) are a top view (a), a side view (b), and a bottom view (c) of a chip type electric double layer capacitor according to an embodiment of the present invention and a conventional example. Figure 4(a)~
(c) is a side (perspective) view showing a case molding process of a conventional chip type electric double layer capacitor. Figure 2 (a
) to (c), lead terminal plates 2a and 2b for leading out to the outside are in contact with both ends of the electric double layer capacitor element laminate stacked in series. As shown in the figure, the lead terminal plates 2a and 2b have electric double layer capacitor elements 1 stacked in series, spaced apart from electrodes (not shown) exposed layer by layer on the side surfaces of the electric double layer capacitor elements 1.
A bending process is added from approximately the center to the outer circumferential direction. In order to mold the case 3 with the lead terminal plates 2a, 2b in contact with each other, the molding molds 4a, 4. b, and resin is injected from the gate part 4c. As a molding resin, it satisfies the heat resistance required for chip parts.
So-called engineering plastics such as PPS (polyphenylene sulfite) resin are used. Molding mold 4a, 4. Within b,
The electric double layer condenser element 1 is installed in the molding molds 4a, 4b via the saw 1 and the terminal plates 2a, 2b in the convex portion 4.
d, 4e (eight in the present invention). In the case of an electric double layer capacitor, electric double layer capacitor element 1
Not only does the equal series resistance value change depending on the compressed state of
Since the contact resistance value between the parts increases, this compressed state has become a particularly important item to manage. In the case of the present invention, since the protrusions 4d and 4e that pressurize the electric double layer capacitor element 1 are movable by the springs 5a and 5b using metal coil springs, even if there are variations in the thickness of the electric double layer capacitor element 1, Since it is pressurized at a nearly constant pressure, not only can uniform and stable equal series resistance values be obtained, but the cost reduction effect is achieved because the thickness selection of the electric double layer capacitor element 1, which was previously required, is no longer required. There is also. The element diameter of the electric double layer capacitor element 1 is 1.1. m m, number of laminated sheets is 6
Sheet.
−枚当たりの厚さが1.4mmの場合スプリングの加圧
力は約50〜100kgが望ましい。ケース3が成形さ
れた後、ケース3から外部へ導出されたリード端子板2
a、2bは所定の電極形状に折り曲げられ、第1図に示
す様なチップ型電気二重層コンデンサが完成される。- When the thickness per sheet is 1.4 mm, the pressing force of the spring is preferably about 50 to 100 kg. After the case 3 is molded, the lead terminal plate 2 is led out from the case 3
A and 2b are bent into a predetermined electrode shape to complete a chip type electric double layer capacitor as shown in FIG.
ここで使用されるスプリング5a、5bは、本実施例で
は第2図に示したようにコイルハネを用いたが、ゴム系
のバネなどを使用しても良いことは当然である。The springs 5a and 5b used here are coil springs as shown in FIG. 2 in this embodiment, but it goes without saying that rubber springs or the like may also be used.
6一
以上説明したように本発明は、電気二重層コンテンザ素
子の厚さバラツキに対し、はぼ無関係に一定圧力で加圧
することができる為、安定で均一な品質特性が得られる
とともに、電気二重層コンテンサ素子の厚さ選別か不要
となるので、コスト安の利点も有している。6. As explained above, the present invention can apply pressure at a constant pressure irrespective of the thickness variation of the electric double layer condenser element, so stable and uniform quality characteristics can be obtained and the electric double layer condenser element can be pressurized with a constant pressure. Since there is no need to select the thickness of the multilayer condenser element, it also has the advantage of lower costs.
第1図は本発明の一実施例のチップ型電気二重層コンデ
ンサの断面図、第2図(a)〜(c)は本発明の一実施
例のチップ型電気二重層コンデンサの製造方法を示した
側面図、第3図(a)〜(C)は本発明の一実施例およ
び従来例のチップ型電気二重層コンデンサの上面図、側
面図および底面図、第4図(a)〜(c)は従来のチッ
プ型電気二重層コンデンサの製造方法を示した側面図で
ある。
1・電気二重層コンデンサ素子、2a、2b・・・リー
ド端子板、3・・外装ケース、4a、4b・・・成形金
型、4. c−ゲート部、4.d、 4.e、 4.f
、 4g・・・凸部、5a、5b・・・スプリンタ。FIG. 1 is a cross-sectional view of a chip-type electric double layer capacitor according to an embodiment of the present invention, and FIGS. 2(a) to (c) show a method for manufacturing a chip-type electric double-layer capacitor according to an embodiment of the present invention. FIGS. 3(a) to 3(c) are top views, side views, and bottom views of chip-type electric double layer capacitors according to an embodiment of the present invention and a conventional example, and FIGS. 4(a) to (c). ) is a side view showing a conventional method for manufacturing a chip type electric double layer capacitor. 1. Electric double layer capacitor element, 2a, 2b... Lead terminal board, 3. Exterior case, 4a, 4b... Molding mold, 4. c-gate section, 4. d, 4. e, 4. f
, 4g... Convex portion, 5a, 5b... Splinter.
Claims (1)
の両端部に外部導出用リード端子板を設置し、前記リー
ド端子板を介し、前記電気二重層コンデンサ素子積層体
を成形金型内の一部に埋め込まれたバネにより可動する
凸部で圧縮し、前記成形金型内に樹脂を注型し、外装ケ
ースを形成した後、前記外装ケース側面から導出された
それぞれのリード端子を同一方向に折り曲げ整形するこ
とを特徴とするチップ型電気二重層コンデンサの製造方
法。A lead terminal plate for external extraction is installed at both ends of a plurality of electric double layer capacitor element laminates stacked in series, and the electric double layer capacitor element laminate is inserted into a part of the molding die via the lead terminal plate. The resin is compressed by a movable convex part by a spring embedded in the mold, and the resin is poured into the mold to form an outer case, and then each lead terminal led out from the side surface of the outer case is bent in the same direction. A method for manufacturing a chip type electric double layer capacitor, which is characterized by shaping.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2303440A JPH04176112A (en) | 1990-11-08 | 1990-11-08 | Manufacture of chip type electric double layer capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2303440A JPH04176112A (en) | 1990-11-08 | 1990-11-08 | Manufacture of chip type electric double layer capacitor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04176112A true JPH04176112A (en) | 1992-06-23 |
Family
ID=17921029
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2303440A Pending JPH04176112A (en) | 1990-11-08 | 1990-11-08 | Manufacture of chip type electric double layer capacitor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04176112A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0528024U (en) * | 1991-09-20 | 1993-04-09 | エルナー株式会社 | Electric double layer capacitor |
-
1990
- 1990-11-08 JP JP2303440A patent/JPH04176112A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0528024U (en) * | 1991-09-20 | 1993-04-09 | エルナー株式会社 | Electric double layer capacitor |
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