JPH04175955A - Input/output processor - Google Patents

Input/output processor

Info

Publication number
JPH04175955A
JPH04175955A JP30425690A JP30425690A JPH04175955A JP H04175955 A JPH04175955 A JP H04175955A JP 30425690 A JP30425690 A JP 30425690A JP 30425690 A JP30425690 A JP 30425690A JP H04175955 A JPH04175955 A JP H04175955A
Authority
JP
Japan
Prior art keywords
channel
microprogram
transfer
data
transferring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30425690A
Other languages
Japanese (ja)
Inventor
Yoko Fujimoto
洋子 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP30425690A priority Critical patent/JPH04175955A/en
Publication of JPH04175955A publication Critical patent/JPH04175955A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To facilitate control by transferring a 1st channel microprogram from a storage device initially, transferring a microprogram in its channel into a next channel next time, and reporting the end of storage to a channel controller over an (n)th channel. CONSTITUTION:When a microprogram transfer instruction is sent out, an instruction control part 9 instructs a microprogram storage part 4 to transfer the microprogram to a data storage part 7-1, and when the transfer ends, a data control part 8-1 instructs the data storage part 7-1 to transfer the microprogram to a data storage part 7-2 in a 2nd channel 6-2. Similarly, the microprogram is transferred one after another up to channels n-1 and 6-n-1 and when the microprogram is transferred to a data storage part 7-n in the (n)th channel 6-n, a data control part 8-n informs the instruction control part 9 of the end of channel-(n) microprogram transfer. Consequently, the control is facilitated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は入出力処理装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an input/output processing device.

〔従来の技術〕[Conventional technology]

従来、この種の入出力処理装置は、マイクロプログラム
転送時、各チャネル毎に、個別のデータバスを用いて、
記憶装置よりチャネル制御装置を介し、マイクロプログ
ラムを各チャネルへ転送していた。Conventionally, this type of input/output processing device uses a separate data bus for each channel when transferring a microprogram.
Microprograms were transferred from the storage device to each channel via the channel control device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の入出力処理装置はマイクロプログラム転
送時、各チャネル毎に個別のデータバスを用いて記憶装
置よりチャネル制御装置を介しマイクロプログラムを各
チャネルへ転送していた為、制御が複雑であるという欠
点がある。When transferring a microprogram, the conventional input/output processing device described above uses a separate data bus for each channel to transfer the microprogram from the storage device to each channel via the channel control device, making control complicated. There is a drawback.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の入出力処理装置は、チャネル制御装置にて、記
憶装置に格納されているマイクロプログラムを第１のチ
ャネルに転送する手段と、第１のチャネルにてマイクロ
プログラム格納終了時に自チャネル内のマイクロプログ
ラムを読み出し第２のチャネルへ転送する手段と以下同
様にｎ−１チャネルまで次のチャネルにマイクロプログ
ラムを転送する手段と、第ｎチャネルにマイクロプログ
ラム格納時にチャネル制御装置にマイクロプログラム格
納終了を報告する手段とを含んで構成される。The input/output processing device of the present invention includes means for transferring a microprogram stored in a storage device to a first channel in a channel control device, and a means for transferring a microprogram stored in a storage device to a first channel, and a means for transferring a microprogram stored in a storage device to a first channel, and means for reading the microprogram and transferring it to the second channel; means for similarly transferring the microprogram to the next channel up to channel n-1; and means for instructing the channel control device to finish storing the microprogram when storing the microprogram in the n-th channel. and a means for reporting.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

マイクロプログラム転送命令が信号線２１を介して命令
制御部９に出されると、命令制御部９は信号線２２を介
して、マイクロプログラム格納部４ヘマイクロプログラ
ムをデータバス４１を介してデータ格納部７−１へ転送
するよう指示し、同時に命令制御部９は信号線２３を介
しデータ制御部８−、ヘマイクロプログラム転送を指示
することによりデータ転送制御部８−１は信号線２４を
介し、データ格納部７−１へマイクロプログラム受付は
可の指示を送る。When a microprogram transfer command is issued to the command control unit 9 via the signal line 21, the command control unit 9 transfers the microprogram to the microprogram storage unit 4 via the signal line 22, and transfers the microprogram to the data storage unit via the data bus 41. At the same time, the instruction control unit 9 instructs the data control unit 8- to transfer the microprogram to the data control unit 8-1 via the signal line 23, so that the data transfer control unit 8-1 transfers the microprogram to the data control unit 8-1 via the signal line 24. An instruction is sent to the data storage unit 7-1 to allow microprogram reception.

これによりマイクロプログラム格納部４内のマイクロプ
ログラムは、データバス４１を介してデータ格納部７−
１へ転送される。As a result, the microprograms in the microprogram storage section 4 are transferred to the data storage section 7 through the data bus 41.
Transferred to 1.

データ格納部７−１へのマイクロプログラム転送が終了
すると、データ格納部７−、は信号線２４を介し、デー
タ制御部８−１へ転送終了指示を送る。転送終了指示を
受取ったデータ制御部８−１は信号線２４を介しデータ
格納部７−、へ、マイクロプログラムを第２チャネル６
−２内デ一タ格納部７−２へ転送するよう指示すると同
時に、データ制御部８−１は信号線２８を介し、データ
制御部８−２へマイクロプログラム転送を指示する。When the microprogram transfer to the data storage section 7-1 is completed, the data storage section 7- sends a transfer end instruction to the data control section 8-1 via the signal line 24. The data control unit 8-1, which received the transfer end instruction, transfers the microprogram to the data storage unit 7- through the signal line 24 to the second channel 6.
At the same time as instructing the microprogram to be transferred to the internal data storage section 7-2, the data control section 8-1 instructs the data control section 8-2 to transfer the microprogram via the signal line 28.

これによりチャネル１．６−、内のデータ格納部７−１
に格納されているマイクロプログラムはチャネル２．６
−２内のデータ格納部７−２へ転送される。As a result, data storage section 7-1 in channel 1.6-,
The microprogram stored in channel 2.6
-2 is transferred to the data storage section 7-2.

以下同様にチャネルｎ−１＋Ｅｆ−□−１まで次チャネ
ルにマイクロプログラムを転送する方法をとる。Thereafter, the microprogram is similarly transferred to the next channel up to channel n-1+Ef-□-1.

第ｎチャネル６−０内のデータ格納部７−．１にマイク
ロプログラムが転送されるとデータ格納部７−０は信号
線２７を介し、データ制御部８−９へ転送終了指示を送
る。Data storage unit 7-. in n-th channel 6-0. 1, the data storage section 7-0 sends a transfer end instruction to the data control section 8-9 via the signal line 27.

転送終了指示を受取ったデータ制御部８−９は信号線３
１を介し命令制御部９ヘチャネルｎマイクロプログラム
転送終了を報告する。The data control unit 8-9 that received the transfer end instruction transmits the signal line 3.
The completion of channel n microprogram transfer is reported to the instruction control unit 9 via the channel n channel 1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は複数チャネルへのマイクロ
プログラム転送時初回記憶装置よりチャネル制御装置を
介し、第１チャネルへマイクロプログラムを転送し次回
より自チャネル内のマイクロプログラムを次のチャネル
内へ転送して第ｎチャネルまで転送が終了すると第ｎチ
ャネルはマイクロプログラム格納終了をチャネル制御装
置へ報告することにより制御が簡略化するという効果が
ある。As explained above, when transferring a microprogram to multiple channels, the present invention first transfers the microprogram from the storage device to the first channel via the channel control device, and then transfers the microprogram in the own channel to the next channel. When the transfer to the n-th channel is completed, the n-th channel reports the end of microprogram storage to the channel control device, which has the effect of simplifying control.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示すブロック図である。 １・・・記憶装置、２・・・入出力処理装置、３−１〜
３−９・・・入出力装置（１〜ｎ）、４・・・マイクロ
プログラム格納部、５・・・チャネル制御装置、６−１
〜Ｂ−ｎ・・・チャネル（１〜ｎ）、７ｔ〜７−、。 ・・・データ格納部、８−１〜８−、、・・・データ制
御部、９・・・命令制御部、２１〜３１・・・信号線、
４１〜４５・・・データバス、４６−、〜４６−７・・
・データバス。FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Storage device, 2... Input/output processing device, 3-1~
3-9... Input/output device (1 to n), 4... Microprogram storage section, 5... Channel control device, 6-1
~Bn... Channel (1~n), 7t~7-,. ...Data storage section, 8-1 to 8-,... Data control section, 9... Command control section, 21 to 31... Signal line,
41-45...data bus, 46-, ~46-7...
・Data bus.

Claims (1)

【特許請求の範囲】[Claims] マイクロプログラムにより制御されるｎ個のチャネルと
該チャネルを多重制御するチャネル制御装置から成り記
憶装置と入出力装置間のデータ転送を制御する入出力処
理装置において、前記チャネル制御装置には前記記憶装
置に格納されているマイクロプログラムを前記第１のチ
ャネルに転送する手段と、前記第１のチャネルにはマイ
クロプログラム格納終了時に自チャネル内のマイクロプ
ログラムを読み出し前記第２のチャネルへ転送する手段
と、以下同様に前記ｎ−１チャネルまで次のチャネルに
マイクロプログラムを転送する手段と、前記第ｎチャネ
ルにはマイクロプログラム格納時に前記チャネル制御装
置にマイクロプログラム格納終了を報告する手段とを含
むことを特徴とする入出力処理装置。In an input/output processing device that includes n channels controlled by a microprogram and a channel control device that multiplex-controls the channels, and controls data transfer between a storage device and an input/output device, the channel control device includes the storage device means for transferring a microprogram stored in the microprogram to the first channel; and means for reading the microprogram in the own channel and transferring it to the second channel when the microprogram storage is finished in the first channel; Similarly, the nth channel includes means for transferring the microprogram to the next channel up to the n-1 channel, and means for reporting completion of storing the microprogram to the channel control device when storing the microprogram in the nth channel. An input/output processing device.
JP30425690A 1990-11-09 1990-11-09 Input/output processor Pending JPH04175955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30425690A JPH04175955A (en) 1990-11-09 1990-11-09 Input/output processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30425690A JPH04175955A (en) 1990-11-09 1990-11-09 Input/output processor

Publications (1)

Publication Number Publication Date
JPH04175955A true JPH04175955A (en) 1992-06-23

Family

ID=17930870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30425690A Pending JPH04175955A (en) 1990-11-09 1990-11-09 Input/output processor

Country Status (1)

Country Link
JP (1) JPH04175955A (en)

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