JPH04173159A - Video data control circuit - Google Patents

Video data control circuit

Info

Publication number
JPH04173159A
JPH04173159A JP2299352A JP29935290A JPH04173159A JP H04173159 A JPH04173159 A JP H04173159A JP 2299352 A JP2299352 A JP 2299352A JP 29935290 A JP29935290 A JP 29935290A JP H04173159 A JPH04173159 A JP H04173159A
Authority
JP
Japan
Prior art keywords
address
page buffer
page
image
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2299352A
Other languages
Japanese (ja)
Inventor
Masatoshi Tamura
田村 政敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niigata Fuji Xerox Manufacturing Co Ltd
Original Assignee
Niigata Fuji Xerox Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Niigata Fuji Xerox Manufacturing Co Ltd filed Critical Niigata Fuji Xerox Manufacturing Co Ltd
Priority to JP2299352A priority Critical patent/JPH04173159A/en
Publication of JPH04173159A publication Critical patent/JPH04173159A/en
Pending legal-status Critical Current

Links

Landscapes

  • Laser Beam Printer (AREA)
  • Editing Of Facsimile Originals (AREA)
  • Dot-Matrix Printers And Others (AREA)

Abstract

PURPOSE:To make possible the printing of an image rotated at 180 deg. by providing an address decrement device of a page buffer and an LSBAMSB bit exchange device of data. CONSTITUTION:When an image is normally printed, an address 'OH' and an increment are set in an address counter 2, and data is read in the order of ABC... from a page buffer 1 by setting bit replacement OFF. Subsequently, a drawn image is printed as such. When set in the 180 deg. page rotate mode, an address 'XH' and a decrement are set in the address counter 2, and data is read in the order of ZYX... by switching a bit replacement part ON. Thus an image rotated at 180 deg. based on an image drawn in a page buffer 1 is printed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はビデオ・データ制御回路、特に、高印字品質を
有するページプリンタに用いられるビデオ・データ制御
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video data control circuit, and particularly to a video data control circuit used in a page printer having high print quality.

〔従来の技術〕[Conventional technology]

従来、この種のビデオ・データ制御回路は180度のペ
ージローテート機能は持っていなかった。
Conventionally, this type of video data control circuit has not had a 180 degree page rotation function.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のページプリンタは、90度のページロー
テート機能しか持っていなので、両面印字ができないと
いう欠点かあった。
The above-mentioned conventional page printers only have a 90 degree page rotation function, so they have the disadvantage of not being able to print on both sides.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のビデオ・データ制御回路は、1ペ一ジ分のペー
ジバッファと、そのページバッファのアドレスの設定と
アドレスのインクリメント/デクリメントを制御するア
ドレス・カウンタと、前記ページバッファから読み出し
なデータのLSB←→MSBのビット交換をするビット
交換部と、前記読み出しなデータをシリアル・データに
変換するパラレル/シリアル変換部と、各々の制御する
ビデオ制御部とを含んで構成される。
The video data control circuit of the present invention includes a page buffer for one page, an address counter that controls setting of the address of the page buffer and increment/decrement of the address, and LSB of data read from the page buffer. It is configured to include a bit exchange section that exchanges bits of ←→MSB, a parallel/serial conversion section that converts the read data into serial data, and a video control section that controls each of them.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
は本発明のブロック図、第2図はページバッファのアド
レスの割り付は図、第3図は通常印字(ポートレート)
の場合の印字結果を示す図、第4図は180度ページロ
ーテートの印字結果を示す図である。
Next, the present invention will be explained with reference to the drawings. Figure 1 is a block diagram of the present invention, Figure 2 is a diagram of page buffer address allocation, and Figure 3 is normal printing (portrait).
FIG. 4 is a diagram showing the printing results when the page is rotated 180 degrees.

まず通常印字の場合、アドレスカウンタ2にアドレス“
OH″とカウントアツプを設定し、ビット交換をOFF
にすることによりページバッファ1からの読み出しは”
 A B C・・・′°の順となり、描画された画像が
そのまま印字され、印字結果としては第3図のようにな
る。
First, in the case of normal printing, the address “
Set the count up as ``OH'' and turn off the bit exchange.
By doing so, reading from page buffer 1 is “
The drawn image is printed in the order of A B C...'°, and the printed image is as shown in FIG. 3.

180度ページローテートの場合、アドレスカウンタ2
にアドレス“XH”′とカウントダウンを設定し、ビッ
ト交換部をONにすることにより、ページバッファ1か
らの読出しは’zyx・・・″の順となり、ページバッ
ファ1に描画した画像から180度回転した画像が印字
され印字結果としては第4図のようになる。
In case of 180 degree page rotation, address counter 2
By setting the address "XH"' and countdown to , and turning on the bit exchange section, reading from page buffer 1 will be in the order of 'zyx...'', and the image drawn on page buffer 1 will be rotated 180 degrees. The resulting image is printed, and the print result is as shown in FIG.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ページバッファのアドレ
スデクリメンI・手段と、データのLSB←MSBビッ
ト交換手段を持つことにより、180度のページローテ
ート印字ができるので、画面印字ができるという効果が
ある。
As explained above, the present invention has an address decrement I/means for a page buffer and a data LSB←MSB bit exchange means, so that 180 degree page rotation printing can be performed, so that screen printing is possible. There is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のブロック図、第2図はページバッファ
のアドレスの割り付は図、第3図は通常印字(ポートレ
ート)の場合の印字結果を示す図、第4図は180度ペ
ージローテートの印字結果を示す図である。 1・・・ページバッファ、2・・・アドレスカウンタ、
3・・・LSB HMSBビット交換部、4・・パラレ
ル/シリアル変換部、5・・・ビデオ制御部。
Figure 1 is a block diagram of the present invention, Figure 2 is a diagram showing the page buffer address allocation, Figure 3 is a diagram showing the printing results for normal printing (portrait), and Figure 4 is a 180 degree page. FIG. 7 is a diagram illustrating printing results of rotation. 1...Page buffer, 2...Address counter,
3...LSB HMSB bit exchange section, 4...Parallel/serial conversion section, 5...Video control section.

Claims (1)

【特許請求の範囲】[Claims]  1ページ分のページバッファと、そのページバッファ
のアドレスの設定とアドレスのインクリメント/デクリ
メントを制御するアドレス・カウンタと、前記ページバ
ッファから読み出したデータのLSB←→MSBのビッ
ト交換をするビット交換部と、前記読み出したデータを
シリアル・データに変換するパラレル/シリアル変換部
と、各々の制御するビデオ制御部とを含むことを特徴と
するビデオ・データ制御回路。
A page buffer for one page, an address counter that controls setting of the address of the page buffer and increment/decrement of the address, and a bit exchange unit that exchanges bits of LSB←→MSB of data read from the page buffer. , a parallel/serial conversion unit that converts the read data into serial data, and a video control unit that controls each of the parallel/serial conversion units.
JP2299352A 1990-11-05 1990-11-05 Video data control circuit Pending JPH04173159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2299352A JPH04173159A (en) 1990-11-05 1990-11-05 Video data control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2299352A JPH04173159A (en) 1990-11-05 1990-11-05 Video data control circuit

Publications (1)

Publication Number Publication Date
JPH04173159A true JPH04173159A (en) 1992-06-19

Family

ID=17871448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2299352A Pending JPH04173159A (en) 1990-11-05 1990-11-05 Video data control circuit

Country Status (1)

Country Link
JP (1) JPH04173159A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016212192A (en) * 2015-05-01 2016-12-15 ローム株式会社 DSD decoder, audio system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016212192A (en) * 2015-05-01 2016-12-15 ローム株式会社 DSD decoder, audio system

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