JPH04172965A - Double voltage generating circuit - Google Patents
Double voltage generating circuitInfo
- Publication number
- JPH04172965A JPH04172965A JP30023690A JP30023690A JPH04172965A JP H04172965 A JPH04172965 A JP H04172965A JP 30023690 A JP30023690 A JP 30023690A JP 30023690 A JP30023690 A JP 30023690A JP H04172965 A JPH04172965 A JP H04172965A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- series
- capacitors
- generating circuit
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 238000010586 diagram Methods 0.000 description 4
- 238000007792 addition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】 本発明は倍電圧発生回路に関するものである。[Detailed description of the invention] The present invention relates to a voltage doubler generating circuit.
従来から、倍電圧発生回路として、直流電源、インバー
タ回路、及び倍電圧整流回路から成るものなどが知られ
ている。2. Description of the Related Art Conventionally, voltage doubler generating circuits consisting of a DC power supply, an inverter circuit, and a voltage doubler rectifier circuit have been known.
第1図は従来の倍電圧発生回路の例である。図において
1.2は直流入力端子、c、dは直流出力端子、Sl、
S2、S3、S4はサイリスタ、トランジスタ等のスイ
ッチ素子、Dl、D2はダイオード、CI、C2は倍電
圧用のコンデンサ、Ellは直流電源、Roは倍電圧発
生回路の負荷である。FIG. 1 is an example of a conventional voltage doubler generating circuit. In the figure, 1.2 is a DC input terminal, c, d are DC output terminals, Sl,
S2, S3, and S4 are switching elements such as thyristors and transistors, Dl and D2 are diodes, CI and C2 are voltage doubler capacitors, Ell is a DC power supply, and Ro is a load of the voltage doubler generating circuit.
直流電源E、が入力1.2に接続され、■1を印加する
と、Sl、34が閉路、S2、S3が開路であるとE、
十→S1→D1→C1−84−E、−の順に通電し、C
1を■1まで充電する。次に81、S4が開路、S2、
S3が閉路であると、E、+−83→C2→D2→S2
→E4、−の順に通電し て=IンデンサC2を■1ま
で充電する。以下、この動作を繰返すことによりコンデ
ンサC1,C2の容量が十分大きく、ダイオードD1.
D2の電圧降下を無視すればC1,C2の直列回路の両
端電圧V。は2V、となり、倍電圧発生回路となる。こ
のように第1図の倍電圧発生回路ではスイッチ素子が少
なくとも4個必要となり、スイッチ素子の制御回路を含
め、構造が複雑で、高価となる。又、更に、縦続接続に
より4倍電圧等を得る場合、インバータ回路が各段ごと
に必要になるなどの欠点がある。When DC power source E is connected to input 1.2 and 1 is applied, Sl and 34 are closed and S2 and S3 are open, E,
Electrify in the order of 10 → S1 → D1 → C1-84-E, -, and C
Charge 1 to ■1. Next, 81, S4 is open, S2,
If S3 is a closed circuit, E, +-83 → C2 → D2 → S2
→Turn on power in the order of E4 and - to charge =I capacitor C2 to ■1. Thereafter, by repeating this operation, the capacitance of capacitors C1 and C2 becomes sufficiently large, and diode D1.
If the voltage drop of D2 is ignored, the voltage across the series circuit of C1 and C2 is V. becomes 2V, and becomes a voltage doubler generating circuit. As described above, the voltage doubler generating circuit shown in FIG. 1 requires at least four switching elements, and the structure including the control circuit for the switching elements is complicated and expensive. Furthermore, when obtaining a quadrupled voltage or the like by cascade connection, there is a drawback that an inverter circuit is required for each stage.
本発明は前記せる従来回路の欠点を解消し、簡単な回路
で、かつ、効率の高い倍電圧発生回路を提供することを
目的とし、又、高電圧回路や交流変換回路への適用を可
能とする倍電圧発生回路を提供する。第2図は本発明の
実施例であり、第5図は第2図の動作説明図である。両
図中、E8は、直流電源、a、bは直流入力端子、c、
clは直流出力端子、DI D2は整流ダイオード、
Ci 、C2はコンデンサ、Sl、S2はサイリスタ、
トランジスタ等のスイッチ素子、ROは負荷である。The present invention aims to eliminate the drawbacks of the conventional circuits mentioned above and provide a simple and highly efficient voltage doubler generating circuit, and also to be applicable to high voltage circuits and AC conversion circuits. The present invention provides a voltage doubler generating circuit that performs the following steps. FIG. 2 shows an embodiment of the present invention, and FIG. 5 is an explanatory diagram of the operation of FIG. 2. In both figures, E8 is a DC power supply, a, b are DC input terminals, c,
cl is a DC output terminal, DI D2 is a rectifier diode,
Ci, C2 are capacitors, Sl, S2 are thyristors,
Switch elements such as transistors and RO are loads.
即ち、スイッチ素子S1と82を直列に接続し、その両
端部(第1の両端部という)を直流入力端子a、bに接
続する。又、コンデンサC】と02を直列に接続し、そ
の両端部(第2の両端部という)を直流出力端子c、d
に接続する。更に、第1の両端部と第2の両端部間に、
それぞれ、整流ダイオードD1、D2をE R+ −1
C4D 1−+ C−+ R。That is, the switch elements S1 and 82 are connected in series, and both ends thereof (referred to as first ends) are connected to DC input terminals a and b. Also, capacitors C] and 02 are connected in series, and both ends (referred to as second ends) are connected to DC output terminals c and d.
Connect to. Furthermore, between the first and second ends,
Respectively, the rectifier diodes D1 and D2 are E R+ -1
C4D 1-+ C-+ R.
→d−D2−b+EI]−に通電する方向に接続し、ス
イッチ素子S1と82の中間点とコンデンサC1と02
の中間点間を結線する。→d-D2-b+EI]- in the direction of energization, and the midpoint between switch elements S1 and 82 and capacitors C1 and 02
Connect between the intermediate points.
次に動作について説明する。第2図のa、b端子に直流
電源ERが接続されvlが印加され、Slが開路、S2
が閉路であると、第3図(a)のモードIに示す通り、
C1への充電電流11が01の電圧が■1になるまで流
れる。次に、第2図でSlが閉路、S2が開路となると
、第3図(b)のモードHに示す通り、充電電流12が
流れて02がVlまで充電される。以下この動作を繰返
すことにより直列接続されたコンデンサC1,C2め第
2の両端部には直流入力電圧の2倍の電圧V2が得られ
る。負荷R6への直流出力はスイッチ素子S1、S2の
動作周波数の増加や、コンデンサC1,C2の容量の増
大により、変動の少ないものとなる。Next, the operation will be explained. DC power supply ER is connected to terminals a and b in Fig. 2, vl is applied, Sl is open, and S2
If is a closed circuit, as shown in mode I in Fig. 3(a),
The charging current 11 to C1 flows until the voltage of 01 becomes ■1. Next, when Sl is closed and S2 is opened in FIG. 2, charging current 12 flows and 02 is charged up to Vl, as shown in mode H in FIG. 3(b). Thereafter, by repeating this operation, a voltage V2 twice the DC input voltage is obtained at both ends of the second capacitors C1 and C2 connected in series. The DC output to the load R6 has less fluctuation due to an increase in the operating frequency of the switching elements S1 and S2 and an increase in the capacitance of the capacitors C1 and C2.
第4図は本発明の倍電圧発生回路をインバータ回路に応
用した例である。直流電源E6がバッテリーである場合
に容易に昇圧が可能であり、直流入力電圧の2倍に昇圧
された出力電圧■2をスイッチ素子S3、S4、S5、
S6により構成される例えば、ブリッジインバータ回路
に印加して、交流出力■。を得ることが出来る。FIG. 4 shows an example in which the voltage doubler generating circuit of the present invention is applied to an inverter circuit. When the DC power source E6 is a battery, it is possible to easily boost the voltage, and the output voltage 2, which is boosted to twice the DC input voltage, is transferred to the switch elements S3, S4, S5,
For example, it is applied to a bridge inverter circuit configured by S6 to output AC. can be obtained.
第5図は、該本発明の倍電圧発生回路を2段縦続接続し
た例である。これにより、出力電圧V3はコンデンサC
1、C2、C3、C4が十分大きく、D 1 、 D
2.D 3.D4.S 1、S2、S3.S4の電圧降
下を無視すれば直流入力電圧■1の4倍が得られる。更
に、段数を増せばn段のときには2n倍の出力電圧が得
られる。FIG. 5 shows an example in which two stages of voltage doubler generating circuits according to the present invention are connected in cascade. As a result, the output voltage V3 becomes the capacitor C
1, C2, C3, and C4 are sufficiently large, and D 1 and D
2. D3. D4. S1, S2, S3. If the voltage drop of S4 is ignored, four times the DC input voltage ■1 can be obtained. Furthermore, if the number of stages is increased, an output voltage 2n times higher can be obtained when there are n stages.
第2図、第4図及び第5図の本発明の実施例は利用上、
種々の変形をなし得るものである。The embodiments of the present invention shown in FIGS. 2, 4, and 5 may be used in
Various modifications can be made.
例えば、直流電源EBはバッテリでなく、交流電源を整
流器により変換して得る場合、ブリッジインバータ以外
のインバータ回路を用いる場合、縦続段数を増加した場
合、各種の保護装置を付加する場合、その他、設計上の
変更、付加等は本発明の要旨の範囲で本願に含まれるも
のである。For example, when the DC power supply EB is obtained by converting the AC power supply with a rectifier instead of a battery, when an inverter circuit other than a bridge inverter is used, when the number of cascade stages is increased, when various protection devices are added, and in other cases, the design The above changes, additions, etc. are included in the present application within the scope of the gist of the present invention.
本発明によれば、極めて簡単な回路で効率も高くバッテ
リ等の直流電源を昇圧出来ることから、インバータ回路
の直流入力用等に有効であり、産業上の利用効果大であ
る。According to the present invention, since it is possible to boost the voltage of a DC power source such as a battery with a very simple circuit and high efficiency, it is effective for DC input of an inverter circuit, and has great industrial effects.
第1図IJ従来回路の例、第2図は本発明の実施例をし
めす回路図、第3図は第2図の動作説明図、第4図、第
5図は本発明の他の実施例をしめす回路図であり、Sl
、S2、S3、S4.S5.S6はスイッチ素子、C1
,C2、C3、C4はコンデンサ、DI、D2、D3、
D4は整流ダイオード、EBは直流電源、Roは負荷、
V 1 、V 2 、V 3、Voは各指定の電圧、a
、b、c、d、e、f、3.4は指定の各端子である。
特許出願人 新電元工業株式会社2
I!1図
尾2図
a Dl
第3図
第4図
第5図Fig. 1 is an example of a conventional IJ circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Figs. 4 and 5 are other embodiments of the present invention. This is a circuit diagram showing Sl.
, S2, S3, S4. S5. S6 is a switch element, C1
, C2, C3, C4 are capacitors, DI, D2, D3,
D4 is a rectifier diode, EB is a DC power supply, Ro is a load,
V 1 , V 2 , V 3 , Vo are each specified voltage, a
, b, c, d, e, f, and 3.4 are designated terminals. Patent applicant: Shindengen Kogyo Co., Ltd. 2
I! Figure 1 Tail Figure 2 a Dl Figure 3 Figure 4 Figure 5
Claims (3)
したコンデンサ、及び前記直列接続したスイッチ素子の
第1の両端部と前記直列接続したコンデンサの第2の両
端部間に接続される各整流ダイオードから成り、前記直
列接続したスイッチ素子の中間点と直列接続したコンデ
ンサの中間点を結線し、第1の両端部を直流電源側に並
列に、又、第2の両端部を負荷側に並列に接続し、前記
整流ダイオードの接続を負荷電流の通電方向とし、前記
直列接続したスイッチ素子は交互にオンオフするように
したことを特徴とする倍電圧発生回路。(1) A DC power supply, a series-connected switch element, a series-connected capacitor, and each rectifier diode connected between the first end of the series-connected switch element and the second end of the series-connected capacitor. The intermediate point of the series-connected switch elements and the intermediate point of the series-connected capacitor are connected, and the first both ends are connected in parallel to the DC power supply side, and the second both ends are connected in parallel to the load side. A voltage doubler generating circuit characterized in that the connection of the rectifier diode is made to be in the direction of conduction of the load current, and the switch elements connected in series are alternately turned on and off.
の倍電圧発生回路。(2) The voltage doubler generating circuit according to claim (1), which is connected in series in multiple stages.
(1)項又は第(2)項の倍電圧発生回路。(3) The voltage doubler generating circuit according to claim (1) or (2), which additionally connects an inverter circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30023690A JPH04172965A (en) | 1990-11-06 | 1990-11-06 | Double voltage generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30023690A JPH04172965A (en) | 1990-11-06 | 1990-11-06 | Double voltage generating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04172965A true JPH04172965A (en) | 1992-06-19 |
Family
ID=17882352
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30023690A Pending JPH04172965A (en) | 1990-11-06 | 1990-11-06 | Double voltage generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04172965A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103887987A (en) * | 2014-04-17 | 2014-06-25 | 南京航空航天大学 | Multiple voltage-multiplying high-gain high-frequency rectification isolation converter based on switched capacitor |
-
1990
- 1990-11-06 JP JP30023690A patent/JPH04172965A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103887987A (en) * | 2014-04-17 | 2014-06-25 | 南京航空航天大学 | Multiple voltage-multiplying high-gain high-frequency rectification isolation converter based on switched capacitor |
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