JPH04172698A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the need of enlarging the memory cell size of a semiconductor integrated circuit by providing a plurality of kinds of memory cell transistors having different gate turning-on threshold voltages and a voltage transformation circuit which changes the voltages applied across the gates of the memory cell transistors. CONSTITUTION:Memory cell transistors 3 having different threshold voltages and a voltage transformation circuit 7 which can arbitrarily change the gate voltages for turning on the transistors 3 are provided. Since the plurality of kinds of memory cell transistors 3 having different threshold voltages are provided, plural kinds of information can be held by means of one memory cell transistor 3. Therefore, the cell size of this semiconductor device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to nonvolatile integrated circuits.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional nonvolatile integrated circuit. Third
In the figure, a row (word) decoder 1 and a column (bit) decoder 2 select a memory cell transistor 3, output information to an output 4, and repeat this operation to select an arbitrary memory cell transistor 3. I was able to obtain information.

For example, word line A is Ov, word lines B, C, and D are 5V.
, When bit line A is set to 5V and bit lines B, C, and D are set to OV, output 4 is the memory cell transistor (A).
In the case of depression type (D type), it is OV, and in the case of enhancement type (E type), it is 5V. In FIG. 3, memory cell transistors (A), (B), (C), (
D) is type E.

For E type, D type, and E type, the output is 5 V each.
, 5 V, OV, 5 V Tonari,
The information is 1.1, 0.1.

In conventional non-volatile integrated circuits, a depletion type transistor and an enhancement type transistor are formed by an implantation method in the manufacturing process, and any transistor in this memory cell is selected, and whether the selected transistor is a depletion type or an enhancement type transistor is formed. By determining the type of transistor, information about the transistor could be determined as "1" or "0".

[Problem to be solved by the invention]

In such conventional non-volatile integrated circuits, memory cell transistors are of two types: depletion type and enhancement type, and one transistor has “1
” or “0” because only one data can be stored.
As the size of the semiconductor device becomes larger, the area of the semiconductor device increases, and the resulting decrease in yield hinders the development of the semiconductor device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that solves the above problem and eliminates the need for increasing memory cell size.

[Means to solve the problem]

The structure of the semiconductor integrated circuit of the present invention is characterized by comprising a plurality of types of memory cell transistors having different gate threshold voltages for turning on, and a transformer circuit for changing the voltage applied to the gate of the memory cell transistor. do.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, in this embodiment, a row (word)
Decoder 1, column (focus) decoder 2, and transformer circuit 7
, a transistor (A), and a transistor (B). The transistor 3 consists of two types: a transistor (A) and a transistor (B).

In FIG. 1, this embodiment has a transformer circuit 7 between a row decoder 1 and a memory cell transistor 3. The threshold voltage is 0V (D type), 2V, 4V, e
It has four types of V transistors. For example, in FIG. 1, if the threshold voltage of the memory cell transistor (A) is 6V and the threshold voltage of the transistor (B) is 2V, the bit line A is 5V, the bit line B is OV,
Word lines B, C, and D are set to 5V, and word line A voltage is set to O.
When the voltage is changed to V, 2V, and 4V, the threshold voltage of the memory cell transistor (A) is 6V, so the transistor is always OFF and the output is always 5V. Similarly, in the case of transistor (B), when the voltage to the word line is OV, the output is 5V, when it is 2V, it is OV, and when it is 4V, the output is O
It becomes V.

As shown in FIG. 2, by determining the information of the memory cell transistor based on the output voltage of the word line and whether it changes from 5V to OV, it is possible to obtain two pieces of information with one memory cell transistor 3. It becomes possible.

In this embodiment, h of the memory cell transistor (A)
The information of the memory cell transistor (B) is "0.1", and compared to the conventional non-volatile integrated circuit shown in Figure 3, half the transistors have the same amount of information. becomes possible.

As described above, in this embodiment, deblecron type enhancement type transistors are formed in memory cells and transistors by ion implantation, and in nonvolatile integrated circuits that store information during the semiconductor manufacturing process. It is sufficient to have a memory cell transistor having a plurality of types of threshold voltages and a transformer circuit capable of arbitrarily changing the gate voltage for turning on the memory cell transistor.

〔Effect of the invention〕

As explained above, since the present invention uses multiple types of memory cell transistors with different threshold voltages, it is possible to hold multiple pieces of information with one memory cell transistor, and as a result, semiconductor This has the effect of reducing the cell size of the device and improving storage capacity.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a correspondence table between the output voltage and the information obtained with respect to the word line voltage in FIG. 1, and FIG. The figure is a circuit diagram of a conventional nonvolatile integrated circuit. 1... Row (word) decoder, 2... Column (bit)
Decoder, 3...Memory cell transistor, 4...
Output, 5...word line, 6...bi-soto line, 7...
・Transformer circuit.

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising: a plurality of types of memory cell transistors having different gate/threshold voltages to be turned on; and a transformer circuit for changing the voltage applied to the gates of the memory cell transistors.