JPH04172660A - Video signal processor - Google Patents

Abstract

PURPOSE:To accurately control carriers of a plurality of FM modulators by operating the modulators as a function of a voltage controlled oscillator (VCO) in a PLL, and operating the modulators by the PLL. CONSTITUTION:An FM modulator is composed of phase-locked loop (PLL) control type FM modulators 20, 21, and an FM modulation signal is modulated by using a clock divided in frequency by the ratio of integer multiples of a certain clock. That is, the modulator 20 (21) is composed of an FM modulator 201, a frequency divider 202 having 1/M of frequency dividing ratio, a frequency divider 203 having 1/N of frequency dividing ratio, a phase comparator 204, and a low pass filter 206 connected thereto to use the fact that the modulator 201 is operated as a function of a VCO. Thus, a difference of the carriers of the modulators is very reduced, and accurate FM modulation is performed by a simple circuit configuration.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal recording and reproducing device such as a high-definition VTR device, and particularly to a recording medium by FM modulating a video signal divided into multiple channels. The present invention relates to a video signal recording device that accurately synchronizes a plurality of channels and performs FM modulation and recording when recording on a video signal.

[Conventional technology]

FIG. 3 shows a circuit configuration of a recording system of a high-definition VTR device (HDVTR device) as a conventional video signal recording device.

The recording system REC of this HDVTR device includes low pass filters (LPFs) 1 to 3. Analog/digital signal conversion circuits (ADC) 5 to 7, TDM encoder circuit 8, synchronization signal generation circuit 10. Signal addition circuits 11, 12. Digital/analog signal conversion circuit (DAC) 14, 15.
LPF16°17, analog signal processing circuits 18, 19.
FM modulation circuit 30.31. and amplifier circuit 22.23
are connected and configured as shown in the figure. Other than this.

Although an emphasis circuit and the like are provided, they are not shown.

Note that the HDVTR device is provided with a reproduction system corresponding to the recording system REC, but it is not shown.

The baseband signal recording luminance signal Y and recording color difference signals PB and PR are applied to LPFs 1 to 3, low-pass filtered, and converted into digital signals by AD05 to AD7. The luminance signal Y converted to a digital signal is TDM
The encoder circuit 8 expands the time axis. Also TD
In the M encoder circuit 8, the color difference signals PB and PR converted into digital signals are each digitally filtered and line-sequentially and time-base compressed. Further, the time-axis expanded luminance signal Y and the time-axis compressed color difference signals PB and PR are shuffled in the TDM encoder circuit 8 and converted into TCI signals of signals A and B. The synchronizing signal 5YNC from the synchronizing signal generating circuit 10 and the burst signal BLIR5T are added to the video signals divided into these contrasting signals A and B to the signal adding circuit 11.
12. The channel-divided video signal to which the synchronization signal 5YNC and burst signal BUR3T are added is converted into an analog signal by the DA, C14, and 15, and the LP
The signal is low-pass filtered at F16.17 and subjected to predetermined analog signal processing at analog signal processing circuits 18 and 19. Further, the FM modulation circuit 30.31 performs FM modulation, and the amplification circuit 22.23 amplifies the 5-rotation drum 25.
The information is recorded on a magnetic tape (not shown) via a magnetic tape.

[Problem B to be Solved by the Invention] In order to eliminate adjacent crosstalk, the modulation center frequency of the FM modulation circuit is usually shifted by half the line frequency for each track.

When performing carrier (carrier wave) offset for the purpose of crosstalk cancellation, it is necessary to accurately manage the amount of offset of the FM modulation carrier.

Since a single channel type VTR device has only one FM modulation circuit, carrier differences can be managed quite accurately.

However, in a multi-channel VTR device, channels A and B are provided with FM modulation circuits 30 and 31 as shown in FIG.
It is difficult to accurately match the absolute values of the carriers of the M modulation circuits 30 and 31. For this purpose, the FM modulation circuit 30
．． There is a problem in that a dedicated accurate lock is required for 31, making the two-circuit configuration complicated.

An object of the present invention is to enable accurate control of carriers in a plurality of FM modulation circuits with a simple circuit configuration in a multi-channel video signal processing device that performs FM modulation, such as an HDVTR device.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an FM modulation circuit with a phase-locked (PLL) controlled FM modulation circuit configuration, and
The M modulation frequency signal is modulated using a clock whose frequency is divided by an integral multiple of a certain clock signal.

That is, the video signal processing device of the present invention that performs FM modulation on video signals of multiple channels includes FM modulating the video signals of multiple channels in synchronization with a clock signal obtained by dividing a predetermined clock signal by an integral multiple ratio. Multiple PLLs! An il [type FM modulation circuit is provided.

[Effect]

The FM modulation circuit is a voltage controlled oscillator (VCO) in the PLL.
This FM modulation circuit is operated by PLL. This makes the carrier of the FM modulation circuit accurate. Particularly, when PLL control is performed using a clock obtained by dividing a clock signal into an integer multiple, the carrier difference between the FM modulation circuits becomes extremely small.

(Embodiment) FIG. 1 shows the configuration of a recording system REC of an HDVTR device corresponding to FIG. 3 as an embodiment of the video signal processing apparatus of the present invention. The same reference numerals in FIG. 1 and FIG. 3 indicate the same components.

In the recording system REC of the HDVTR device shown in FIG.

In place of the conventional FM modulation circuit 30 and 31 in FIG.
L-controlled FM modulation circuits 20 and 21 are provided.

FIG. 2 shows the circuit configuration of the PLL @ control FM modulation circuit 20. This PLL control type FM modulation circuit 20 includes an FM modulation circuit 2019, a frequency division circuit 2021 with a frequency division ratio of 1/M, a frequency division circuit 203 with a frequency division ratio of 1/N, a phase comparator 204. A low-pass filter 205 is connected and configured as shown. As is clear, this circuit is a PLL circuit configuration that utilizes the fact that the FM modulation circuit 201 functions as a CO.

An existing TDM clock CLK in the HDVTR device, which is applied to the DACs 14 and 15, is applied to the 1/M frequency divider circuit 202. TDM black, CLK frequency f C
Let's call it LK. Further, the output frequency of the FM modulation circuit 201 is assumed to be fo. -Describe the operation of the circuit shown in Figure 2. 1/M
The frequency divider circuit 202 has a TDM clock C of frequency f CLK.
When LK is applied, the frequency is divided by 1/M and its output frequency becomes f CLK /M, and the TDM clock CLK frequency-divided by 1 is applied to the phase comparator 204 . On the other hand, F.M.
The output signal of the frequency f0 of the modulation circuit 201 is frequency-divided by 1/N by the 1/N frequency divider circuit 203 and applied to the phase comparator 204. Phase comparator 204 outputs an output corresponding to the phase difference between the two input signals to low-pass filter 205. Since the control voltage signal filtered by the low-pass filter 205 is applied to the FM modulation circuit 201 as a VCO control voltage signal of the modulation center frequency, the FM modulation circuit 201 receives the voltage applied from the analog signal processing circuit 18 according to the modulation center frequency. F
M modulates. The FM modulation center frequency f is defined by the following equation.

to= (N/M)rctx --- (1)T
DM clock CLK frequency rctx, division ratio 1/N,
1/M and FM modulation center frequency f. An example is shown below.

(1) fcLK = 29.97MH2 When N/M = 5/8, f, = 18.73125MHz (2) fcL, = 30', 753MHzN/M
=9/16 f0=17.298563MHz (3) fcL,! -30.753MHzN/M= 19
/32, fo-18, 259594MHz Channel A TCI format video signal applied from the analog signal processing circuit 18 to the FM modulation circuit 201 is modulated by the FM modulation circuit 201 and sent to the rotating drum 25 via the amplifier circuit 22. is applied and recorded on a 7M1 air tape.

PLL! The IIfI type FM modulation circuit 21 also has the same circuit configuration as described above and performs the same operation as described above.

Here, since the FM modulation circuit is of PLL II configuration as described above, the modulation center frequency is accurate and stable. Also, since the Cronk signal is set to a ratio of an integer multiple of N/M, 5
The absolute values of the carriers of both PLL-controlled FM modulation circuits 20 and 21 match, and the carrier difference is small. Furthermore, this PLL
Since the existing TDM clock CLK is used as the operating clock for the II-type FM modified FM modulation circuit 20, there is no need to provide a special clock generation circuit.

Although the above embodiment has been exemplified with respect to the recording system REC of an HDVTR device, the present invention can be applied to various other devices that perform FM modulation on video signal signals of a plurality of channels similar to those described above.

〔Effect of the invention〕

As described above, according to the present invention, accurate FM modulation is possible with a simple circuit configuration in a video signal processing device.

[Brief explanation of the drawing]

FIG. 1 shows an HDVT of an embodiment of the video signal processing device of the present invention.
A circuit diagram of a recording system of the R device. FIG. 2 is a PLL-controlled FM modulation circuit diagram in FIG. 1. FIG. 3 is a circuit diagram of a recording system of a conventional HDVTR device. (Explanation of symbols) 20.21...PLL1+1IJil type FM modulation circuit. 201...FM modulation circuit. 202.203... Frequency divider circuit. 204...Phase comparison circuit. 205...Low pass filter.

Claims (1)

[Claims] 1. In a video signal processing device that performs FM modulation of video signals of multiple channels, the video signals of multiple channels are subjected to FM modulation in synchronization with a clock signal obtained by frequency-dividing a predetermined clock signal at an integral multiple ratio. FM using multiple phase-locked circuit controlled FM modulation circuits that modulate
A video signal processing device characterized by modulation.