JPH04171816A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH04171816A
JPH04171816A JP30084790A JP30084790A JPH04171816A JP H04171816 A JPH04171816 A JP H04171816A JP 30084790 A JP30084790 A JP 30084790A JP 30084790 A JP30084790 A JP 30084790A JP H04171816 A JPH04171816 A JP H04171816A
Authority
JP
Japan
Prior art keywords
contact hole
photoresist
insulating film
shallow
deep
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30084790A
Other languages
Japanese (ja)
Inventor
Soichi Nishida
西田 宗一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP30084790A priority Critical patent/JPH04171816A/en
Publication of JPH04171816A publication Critical patent/JPH04171816A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the area occupied by a shallow contact hole by forming at least a deep contact having a tapered shape and the shallow contact hole having no tapered shape in an opening formed on an insulating film on a semiconductor substrate. CONSTITUTION:After a LOCOS separating layer 12 and polycrystalline silicon wiring layer 13 are formed on a semiconductor substrate 11 and an interlayer insulating film 14 is deposited on the substrate 11, a photoresist 15 is patterned. During the course of the patterning process, a remaining part 17 of the photoresist is intentionally formed in a shallow contact hole forming section 16. Because of the photoresist 17, no wet etching takes place in the section 16 when the wet etching is performed in the next process. After the wet etching, a shallow contact hole 19 is formed by removing the photoresist 17 in the section 16 and the insulating film 14 by dry etching. In a deep contact hole forming section 18, a deep contact hole 20 is formed. Finally, a metallic wiring material 21 is deposited and metallic wiring is patterned.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、微細なコンタクトホールを有する半導体装置
およびその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having fine contact holes and a method for manufacturing the same.

従来の技術 半導体装置は高集積化、多機能化へと限りなく進化して
いる。特にMOSメモリー分野における超微細半導体製
造技術の進歩は目ざましいものがある。一般に多層多結
晶シリコン配線を用いたデバイスでは、各配線間の眉間
絶縁膜が幾層にもなり、結果的に眉間絶縁膜がかなりの
厚さになる。
Conventional technology Semiconductor devices are evolving endlessly to become highly integrated and multi-functional. In particular, the progress of ultra-fine semiconductor manufacturing technology in the field of MOS memory is remarkable. Generally, in a device using multilayer polycrystalline silicon wiring, the glabellar insulating film between each wiring has many layers, resulting in a considerable thickness of the glabellar insulating film.

この眉間絶縁膜にコンタクトホールを開口し、最上層部
の金属配線から最下部のシリコン基板までのコンタクト
を形成すると、かなりの深さをもったコンタクトホール
となり、金属配線材料がコンタクトホール内に十分堆積
されず、コンタクトホール内での金属配線の断線等が発
生し易くなる。これを回避するためには、第2図に示す
ようにコンタクトホールの開口部のみを大きくし、金属
配線材料がコンタクトホール内に十分に堆積されるよう
にするテーパエツチング技術が用いられる。すなわち第
2図において、1はシリコン基板、2はLOGO3分離
層、3は多結晶シリコン配線層、4は眉間絶縁膜、5は
フォトレジストパターン、6は浅いコンタクトホール、
7は深いコンタクトホールである。このコンタクトホー
ル6.7のテーパ部のエツチングには、等方性エツチン
グを行い、コンタクトホール開口部に十分テーパを形成
してから異方性エツチングを行い、テーパ形状をもった
コンタクトホール6.7を形成する。また、上記等方性
エツチングには一般的に化学薬品類を用いたウェットエ
ツチング技術が用いられ、上記異方性エツチングにはド
ライエツチング技術が用いられている。
If a contact hole is opened in this glabella insulating film and a contact is formed from the top layer metal wiring to the bottom silicon substrate, the contact hole will be quite deep, and the metal wiring material will be sufficiently filled in the contact hole. The metal wiring is not deposited, and the metal wiring is likely to be disconnected within the contact hole. In order to avoid this, as shown in FIG. 2, a taper etching technique is used in which only the opening of the contact hole is enlarged so that metal wiring material is sufficiently deposited within the contact hole. That is, in FIG. 2, 1 is a silicon substrate, 2 is a LOGO3 separation layer, 3 is a polycrystalline silicon wiring layer, 4 is an insulating film between the eyebrows, 5 is a photoresist pattern, 6 is a shallow contact hole,
7 is a deep contact hole. For etching the tapered portion of the contact hole 6.7, isotropic etching is performed, and after forming a sufficient taper at the contact hole opening, anisotropic etching is performed to form the contact hole 6.7 with a tapered shape. form. Further, a wet etching technique using chemicals is generally used for the above-mentioned isotropic etching, and a dry etching technique is used for the above-mentioned anisotropic etching.

発明が解決しようとする課題 このような従来のコンタクトホールの形成方法では、微
細配線パターンデバイスにおいて、浅いコンタクトホー
ルと深いコンタクトホールの差が大きく、しかも金属配
線材料のコンタクトホール部分における段差被覆性を良
くするために、深いコンタクトホール程大きなテーパを
形成する必要性があり、深いコンタクトホールにおいて
十分なテーパ形状を作るためにウェットエツチングを行
うと、浅いコンタクトホールにおいては、このウェット
エツチングによりサイドエツチングが広がり、浅いコン
タクトホール6の占有面積が大きくなりすぎるという課
題を有していた。
Problems to be Solved by the Invention In such conventional contact hole forming methods, there is a large difference between shallow and deep contact holes in fine wiring pattern devices, and it is difficult to improve step coverage in the contact hole portion of the metal wiring material. In order to improve etching, it is necessary to form a larger taper for deeper contact holes.If wet etching is performed to create a sufficient taper shape for deep contact holes, this wet etching will cause side etching to occur in shallow contact holes. There was a problem in that the area occupied by the wide and shallow contact hole 6 became too large.

本発明は上記課題を解決するもので、深さの浅いコンタ
クトホールの占有面積を小さくした半導体装置およびそ
の製造方法を提供することを目的としている。
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which the area occupied by a shallow contact hole is reduced, and a method for manufacturing the same.

課題を解決するための手段 本発明は上記目的を達成するために、半導体基板上の絶
縁膜に形成された開口部にテーパ形状を有する深さの深
いコンタクトホールと、テーパ形状を有さない深さの浅
いコンタクトホールとを少な(とも有する構成による。
Means for Solving the Problems In order to achieve the above object, the present invention provides a deep contact hole having a tapered shape in an opening formed in an insulating film on a semiconductor substrate and a deep contact hole having a non-tapered shape. Due to the structure having a small number of shallow contact holes.

作用 本発明は上記構成により、浅いコンタクトホール部分で
は底部のフォトレジストが残っているため、テーパエツ
チングを行う際のウェットエツチングが進行せずテーパ
が形成されず、深いコンタクトホールにおいては、通常
通りのテーパが形成され、次工程でのドライエツチング
工程で浅いコンタクトホール部分では、フォトレジスト
残膜をエッチオフしてからコンタクトホールのエツチン
グが進み、また深いコンタクトホールでは通常通りのエ
ツチングが行なわれ、深さの深いコンタクトホールにお
いて理想的なテーパ形状を得、深さの浅いコンタクトホ
ールではほとんどテーパ形状なしに、微小な占有面積の
コンタクトホールが得られる。
Effects of the present invention With the above structure, the photoresist at the bottom remains in the shallow contact hole portion, so wet etching does not proceed during taper etching and no taper is formed, and in the deep contact hole, the photoresist remains as usual. A taper is formed, and in the dry etching process in the next process, the remaining photoresist film is etched off in the shallow contact hole portion, and then the contact hole etching progresses, and the deep contact hole is etched as normal. An ideal taper shape can be obtained in a deep contact hole, and a contact hole with a small occupied area can be obtained with almost no taper shape in a shallow contact hole.

実施例 本発明の一実施例について図面を用いながら説明を行な
う。第1図(a)〜(d)に本発明のコンタクトホール
の形成方法における工程断面図を示す。
Embodiment An embodiment of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(d) show cross-sectional views of steps in the method of forming a contact hole of the present invention.

まず従来例と同じく、第1図(a)に示すように半導体
基板11上に、LOCO8分離層12、多結晶シリコン
配線層13を形成し、層間絶縁膜14を堆積した後、本
発明の特徴とするフォトレジスト15のパターニングを
行う。この際、浅いコンタクトホール形成部分16に故
意にフォトレジスト残り17を発生させる。この現象は
一般にパターン寸法を小さ(すると露光不足となり、底
部の露光不足部に7オトレジストが残るようになる。な
お、18は深さの深いコンタクトホール形成部分である
First, as in the conventional example, as shown in FIG. 1(a), a LOCO8 isolation layer 12 and a polycrystalline silicon wiring layer 13 are formed on a semiconductor substrate 11, and an interlayer insulating film 14 is deposited. The photoresist 15 is patterned. At this time, a photoresist residue 17 is intentionally generated in the shallow contact hole forming portion 16. This phenomenon generally occurs when the pattern size is reduced (which results in underexposure, and 7 photoresists remain in the underexposed area at the bottom. Note that 18 is a deep contact hole formation area).

次に第1図(b)に示すようにバッフアート弗酸を用い
たウェットエツチングを行なう。浅いコンタクトホール
形成部分16では、現像後もフォトレジスト残り17が
存在するため、弗酸によるウェットエツチングが進行し
ていない。さらに第1図(e)に示すようにフロン系ガ
スによるドライエツチングを行ない、コンタクトホール
を開口する。−般にドライエツチングは、対フォトレジ
スト選択性がウェットエツチングと比較して非常に低い
ため、浅いコンタクトホール形成部分16に存在するフ
ォトレジスト残り17をエッチオフした後、絶縁膜14
をエッチオフして深さの浅いコンタクトホール19を完
成する。また、深いコンタクトホール形成部分18では
通常通りのドライエツチングが進行し、深さの深いコン
タクトホール20が形成される。最後に第1図(d)に
示すように金属配線材料21を堆積し、金属配線のパタ
ーニングを行う。
Next, as shown in FIG. 1(b), wet etching is performed using buffered hydrofluoric acid. In the shallow contact hole formation portion 16, the remaining photoresist 17 remains even after development, so that wet etching with hydrofluoric acid has not progressed. Further, as shown in FIG. 1(e), dry etching is performed using a fluorocarbon gas to open a contact hole. - In general, dry etching has a much lower selectivity to photoresist than wet etching, so after etching off the remaining photoresist 17 existing in the shallow contact hole forming portion 16, the insulating film 14 is etched off.
A shallow contact hole 19 is completed by etching off. Further, dry etching proceeds as usual in the deep contact hole forming portion 18, and a deep contact hole 20 is formed. Finally, as shown in FIG. 1(d), a metal wiring material 21 is deposited and the metal wiring is patterned.

発明の効果 以上の実施例から明らかなように本発明によれば、半導
体基板上の絶縁膜に形成された開口部にテーパ形状を有
する深さの深いコンタクトホールと、テーパ形状を有さ
ない深さの浅いコンタクトホールとを少なくとも有する
構成によるので、はとんどテーパ形状を作らず、サイド
エツチングがなく占有面積の小さい深さの浅いコンタク
トホールと開口部にテーパ形状を有する深さの深いコン
タクトホールとを有する超微細な半導体装置およびその
製造方法を提供できる。
Effects of the Invention As is clear from the above embodiments, according to the present invention, a deep contact hole having a tapered shape and a deep contact hole having a non-tapered shape are formed in an opening formed in an insulating film on a semiconductor substrate. Since the structure has at least a shallow contact hole, a tapered shape is rarely created, and there is no side etching, and a shallow contact hole that occupies a small area and a deep contact with a tapered opening are formed. It is possible to provide an ultrafine semiconductor device having holes and a method for manufacturing the same.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(cl)は本発明の一実施例の半導体装
置の製造方法における工程断面図、第2図は従来の半導
体装置の断面図である。 11・・・・・・半導体基板、14・・・・・・層間絶
縁膜(絶縁膜)、19・・・・・・深さの浅いコンタク
トホール、20・・・・・・深さの深いコンタクトホー
ル。 代理人の氏名 弁理士小鍜治明 ほか2名コングクFJ
1−ル 第1図
FIGS. 1A to 1C are cross-sectional views of steps in a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor device. 11... Semiconductor substrate, 14... Interlayer insulating film (insulating film), 19... Shallow contact hole, 20... Deep depth contact hole. Name of agent: Patent attorney Haruaki Ogata and two others Konguk FJ
1-Le Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上の絶縁膜に形成された開口部にテー
パ形状を有する深さの深いコンタクトホールと、テーパ
形状を有さない深さの浅いコンタクトホールとを少なく
とも有することを特徴とする半導体装置。
(1) A semiconductor characterized by having at least a deep contact hole with a tapered shape and a shallow contact hole without a tapered shape in an opening formed in an insulating film on a semiconductor substrate. Device.
(2)半導体基板上の絶縁膜上にフォトレジストパター
ンを形成し、ウェットエッチングした後ドライエッチン
グしてコンタクトホールを形成する工程を含む半導体装
置の製造方法において、前記フォトレジストパターン形
成における深さの浅いコンタクトホール形成部分のフォ
トレジスト膜底部が露光不足となり、その底部のフォト
レジストが現像後も残るようにフォトレジストパターン
の寸法を小さくしてコンタクトホールを形成する工程を
少なくとも含む半導体装置の製造方法。
(2) A method for manufacturing a semiconductor device including a step of forming a photoresist pattern on an insulating film on a semiconductor substrate, performing wet etching and then dry etching to form a contact hole. A method for manufacturing a semiconductor device, which includes at least the step of forming a contact hole by reducing the dimensions of a photoresist pattern so that the bottom of a photoresist film in a shallow contact hole formation portion is underexposed and the photoresist at the bottom remains even after development. .
JP30084790A 1990-11-05 1990-11-05 Semiconductor device and manufacture thereof Pending JPH04171816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30084790A JPH04171816A (en) 1990-11-05 1990-11-05 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30084790A JPH04171816A (en) 1990-11-05 1990-11-05 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH04171816A true JPH04171816A (en) 1992-06-19

Family

ID=17889836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30084790A Pending JPH04171816A (en) 1990-11-05 1990-11-05 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH04171816A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196568A (en) * 1992-12-25 1994-07-15 Mitsubishi Electric Corp Fabrication of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196568A (en) * 1992-12-25 1994-07-15 Mitsubishi Electric Corp Fabrication of semiconductor device

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