JPH04171552A - Microcomputer containing p-rom - Google Patents

Abstract

PURPOSE:To protect the program data stored in a P-ROM and to secure the secrecy of software to the outsiders by inhibiting selectively the verifying function of the P-ROM with use of the data stored in a specific memory cell. CONSTITUTION:A P-ROM 1 is set in a program mode and a bus changeover switch A10 is switched. Thus the customer program data are written into the P-ROM 1 via program data input/output port 9. Then the prescribed specific data is written into a specific memory cell 2 of the P-ROM 1. The cell 2 is addressed and read out by an address qualifying circuit 4 only when a P-ROM mode decoder 7 is set in an inhibition state and then decoded by an instruction decoder 6. Thus a latch signal 16 of a latch circuit 11 is obtained. In other words, the circuit 11 holds an inhibition signal as long as the specific data is written in the cell 2. Thus the secrecy of the data stored in the P-ROM 1 can be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer with a built-in P-ROM.

[Conventional technology]

Normally, a microcomputer with a built-in P-ROM has a P-ROM.
- Program data input/output port and P-ROM for storing P-ROM program data or inputting/outputting stored program data in order to write and verify program data by a ROM writer
It is equipped with a P-ROM mode setting port for setting the program mode.

Figure 4 shows a conventional P-ROM with the above-mentioned functions.
FIG. 2 is a block diagram schematically showing the basic configuration of a P-ROM and its peripheral circuits installed in a built-in microcomputer. In the figure, the P'-ROM 1 has program data addressed by an address decoder 3 connected to an instruction decoder 6 and a program data input/output port 9 via a bus changeover switch AIO.
The output of the program counter 5 which generates P-ROM address information is input to the address decoder 3.

Further, the P-ROM mode setting port 8 is connected to the P-ROM mode decoder 7.
is write signal PGM or program verify signal V
Generates P-ROM control signals such as ER.

P-RO built into such a microcomputer
By inputting data to the P-ROM mode setting port 8, the M14 switches the bus changeover switch 10, and the M14 inputs data to the P-ROM mode setting port 8.
It is configured to be able to input or output data to the OM.

[Problem to be solved by the invention]

As described above, in this type of conventional microcomputer, data stored in the P-ROM can be easily input/output by switching the mode. However, due to this convenience in handling,
By setting the operation mode to verify mode using the P-ROM writer, a third party can easily read the program data stored in the P-ROM. Therefore, there is a problem in that security protection for data stored in the P-ROM is incomplete.

An object of the present invention is to provide a microcomputer with a built-in P'-ROM that maintains the confidentiality of data stored in the P'-ROM.

[Means to solve the problem]

The P-ROM built-in microcomputer of the present invention has a P-ROM built-in microcomputer.
A ROM circuit, a program data input/output port for writing to the P'-ROM circuit and verify processing, and a P-ROM mode setting port for setting a program mode of the P-ROM circuit. P-R
In the microcomputer with built-in OM, the P-RO
P in response to data input from the M mode setting port
- a P-ROM mode decoder that outputs a ROM mode control signal; a latch circuit that stores an inhibit signal among the P'-ROM mode decoder output signals;
- an address generation means for addressing the ROM circuit; an address modification circuit for inputting the address generation means output signal and modifying the P-ROM address signal by the latch circuit output signal; and a predetermined memory cell allocated to control the latch circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing a specific example of the configuration of a P-ROM and its peripheral circuits in a microcomputer with a built-in P-ROM according to the present invention.

First, the configuration will be explained. In Figure 1, P-ROM
1 has a specific memory cell section 2 and an address decoder 3.
The program data addressed by is connected to the instruction decoder 6 and the program data input/output port via the bus changeover switch AIO.

The output of the program counter 5 that generates address information of the P'-ROM is input to an address modification circuit 4, and the output of the address modification circuit 4 is input to the address decoder 3. On the other hand, the P-ROM mode setting port 8 for setting the program mode of the P-ROM is connected to the P-ROM mode decoder 7.
is the write signal PGM or program verify signal V
Generates P-ROM control signals such as ER. A write signal PGM and a program verify signal VER are input to the NOR circuit 12, and a program inhibit signal INH, which is a program inhibit signal, is generated. Further, the output of the NOR circuit 12 is input to the latch circuit 11, and the output thereof is input to the address modification circuit.

Also, one specific one of the control signals output from the instruction decoder 6 is used as a latch control signal for the latch circuit 11. Note that the address modification circuit 4 is a program counter 5.
A logical OR signal of the output of the latch circuit 11 and the latch circuit 11 is output.

Next, the P-ROM built-in microcomputer is
The procedure for verifying with the writer device will be explained.

Figure 2 shows the microcomputer with built-in P-ROM.
The normal flow when verifying with the OM writer device is shown. First, in order to initialize the program counter, set the 0 clear mode. Thereafter, the program enters the program verify mode via the program inhibit mode to prevent erroneous generation of the P-ROM mode signal.

By incrementing the program counter one by one in this mode, checking of the program data in all the customer P-ROM areas is completed. Thereafter, the verify operation is completed via the program inhibit mode and the P-ROM address O clear mode.

Next, the actual operation will be explained. First, the P-ROM mode is set to the program mode, and by switching the bus changeover switch AIO, customer program data is written into the P-ROMI via the program data input/output port 9. After evaluating the written program, the P-ROM
Predetermined specific data is written into a specific memory cell 2 within 1. Note that this specific memory cell 2 is addressed and read by the address modification circuit 4 only when the P'-ROM mode decoder 7 is in the inhibited state. This read data is decoded by the instruction decoder 6 and becomes a latch signal 17 of latch times Nll.

That is, if specific data is written to a predetermined memory cell 2 in the program inhibit mode by this operation, the latch circuit 11 suspends the inhibit signal according to this data, so that the P-ROM mode is switched from then on. However, the address is fixed by the address modification circuit 4. Therefore, verify operation becomes virtually impossible.

FIG. 3 is a block diagram showing the structure of another embodiment of the P-ROM built-in microcomputer according to the present invention. P-ROM built into the microcomputer of this embodiment
has the same configuration as the embodiment shown in FIG. 1, except for the address data input port 18 for inputting the P-ROM address from the outside, and the changeover switch B between the program counter 5 and the address data input port 18. are doing.

In this embodiment, in the P-ROM write mode or verify mode, the program counter is turned off by the bus changeover switch B17, and the program address of the P-ROM is inserted from the outside through the address data input port 18. It is. The basic operation is the same as the first embodiment.

That is, in the inhibit mode, by referring to the data stored in the specific memory cell unit 2 and suspending the inhibit signal depending on the state, it is possible to fix the address data and virtually prohibit subsequent verification. .

〔Effect of the invention〕

As described above, the P'-ROM built-in microcomputer according to the present invention can selectively inhibit the P-ROM verify function based on data stored in a specific memory cell. Therefore, the program data stored in the P-ROM can be protected, and the confidentiality of the software can be maintained from third parties.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing a specific flow of program verification by a P-ROM writer, and FIG. 3 is a block diagram showing another embodiment of the present invention. FIG. 4 is a block diagram showing a conventional example. 1...P-ROM, 2...Specific memory cell section, 3.
...Address decoder, 4...Address modification circuit, 5
...Program counter, 6.Instruction decoder, 7..P-ROM mode decoder, 8.
・P-ROM mode setting port, 9...Program data input/output port, 10...Bus selection switch A
, 11...Latch circuit, 12...NOR circuit, 1B
, 14.15...OR circuit, 16...Latch control signal, 17...Bus changeover switch B, 18...Address data input port.

Claims (1)

[Claims] A P-ROM circuit, a program data input/output port for writing and verifying the P-ROM circuit, and a P-ROM mode setting port for setting the program mode of the P-ROM circuit. TaP-
In the microcomputer with a built-in ROM, the P-R
a P-ROM mode decoder that outputs a P-ROM mode control signal in response to data input from an OM mode setting port; a latch circuit that stores an inhibit signal among the P-ROM mode decoder output signals;
- an address generation means for addressing the ROM circuit; an address modification circuit for inputting the address generation means output signal and modifying the P-ROM address signal by the latch circuit output signal; A microcomputer with a built-in P-ROM, comprising a predetermined memory cell allocated to control the latch circuit.