JPH04170033A - Field effect transistor - Google Patents

Abstract

PURPOSE:To avoid a break in an ohmic electrode due to a step for reducing a resistance between a gate and a source while increasing a drain reverse strength between the gate and a drain by developing a semiconductor layer selectively in the source and drain regions in nearly the same height with a gate electrode. CONSTITUTION:The n<+> GaAs 5-1, 5-2 is selectively developed in source and drain regions. At that time, the thickness of the n<+> GaAs should be smaller than that of an SiO2 film 4 so that the n<+> GaAs may not be brought into direct contact with a gate electrode 3. As a result, a step between the n<+> GaAs 5-1, 5-2 and SiO2 film 4 and a step between the SiO2 film 4 and gate electrode 3 are remarkably alleviated as compared with the thickness of the gate electrode 3. With the SiO2 film 4, a side wall, remained as it is, a resist pattern 6 having an opening which is extended onto the gate electrode 3 and an opening part which is independently formed on the drain region is formed, and AuGe allay 7 is deposited as metal for an ohmic electrode. Consequently, there is no break in the ohmic electrode due to a step and thus a resistance between the gate and source is reduced while a reverse strength between the gate and drain is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a field effect transistor, and particularly to the structure of its ohmic electrode.

(Prior art) Field-effect transistors (hereinafter referred to as FETs) are voltage-controlled devices, and because almost no input current flows, they have high input impedance and low noise, so they are used in ICs and LS.
It is frequently used in I, etc. Especially G, which is a compound semiconductor
Schottky junction gate type FET with aAs substrate
MESFETs (hereinafter referred to as MESFETs) are attracting attention as basic elements for LSIs and the like that enable ultra-high-speed operation that cannot be achieved with integrated circuits using silicon due to the high electron mobility of GaAs.

When realizing an integrated circuit using a GaAs FET, there are many cases where the gate and source of the FET are short-circuited and used as a constant current source, as shown in FIG. FIG. 13 shows this mask pattern layout, and the FE
A generally known method is to extend the gate electrode 3 from the active layer 2 of the T and make a contact 9 with the wiring metal 8 for connection to the ohmic electrode 7-1 which becomes the source outside the active layer. . However, this connection is essentially unnecessary for FET operation. Moreover, the width of this part cannot be changed even if the width of the active layer is reduced, and as a result, F
The ratio of ET to the occupied area has become relatively large, which is a factor that hinders high integration.

When a GaAs substrate is used, AuGe-based metal is mainly used for making ohmic contact. That is, by heat-treating both at a high temperature of about 400° C., an alloying reaction with the substrate occurs to establish ohmic contact. For this reason, if ohmic metal is formed in the stepped portion, the ohmic metal may self-condense during the heat treatment for alloying or the subsequent wiring process, resulting in step breakage. There is. for that,
The structure is as shown above. This is because the processed shape of the gate electrode is generally vertical or nearly vertical, and the steps on the side surfaces thereof are steep. On the other hand, the processed shape of the gate electrode is different from that of the FET because in the normal self-line FET process, the gate electrode itself is used as a mask during ion implantation.
There are conflicting demands such as verticality being desirable in order to precisely suppress characteristics.

In order to solve this problem, a method is known in which the processed shape of the gate metal is partially tapered.

However, with this method, it is necessary to add a special processing process to make the gate metal into a tapered shape in order to control the processing shape, and the manufacturing cost increases due to the increase in the number of processes.
Decrease in yield becomes a major problem. In addition, when one side of the gate electrode is used for connection with an ohmic electrode and the other edge is formed so as to be in contact with the active region of the FET, make sure that the tapered part does not reach the opposite edge. Since it is necessary to take a long margin, it cannot be applied to FETs with a gate length of approximately 0.5 to 0.8 μm, which are currently commonly used, and the gate length must be increased.

In order to have the same current capacity, the gate width must be increased in proportion to the gate length, and as a result, miniaturization becomes difficult.

On the other hand, in recent years, semiconductor devices such as ICs and LSIs have been becoming more highly integrated and have higher performance, and in response, the gate length has been shortened to improve the performance of GaAs MESFETs, which are the basic elements of these devices. There is.

However, as the performance of FETs increases, the gate
Deterioration of FET characteristics caused by source-to-source resistance becomes apparent.

In order to prevent this deterioration, a method has been considered in which an ohmic electrode is formed with a self-line to the gate electrode.
In this method, the source/drain electrodes are formed symmetrically with respect to the gate electrode, so even though the resistance between the gate and source is reduced, the reverse breakdown voltage between the gate and drain is also reduced at the same time. Channel effects are also more likely to occur.

Additionally, a method of forming an ohmic self-alignment line using a gate electrode with a T-shaped cross section is also known, but when this method is used, ions cannot be implanted under the eave-shaped part of the T-shaped electrode. This makes it impossible to form an FET with an LDD structure.

(Problems to be Solved by the Invention) As described above, in the conventional technology, it is necessary to add a large number of steps in order to directly connect the gate electrode of the FET and the ohmic electrode without interruption, which reduces cost and yield. This was a big problem. Furthermore, due to the miniaturization of elements as the performance of semiconductor devices increases, even if an ohmic electrode is formed with an ohmic self-alignment line in a conventional FET, the reverse withstand voltage between the gate and drain decreases and the L
There was a problem that a DD structure FET could not be formed.

The present invention has been made in view of the above circumstances, and the ohmic electrode can be formed without fear of breakage, and the distance between the gate and source can be made shorter than before without causing a decrease in the reverse withstand voltage between the gate and drain. It is an object of the present invention to provide a field effect transistor equipped with an electrode having a structure that allows for.

[Structure of the Invention] (Means for Solving the Problems) The present invention relates to a field effect transistor in which a gate electrode, a source/drain region, and an ohmic electrode are formed in the source/drain region on a semiconductor substrate, and A first feature is that one of the ohmic electrodes extends above the gate electrode so as to partially cover the gate electrode in the active layer. Further, on the semiconductor substrate, a semiconductor layer which becomes a source/drain region is formed in contact with the gate electrode or with an insulating film interposed between the gate electrode, and one of the semiconductor layers is formed with the gate electrode. The second feature is that an ohmic electrode is provided in electrical contact with each other, and further, the ohmic electrode in the source region extending to the gate electrode so as to partially cover the gate electrode and the gate electrode are provided. An insulating film is interposed between them, and both are characterized in that they are electrically insulated from each other.

(Function) Due to the presence of the semiconductor layer serving as the source/drain region, the surface heights of the semiconductor layer and the gate electrode become approximately the same. Since an ohmic electrode is formed on top of this, its surface becomes flat. As a result, step breakage caused by self-condensation does not occur during the heat treatment for alloying or the subsequent heat treatment in the wiring process, and a highly reliable field effect transistor can be obtained with a high yield.

In addition, since the source electrode, which is an ohmic electrode in the source region, is formed so as to overlap the gate electrode through the insulating film, the distance between the gate electrode and the source electrode is only the side wall length of the insulating film, and this distance is The gate-source resistance is reduced as the length becomes shorter. However, at this time, since the drain electrode, which is an ohmic electrode in the drain region, can be formed apart from the gate electrode, the reverse breakdown voltage between the gate and the drain can be improved depending on the distance. Furthermore, since the gate electrode and the drain electrode are sufficiently formed, the influence of the drain voltage on the potential under the gate is reduced, and as a result, the short channel effect is suppressed.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Example 1 FIGS. 1(a) to 1(e) show a first example of the method for manufacturing a MESFET according to the present invention.

An n-type active layer 2 is formed on the surface of a semi-insulating GaAs substrate 1 by implanting Si ions, and a gate electrode 3 made of tungsten silicide WSix is formed on the surface to a thickness of 5000 angstroms (hereinafter abbreviated as A). (Figure 1(a)).

After depositing an insulating film 5 in 2 film 4 to a thickness of 4500A over the entire surface, a resist pattern (not shown) having openings in the portion including the source/drain region and the FET operating layer is formed, and an anisotropic process such as RIE is performed. By etching the 5in2 film using an etching method, the 5in2 film 4 is left on the side wall of the gate electrode. At this time, the width of the 5in2 film formed on the sidewall is approximately 3000A. At this time, it is desirable to perform etching of the 5in2 film until the gate electrode is completely exposed, and in this example, over-etching is performed so that the top of the 5in2 film is approximately 500A lower than the upper surface of the gate electrode. (Figure 1(b)) Continue with S
Using the r02 film 4 and the gate electrode 3 as masks, n'GaAs5-1.5-
2 is selectively grown on the source/drain regions. At this time, the thickness of the n'' GaAs needs to be thinner than the 5iO7 film 4 formed on the side wall of the gate electrode 3 so that the n' GaAs does not come into direct contact with the gate electrode 3. ) OA.

As a result, the step difference between the n' GaAs5-1.5-2 and the 5tO7 film 4 is about 500A, the step difference between the SiO2 film 4 and the gate electrode 3 is also about 500A, and the thickness of the gate electrode is 5 [100A]. (Fig. 1)
C)).

After this, while leaving the sidewalls of the St2 film 4, a resist pattern is formed that has an opening extending to the gate electrode 3 on the n''GaAs 5-1 in the source region and an independent opening on the drain region. 6 is formed, and an AuG″e alloy 7 is deposited as an ohmic electrode metal to a thickness of 2(IQA).At this time, as mentioned above, the step between the n″GaAs and the gate electrode is significantly reduced. Therefore, a highly reliable connection can be obtained without the ohmic electrode being broken or the metal film becoming thinner at the stepped portion (FIG. 1(d)).

By removing the resist, unnecessary parts of the ohmic metal are lifted off, and by heat treatment at 400'C and alloying, ohmic contact is made between AuGe and GaAs, and the source electrode 7-1 and drain electrode 7-
2 is formed, and the GaAs MESFET according to this example is completed (FIG. 1(e)).

Example 2 FIGS. 2(a) to 2(c) show Ga of the second example of the present invention.
It is a process sectional view of AsMESFET.

An n-type active layer 2 is formed on the surface of a semi-insulating GaAs substrate 1 by Si ion implantation, and a gate electrode 3 made of tungsten silicide W S 1 x is formed on the surface to a thickness of 50 GO.
Form into A. 45 (1 (I)
After depositing to a thickness of A, the source/drain regions and FET
A resist pattern (
) and etching the 5in2 film using an anisotropic etching method to form a 5i film on the side wall of the gate electrode 3.
The structure is the same as Example 1 shown in FIG. 1 up to the point where the n2 film 4 is left (see FIG. 1(b)).

Next, a resist pattern 6 having an opening in the source region and covering the drain region is formed, and using this as a mask, only the gate sidewall 5in2 film 4 on the source side is selectively removed (FIG. 2(a)). .

Subsequently, using the 5in2 film 4 and the gate electrode 3 as masks, an n''GaAs5-1.5-2 film was formed by MOCVD.
is selectively grown in the source and drain regions. n'
The film thickness of GaAs5-1.5-2 is 5 inches on the drain side.
It is necessary to make the thickness smaller than the thickness of the 5 inch 2 film 4 so that it does not cross over the side wall of the 2 film 4 and come into contact with the gate electrode 3.

In this example, the height of the SiO2 film 4 is 4501]A
The film thickness of n′″GaAs5-1.5-2 is 400
1] It was set as A. As a result, n″GaAs in the source region
5-1 is in contact with the gate 3, and the drain region is n'Ga
As5-2 is formed so as to be separated from the gate electrode 3 by the sidewalls of the S102 film 4. In addition, the gate electrode 3 and n”
The step difference in GaAs is 10HA, which is relaxed to 115 for the film thickness of the gate electrode 3 of 5000A (Fig. 2(b)).
).

After this, the source side is made of n″GaAs5-1 and the gate electrode 3.
The drain side is made of n”GaAs5 so as to span both of the
-2, AuGe with a thickness of 200 OA is formed as an ohmic electrode metal, and alloyed at 1°C for 4[1 film] to form a source electrode 7-1 and a drain electrode 7-2.
2 to complete the MESFET (Figure 2 (C)
).

Example 3 FIGS. 3(a) to 3(f) show Ga of the third example of the present invention.
It is a process sectional view of AsMESFET.

An n-type active layer 2 is formed on the surface of a semi-insulating GaAs substrate 1 by implanting Si ions, and a laminated layer consisting of a 2000A thick tungsten silicide WSix 31 and a 3000A thick insulating film (SiN) 3-2 is formed on the surface of the semi-insulating GaAs substrate 1. A structure is formed (FIG. 3(a)).

After depositing an insulating film (SiOz) 4 on the entire surface to a thickness of 4500 Å, a resist pattern (not shown) having openings in the portions including the source/drain regions and the FET operating layer is formed, and an anisotropic process such as RIE is performed. By etching the 8102 film using a chemical etching method, a 5-inch layer is etched on the side wall of the gate electrode 3.
2 films 4 are left (FIG. 3(b)).

Next, a resist pattern 6 having an opening in the source region and covering the drain region is formed, and using this as a mask, only the 5in2 film 4, which is the gate sidewall on the source side, is selectively removed using an ammonium fluoride solution. Subsequently, the SiN film 3-2 on the gate electrode was subjected to CDE (Chemical Dr7 Etchi) using a mixed gas of CF4 and 02.
selectively removed by a dry etching method such as ng). As a result, there is a 5 inch gap only on the drain side of the gate electrode 3-1.
A structure having two membrane sidewalls is formed (FIG. 3(C)).

Subsequently, using the 5i02 film 4 and the gate electrode 3-1 as a mask, n''GaAs5-1.5 is deposited by MOCVD.
-2 is selectively grown in the source/drain regions. At this time, the film thickness of the n''GaAs5-1°5-2 is set to be thinner than the height of the side walls and thicker than the film thickness of the gate electrode.In this example, the thickness of the gate electrode 3-1 2000
A. For a sidewall height of 4500A, the film thickness of n''GaAs is set to 30 (IOA).As a result, on the drain side, the gate electrode and n''GaAs are separated by the sidewall, and on the source side, n'GaAs is separated from the gate electrode. A shape that rides on the electrode is obtained (FIGS. 3(d) and (e)).

After this, the source side is made of n'GaAs5-1 and the gate electrode 3.
-1, the drain side is n″GaA
2000 as ohmic electrode metal on top of s5-2
AuGe having a thickness of A is formed and alloyed at 400° C. to form a source electrode 7-1 and a drain electrode 7-2 to complete the MESFET (FIG. 3(f)).

Example 4 In this example, as shown in FIG. 4, ohmic electrodes are also formed using self-alignment lines. The side wall 4 formed on the drain side of the gate electrode has a steep side surface on the gate side.

Therefore, when a metal film is deposited from above, a break occurs. Taking advantage of this, a photoresist 6 having openings in all regions of the gate source and drain is formed, and an AuGe alloy is vacuum evaporated to a thickness of 2000A as an ohmic electrode.
A source electrode 7-1 connects between the drain electrode 7-1 and a drain electrode 7-1.
2 is separated at the top of the side wall and formed into an independent shape. The photoresist is then removed.

Example 5 Next, the fifth example is shown in FIGS. 6 and 7 (a) to (c).
). Figure 6 shows the MESF of this example.
It is a sectional view of ET, and FIGS. 7(a) to 7(c) are sectional views of the manufacturing process.

An n-type active layer 2 is formed on a semi-insulating GaAs substrate 1 . On both sides of this operating layer 2, intermediate concentration impurity diffusion layers (hereinafter simply referred to as intermediate concentration layers) 14-1
．． 14-2 is formed, and on both sides thereof, high concentration impurity diffusion layers (hereinafter simply referred to as high concentration layers) 1
5.16 is formed.

For example, tungsten nitride (W
A gate electrode 3 made of N, ) is formed, and the top thereof is covered with an insulating film 10 made of SiO□ or the like.

Further, the side wall is formed of an insulating film 4 made of, for example, 5i02.
are formed, and these insulating films 4. IO completely covers the gate electrode. On this GaAs substrate 1, among the ohmic electrodes, a source electrode 7-1 is formed from above the gate electrode 3 to the high concentration layer 15, and a drain electrode 7-2 is formed apart from the gate electrode 3. . These ohmic electrodes 7-1. 7-2 is
Both are made of a laminate made of AuGe/Au.

Next, the manufacturing process of this GaAs-MESFET will be explained using FIGS. 7(a) to (C).

A resist pattern (not shown) is formed on the GaAs substrate 1, and Si ions are accelerated at a voltage of 25 k e V, for example.

FE by performing ion implantation at a dose of 7×1012/al.
An n-type operating layer 2 of T is formed. After removing this resist pattern, the entire surface of the GaAs substrate 1 is covered with tungsten nitride (
WN) is deposited to a thickness of 3000A, and then a silicon oxide film (SiO□) is deposited to a thickness of approximately 3000A by atmospheric pressure CVD or the like. Thereafter, although not shown, a resist pattern for forming a gate is formed, and dry etching is performed using this resist pattern as a mask to form the gate electrode 3 and the insulating film 10 thereon. Next, a resist pattern (not shown) for forming an intermediate concentration layer is formed, and using the gate electrode 3 and the insulating film 10 as a mask, Si ions are accelerated at a voltage of 5 [IK e V, a dose of 2XIO].
13/a (by performing ion implantation to form an intermediate concentration layer +4-1.
14-2 is formed (FIG. 7(a)).

Next, using the plasma CVD method, a 5iO7 film with a density of 5000
After deposition to an extent of A, etching back is performed to form an insulating film 4 that will become the side walls of the gate electrode. Next, using a resist pattern for forming a high concentration layer, the gate electrode 3 where the sidewall 4 is present is formed.
Using the insulating film 4 as a mask, for example, Si ions are accelerated at a voltage of 81]K e V.

Ion implantation is performed at a dose of 5×10”7cnf to form a high concentration layer 15.+6 (FIG. 7(b)).

Next, this substrate 1 was heated to 800 to 900% in an arsine atmosphere.
Capless annealing is performed at 0°C for about 30 minutes.

Next, a photoresist 6 is formed on the entire surface of the substrate, and on the source region side, an opening is formed between the gate electrode 3 and the insulating film 4.
．． On the drain region side, the resist 6 is patterned so that the opening is located away from the gate electrode 3 so as to partially contain the IO.

After that, AuGe/AU layer 7 which is an ohmic electrode material
A source electrode 7-1 and a drain electrode 7-2 are formed by depositing about 5000 Å of the same (FIG. 7(C)).

After that, the resist 6 and the A on it are removed by lift-off.
After removing the u G e / A u layer 7, the source
400°c1 about 1 for drain electrode 7-1.7-2
After 0 minutes of annealing, the LDD structure MESFET
Complete (Figure 6).

Example 6 In the previous example, a device with an LDD structure was described, but in this example, a device with a normal structure (GaA
The present invention will be described with respect to a sMESFET.

First, as shown in FIG. 8(a), a gate electrode 3 made of tungsten nitrogen (WN) with a thickness of 3000 Å is placed on a GaAs substrate 1, and a normal pressure CVD with a thickness of about 3000 Å is placed on the gate electrode 3 made of tungsten nitrogen (WN).
S 102 N-type F under the insulating film 10 and gate electrode 3
The steps up to the formation of the ET operation layer 2 are the same as in the previous example 5.

Next, an insulating film 4 of 5 in 2 is deposited at a thickness of about 5000 A by plasma CVD and then etched back to form the side walls of the gate electrode.
form. Next, using a resist pattern for forming a high concentration layer and using the gate electrode and insulating film 4 where the sidewalls 4 are present as a mask, Si ions are heated at an acceleration voltage of 80
K e V, dose amount 5X I Q + 3 / an
3, ion implantation is performed to form a high concentration layer 15.degree. 16 (FIG. 8(b)).

Next, this GaAs substrate 1 is placed in an arsine atmosphere (81).
Anneal at 11-9110°C for about 30 minutes. Then,
A resist 6 is applied to the entire surface of the GaAs substrate, and on the source region side, an opening is formed to form a gate electrode 3 and an insulating film 4. l
On the drain region side, the resist 6 is patterned so that the opening is located at a certain distance from the gate electrode so as to partially contain O. After that, A u G e
/Au layer 7 is deposited to a thickness of 5 [1 (IOA) to form a source electrode 7-1 and a drain electrode 7-1 (Fig. 8).
C)). After that, the resist 6 is removed by lift-off,
An ohmic electrode is formed by annealing at 400° C. for 10 minutes.

Embodiment 7 FIG. 9 shows a seventh embodiment of the present invention.
It is a sectional view of ESFET.

First, an n-type FET operating layer 2 is formed on a GaAs substrate 1,
The steps from forming the gate electrode 3 and the 5in2 insulating film IO thereon to forming the insulating film 4 serving as the sidewalls of the gate electrode 3 are carried out under the same conditions as in the previous Example 6. Continuing, SiO
□Using the insulating films 4, 10 and gate electrode 3 as a mask,
By the MO-CVD method using TMG and AsH3 as reaction gases, n''GaAs5-1.5-2 is selectively grown in the source and drain regions.The thickness of this n''GaAs is as follows.
Since it is approximately 4000A, the step difference between the gate portion and the source/drain region is greatly reduced. After that, the gate electrode 3 is covered with an insulating film 4. A gate electrode 3 is placed on the n'GaAs' 5-1 which is the source region in a state where it is completely covered with IO.
A resist pattern having an opening extending upward and an independent opening above the drain region is formed, and a metal containing AuGe is deposited to a thickness of 2000 Å as an ohmic electrode metal. Then, by removing the resist, unnecessary parts of the metal for the ohmic electrode are lifted off, and by heat-treating at 400°C to form an alloy, ohmic contact between AuGe and GaAs is obtained, and the source electrode 7-1 and drain electrode 7-2 to complete the GaAs MESFET. While the source electrode 7-1 extends above the gate electrode 3, the drain electrode 7-2 can be separated from the gate electrode by a sufficient distance to the required distance.
It is possible to reduce the source-to-source resistance, improve the reverse breakdown voltage between the gate and drain, and suppress the short channel effect. In addition, by reducing the level difference, it is possible to prevent level breakage.

FIGS. 1O to 12 are characteristic diagrams for explaining the present invention in detail. Figure 10 shows the value (Id=K (
Vg-Vt h) 2) Gate-source distance (L
s g) Shows dependence. However, the gate-drain distance (L d g) is constant at 1 μm. It can be seen from this figure that the value increases rapidly as Lsg becomes shorter. This is because the gate-source resistance is reduced as Lsg is shortened.

FIG. 11 compares the drain reverse breakdown voltage between the gate and drain with that of a conventional example using an ohmic self-line. It can be seen that the FET of the present invention achieves a breakdown voltage that is more than twice the IOV, whereas in this conventional example, the voltage is about 4V. This is because Ldg is 0.3 μm in the conventional example, whereas Ldg in the present invention is 1 μm.
This is because the distance can be increased.

Further, FIG. 12 shows the dependence of the threshold voltage on the gate length. In the conventional example using ohmic self-line, it is 0.
．． The threshold voltage shifts to the negative side due to the short channel effect from 8 μm, whereas in the present invention, from 0.6 μm, the threshold voltage shifts to the negative side due to the short channel effect.
The short channel effect is suppressed down to μm, indicating that the gate length can be shortened by 25%. This is because the Ldg of the present invention is 1 μm, whereas the Ldg of the conventional example is 0.3 μm, and as the distance becomes longer, the influence of the drain voltage on the potential under the gate electrode is weakened, and therefore the decrease in potential due to the drain voltage is suppressed. , due to the suppression of short channel effects.

Although a GaAs substrate was used in the embodiment, this is just an example, and the present invention can of course be applied to other semiconductors such as Si, Ge, and InP. Furthermore, although we used an n-type semiconductor layer as the source/drain region, in the case of a P-channel FET, a p-type semiconductor layer is used.
Of course, a type semiconductor layer can be used.

In the example, the gate electrode material is tungsten silicide (W
For example, MoSix, TiSi
x, TaSix, WSiN, etc. are also applicable. Further, it is also possible to use other materials for the insulating film, such as Si and N4. The present invention is fully applicable to FETs with a gate length of about 0.5 to 0.8 μm, which are currently commonly used.

[Effects of the Invention] As described above, the present invention provides an FET in which an ohmic electrode extends above the gate electrode.
By selectively growing a highly doped semiconductor layer in the drain region to a height between the gate electrode and the path, the level difference between the two is greatly reduced, and the source region and gate region formed above are directly connected. It is now possible to prevent disconnection of the ohmic electrode, and by covering the gate electrode with an insulating film, it is possible to separate the drain electrode from the gate electrode by the required distance and at the same time bring the source electrode sufficiently close to the gate electrode. Therefore, it is possible to simultaneously reduce the gate-source resistance and improve the drain reverse breakdown voltage between the gate and drain.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) show GaAs of Example 1 of the present invention.
Cross-sectional diagram of MESFET manufacturing process, Figure 2 (a) to (c)
is a cross-sectional view of the manufacturing process of GaAs MESFET of Example 2, and FIGS. 3(a) to 3(f) are GaAs MESFET of Example 3.
FIG. 4 is a cross-sectional view of the manufacturing process of M E S F E T of Example 4.
5 is a connection diagram when the FET is used as a constant current source, FIG. 6 is a sectional view of the ME5FET of Example 5, and FIGS. 7(a) to (C) are examples of the example. 5 MESF
8(a) to 8(c) are cross-sectional views of the manufacturing process of the MESFET of Example 6, and FIG. 9 is a cross-sectional view of the MESFET of Example 7. ~12th
10 is a diagram showing the relationship between the K value and the gate-source distance, and FIG. 11 is a characteristic diagram illustrating the present invention.
FIG. 12 is a diagram showing the relationship between gate-drain current and gate-drain reverse voltage, FIG. 12 is a diagram showing the relationship between threshold voltage and gate length, and FIG. 13 is a diagram showing the pattern of a conventional FET. FIG. 1... GaAs substrate, 2... n-type FET operating layer, 3.3-1... gate electrode, 3-2. 4.10... Insulating film, 5-1.5-2---n' GaAs semiconductor layer, 6...
・Resist, 7... Ohmic electrode material, 7-1... Source electrode, 7-2... Drain electrode, +4-1.14-2... Intermediate concentration layer, 15, 16.
...High concentration layer. (8733) Agent: Yoshiaki Inomata, patent attorney (and others)
1 person) (+2.Cb) 1st round (d) 1st bacterium (a no Cb) 2nd rf! J (αn(b) (C) 3rd I!T Cd) αsuCf) 3rd side $f b times C0-) 7th father CC) 7th vilJ (a-) (b) s'v (C ) Figure 6 Broom qWJ Gate Source Dark Masaru 2# [P? rl] Kaya IO times: To dress> Fake R insect power direction 1 et al. [■] No. //
T! H Gate Chief et al gflL] Kaya! 2 Figure

Claims (3)

[Claims] (1) In a field effect transistor including a gate electrode, a source/drain region, and an ohmic electrode formed on the source/drain region on a semiconductor substrate, one of the ohmic electrodes partially covers the gate electrode in the active layer. A field effect transistor is characterized in that it extends to above the gate electrode. (2) A semiconductor layer that is in contact with a gate electrode or has an insulating film interposed between the gate electrode and an ohmic electrode formed on the semiconductor layer is provided on the semiconductor substrate; The field effect transistor according to claim 1, characterized in that the field effect transistor is a source/drain region. (3) The ohmic electrode in the drain region is spaced apart from the gate electrode, and an insulating film is provided between the ohmic electrode in the source region and the gate electrode that partially covers the gate electrode. It is intervening,
2. The field effect transistor according to claim 1, wherein both are electrically insulated from each other.