JPH04170027A - Dry etching - Google Patents

Abstract

PURPOSE:To increase a productivity, controllability, stability, etc., of etching of a silicon oxide material layer by performing etching, setting such conditions that the etching speed of an organic polymer film might be equal to that of the silicon oxide material layer. CONSTITUTION:When isostatic etching is performed for a resist film 5 and layer-to-layer insulated film 4 using C2F3 gas, the layer-to-layer insulated film 4 is made nearly flat. If all the specified etching conditions are met, the etching speed of the resist 5 is made equal to that of the layer-to-layer insulated film 4 simply by optimizing the temperature of an etched substrate within a practical temperature range. In the etching, such an etching gas is used as may contain only one kind of gas which generates a principal etching species and such etching conditions are set that the etching speed of an organic polymer film may be made equal to that of a silicon oxide material layer by controlling the temperature of the etched substrate. Consequently, a rapid etchback is performed especially for the silicon oxide material layer with good controllability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dry etching method, and more particularly to a method for etching back a silicon oxide material layer at high speed and with good controllability.

[Summary of the invention]

The present invention provides a dry etching method in which the surface of a substrate is first substantially flattened with an organic polymer film and then etched back in order to planarize a silicon oxide material layer having steps. using an etching gas, especially a gas containing at least carbon and hydrogen as constituent elements, and achieving conditions for uniform etching of the organic polymer film and the silicon oxide material layer only by controlling the temperature of the substrate to be etched. Increase productivity.

The aim is to significantly improve controllability, stability, etc.

[Conventional technology]

VLS 1. As semiconductor devices become more highly integrated and densely packed, as seen in ULS I, the proportion of wiring on device chips tends to increase. In order to prevent this, multilayer wiring is progressing. Here, the wiring layer cannot be made excessively thin because of the need to maintain low resistance, and the aspect ratio of the wiring layer tends to increase. On the other hand, the glabellar insulating film for insulating each wiring layer cannot be formed too thin from the viewpoint of keeping the capacitance between the wiring layers as small as possible. Therefore, on the device chip, the reduction in three dimensions is delayed compared to the reduction in two dimensions, and the surface level difference of the substrate tends to increase. Such an increase in surface steps leads to deterioration of pattern resolution in lithography, and therefore, in recent years, planarization technology, particularly interlayer insulating film planarization technology, has become increasingly important.

Various methods are known for planarizing interlayer insulating films, but one widely used method is to apply a resist material, etc. to substantially planarize the substrate surface, and then perform etchback. . - For example, conventional etchback for planarizing an interlayer dielectric film made of silicon oxide is generally performed using batch RIE (reactive ion etching).
CF using etching) equipment, 10. system, CHF
, 10f system, CF = / CHF s / A r
This is done using a mixed gas system such as a gas system. For example, in Japanese Patent Application Laid-open No. 61-220334, a photoresist material such as novolac or phenol is applied on an interlayer insulating film having steps, and after causing a Wagner-Meyer-Wein transition by irradiation with ultraviolet rays, heat treatment is applied. The surface of the photoresist material layer is planarized and then CHF l
/ O! A technique has been disclosed in which a photoresist material layer and an interlayer insulating film are etched at a uniform rate using a series etching gas. Generally, uniform etching conditions in such a mixed gas system are achieved by adjusting the flow rate ratio of each component gas to be supplied.

[Problem to be solved by the invention]

However, due to higher integration, the area of device chips has expanded and the diameter of wafers has become larger, while the patterns to be formed have become smaller, so batch-type RIE equipment has become problematic due to lack of uniformity within the wafer surface. It's here. Therefore,
The mainstream of dry etching equipment is about to shift from the conventional batch type to the single wafer type. However, in this case, in order to maintain the same productivity as before, it is essential to significantly improve the etching speed. Furthermore, in the mixed gas system as described above, the conditions tend to become unstable as the number of treatments increases, so from the viewpoint of ensuring process stability and controllability, it is desirable to employ a simple gas system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dry etching method that solves the above-mentioned problems and can flatten a silicon oxide material layer such as a glabellar insulating film at high speed using a simple gas system.

[Means to solve the problem]

The inventor of the present invention has conducted studies focusing on the differences in the etching reaction mechanism between organic polymeric materials such as photoresists and silicon oxide, and as a result, has determined that the gas force q that generates the main etching species (main etchant) Even so, the present inventors have discovered that once predetermined etching conditions are met, uniform etching conditions can be achieved simply by controlling the temperature of the substrate to be etched, and this has led to the completion of the present invention.

That is, the dry etching method according to the first aspect of the present invention involves etching back a substrate on which a substantially flat organic polymer film is formed by covering a silicon oxide material layer having steps. A method for planarizing a material layer, wherein the etchback is performed by using an etching gas containing only one type of gas that generates the main etching species and by controlling the temperature of the substrate to be etched. The etching is performed under conditions such that the etching rate of the silicon oxide-based material layer and the etching rate of the silicon oxide-based material layer are the same.

The dry etching method according to the second invention of the present invention includes:
The present invention is characterized in that a gas containing at least carbon and fluorine as constituent elements is used as the gas for generating the main etching species.

[Effect]

Etching of organic polymeric materials such as photoresists mainly proceeds in radical mode. In other words, since this process is a chemical reaction, if the substrate to be etched is cooled and the temperature of the reaction system near the substrate is lowered, the movement of radicals is suppressed and the etching rate is reduced. On the other hand, since etching of silicon oxide-based materials proceeds through a physical process mainly consisting of sputtering by ions, the decrease in etching rate due to cooling is not as noticeable for resist materials or silicon-based materials. As described above, since there is a difference in the temperature dependence of the etching rate between organic polymer materials and silicon oxide materials, once the predetermined etching conditions are met, the temperature of the substrate to be etched can be optimized within a practical temperature range. By simply using this method, we can find the point where the etching speeds of both of them become equal. The first aspect of the present invention is based on this idea, and has the advantage that an etching gas having a substantially single composition can be used.

The second aspect of the present invention provides the first aspect as a practical process by using a gas containing at least carbon and fluorine as constituent elements as the gas for generating the main etching species. When such a gas dissociates in the plasma, it becomes F.

Etching species such as () fluorine radicals), CF, and (especially CF) ions are generated, and the former mainly contributes to the etching of the organic polymer film, and the latter mainly contributes to the etching of the silicon oxide-based material layer. .

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

First, before applying the present invention to an actual process, as a preliminary experiment, the temperature dependence of the etching rate of a silicon oxide layer and an organic polymer film was investigated.

That is, a sample wafer in which a silicon oxide layer was formed by CvD on a 5-inch diameter silicon substrate, and a novolak-based positive photoresist material (product name 0F).
A sample wafer on which a resist film was formed using PR-800 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was prepared, and C, F, gas (fluorocarbon 2I8) was performed, and changes in etching rate due to changes in wafer temperature were investigated. Here, the wafer temperature is controlled by connecting a chiller using ethanol refrigerant to the etching equipment mentioned above to cool the wafer-installed electrode, and the temperature is measured using fluorescent light from the back side of the sample wafer so as not to be affected by the plasma. This was done by contacting with a fiber thermometer. The etching conditions were C2F, flow rate 46 SCCM, and gas pressure 10 mTorr (= 1.3 Pa).

Microwave power 850W, RF bias power 10
It was set to 0 W (2 MHz).

The results are shown in Figure 1. In the figure, the vertical axis is the etching rate (n
m/min), the horizontal axis represents the wafer temperature ('C), and the black circle (・
) The plot with white circles (0) corresponds to the measurement data of the resist film, and the plot with white circles (0) corresponds to the measurement data of the silicon oxide layer. This figure shows that for the resist film where the etching reaction proceeds mainly in the radical mode, the etching rate increases almost linearly as the wafer temperature rises, whereas the etching rate mainly occurs in the ion mode.
It is clear that in the silicon oxide layer where the etching reaction progresses depending on the mode, the influence of temperature tends not to be so pronounced. Furthermore, in addition to this general tendency, in this experiment, the etching rate of the silicon oxide layer and the etching rate of the resist film were close to each other in the temperature range of 180 DEG C. to 20 DEG C. Originally, the etching rate of the silicon oxide layer could be higher if conditions such as the constituent materials of the device were different, so the etching rates of the two do not necessarily approach each other within the above-mentioned temperature range. However, since the etching chamber of the etching apparatus used here is made of quartz, some of the etching species in the silicon oxide layer are consumed on the chamber walls, reducing the overall etching rate. The etching speed has been achieved.

As described above, the temperature range in which the etching rates of the silicon oxide layer and the resist film are equal depends on the equipment and other conditions, and cannot be generally discussed.

However, if these conditions are appropriately selected, uniform etching conditions can be set simply by controlling the temperature of the substrate to be etched. Here, if the ratio of the etching rate of the silicon oxide layer to the etching rate of the photoresist layer is defined as the etching selectivity, in the example shown in FIG. 1, it is 0.75 at 20°C and 1.0 at -45°C.
, a value of 1.1 was obtained at -80°C. In other words, -
This means that uniform etching conditions are established at 45°C.

Next, an example in which the present invention is actually applied to a manufacturing process of a semiconductor device will be described with reference to FIGS. 2(A) to 2(C).

First, as shown in FIG. 2(A), a wiring layer (3) made of polycrystalline silicon or the like is formed on a semiconductor substrate (1) made of silicon or the like with an insulating oxide film (2) interposed therebetween. An interlayer insulating film (4) made of silicon oxide was formed on the entire surface by a method such as CVD. At this time, the above interlayer insulating film (
Steps were formed on the surface of 4) reflecting the formation pattern of the wiring layer (3).

Furthermore, the above-mentioned novolac positive type photoresist material, for example, was applied to the entire surface of the substrate to form a substantially flat resist film (5) as shown in FIG. 2(B).

Next, in the same manner as in the preliminary experiment described above, the resist film (5) and the interlayer insulating film (4) were etched at a constant rate using C, F, and gas, as shown in FIG. 2(C). As can be seen, the interlayer insulating film (4) was almost flattened.

In the above example, C and F were used as gases containing at least C and F as constituent elements, but in the present invention, other gases such as CF, C, Fl, C, and Fl are also used. Saturated fluorocarbon compounds such as ClF3. CtFt.

Unsaturated fluorocarbon compounds such as C5Fs, C5Fs, C4F@, CaFs, CaFa, etc., or compounds such as CHF containing H as a constituent element in addition to C and F may be used. Among them, the number of C atoms is 2 or more, it is possible to generate 2 or more CFr ions from one molecule, and the F/C ratio is 2 or more, so it is possible to efficiently generate a relatively large number of F9. It is particularly preferable to use a higher-order fluorocarbon gas from the viewpoint of increasing the etching rate.

Furthermore, O, gas, N, gas, etc. may be added to the above-mentioned gas system in order to control the etching rate.
A rare gas such as e, Ar, etc. may be added as appropriate.

The silicon oxide-based material layer to be planarized in the present invention is not limited to the above-mentioned silicon oxide, but includes PSG, BSG,
BPSG, As5G, AsPSG.

It may also be AsBSG or the like.

Furthermore, the present invention is applicable not only to planarization of interlayer insulating films, but also to etch-back for flattening trenches for element isolation formed in a silicon substrate with a silicon oxide deposited film in trench isolation technology, for example. be able to.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even if an etching gas having a substantially single composition is used, the organic polymer film and the silicon oxide material layer can be bonded by controlling the temperature of the substrate to be etched. It becomes possible to achieve uniform etching conditions. Therefore, excellent stability and controllability can be obtained even if the process is repeated many times using a single-wafer dry etching device, which is expected to become mainstream in the future. Therefore, the present invention is extremely effective in manufacturing semiconductor devices with high performance and high degree of integration based on fine design rules.

[Brief explanation of drawings]

Figure 1 shows the etching of the silicon oxide layer and resist film. FIG. FIG. 2(A) to FIG. 2(C) are schematic cross-sectional views illustrating an example of applying the present invention to planarization of an interlayer insulating film according to the process order, and FIG. 2(A) shows a step-like structure. The process of forming an interlayer insulating film, FIG. 2(B) shows the process of planarizing the substrate using a resist film, and FIG. 2(C) shows the process of planarizing the interlayer insulating film by uniformly etching back the resist film and the interlayer insulating film. Represent each. l...Semiconductor substrate 2...Insulating oxide film 3...Wiring layer 4...Interlayer insulating film 5...Resist film Patent applicant Sony Corporation representative Patent attorney Koike Mima Sakae Tamura - Same Masaru Sahara Figure 1

Claims (2)

[Claims] (1) In a dry etching method in which a substrate formed by covering a silicon oxide material layer with steps and a substantially flat organic polymer film is etched back to planarize the silicon oxide material layer, the etch The back is the gas that generates the main etching species.
The method is characterized in that the etching is performed by using an etching gas containing only the different types of etching gas and by controlling the temperature of the substrate to be etched so that the etching rate of the organic polymer film and the silicon oxide material layer are equal. Dry etching method. (2) The dry etching method according to claim 1, wherein the gas that generates the main etching species is a gas containing at least carbon and fluorine as constituent elements.