JPH04168878A - Picture smoothing processing system - Google Patents

Abstract

PURPOSE:To attain smoothing processing in response to the tilt of a slant line without useless preparation of a standard picture element pattern while avoiding complicated circuit constitution by applying individually magnification in the main scanning direction and magnification in the subscanning direction sequentially and applying smoothing processing only at the point of time of the magnification in the subscanning direction to form a final picture. CONSTITUTION:A bit data magnified twice in the main scanning direction is serially inputted to a main scanning reduction circuit 20 from a shift register 15. The data is not subject to interleave processing in the main scanning reduction circuit 20 but stored to a cyclic line buffer circuit 3 as it is serially. A smoothing logic circuit 4 implements smoothing based on a current line data stored in a shift register and main scanning line data information by preceding and succeeding three lines, and a unit division data outputted serially or a serial output from the shift register of the current line is properly selected based on a selection signal from an operation mode register and printed out.

Description

Detailed Description of the Invention "Industrial Application Field" The present invention is applicable to converting pixel density to high resolution, such as when transmitting an image read by a facsimile machine, increasing the resolution, and outputting it on a page printer. The present invention relates to an image smoothing processing method when enlarging an image by increasing the number of pixels.

“Conventional technology” Conventionally, facsimile machines and image scanners have generally used 8
It is read at a pixel density (normal mode) of about dat(line)/mm, and when outputting this with a laser printer or other image printer, it becomes the target of the transmission image in order to match the resolution of the printer. By interpolating a unit pixel with, for example, twice the resolution based on the image information surrounding the pixel of interest, the pixel density of the image data expanded and stored in the printer's video memory can be increased (
A configuration is adopted in which the resolution is increased by enlarging the image to 16 dots/ma+), but with such an interpolation method, the contour line is formed in a step-like manner, and a high-quality image cannot be formed.

Therefore, in conventional devices, in order to eliminate the step-like distortion, a smoothing method has been developed that determines whether to add or delete a unit pixel depending on the direction of the normal to the contour line. Although the smoothing method is effective for diagonal lines with an angle of 45", it has the disadvantage that it has little smoothing effect on diagonal lines whose slope is biased toward the main scanning direction or the sub-scanning direction. vinegar.

In order to eliminate this drawback, the target transmission pixel (
(hereinafter referred to as the pixel of interest) in both the main scanning direction and the sub-scanning direction.
It is divided into 2×2 unit pixels (pixels developed in video memory) with twice the resolution, and the processing content of adding and deleting the unit pixels is divided into the target pixel of interest and the pixels surrounding the pixel of interest. The 2×2 transmission pixel data is 2×2 according to a predetermined standard pattern with reference to 5×3 transmitted pixel data of 5 transmitted pixels in the main scanning direction and 3 transmitted pixels in the sub-scanning direction.
We have proposed an image processing method that enables smoothing processing according to the slope of the diagonal line by simultaneously generating unit pixels in the main scanning direction and sub-scanning direction. (Japanese Unexamined Patent Publication No. 58-114573) "Technical Problems to be Solved by the Invention" However, in the above processing method, since unit pixels in the main scanning direction and sub-scanning direction are generated simultaneously, the circuit configuration becomes complicated and ( (5X3)・(2X2))
It is necessary to prepare only the number of standard pixel patterns corresponding to the required enlargement magnification, and as a result, the memory for storing the pixel patterns becomes large.

In addition, it is difficult to generate unit pixels in the main scanning direction and sub-scanning direction at the same time, for example, when setting the top margin or left margin, it is difficult to bias one side (the magnification in the longitudinal direction and the width direction is different). However, if we try to make this deviation possible, we would have to prepare an infinite number of pixel patterns that would make this possible, which is practically impossible.

In view of the drawbacks of the prior art, the present invention provides a smoothing processing method that makes it possible to perform smoothing processing according to the slope of a diagonal line without complicating the circuit configuration and without needlessly preparing a standard pixel pattern. The purpose is to do.

Another object of the present invention is to easily perform smoothing processing even when the enlargement magnifications in the main scanning direction and sub-scanning direction are set independently, and thereby when setting the top margin and left margin. The object of the present invention is to provide a smoothing processing method that enables bias processing.

It should be noted that the present invention is applicable not only to the above-mentioned image smoothing processing method for achieving high resolution with a pixel density but also for enlarging an image by increasing the number of pixels.

"Technical Means for Solving the Problem" In order to achieve the technical problem, the present invention arranges pixel groups constituting the transmitted image and other original images in the main scanning direction and the sub-scanning direction, as in the prior art. Enlargement magnification (first set magnification: W) without performing enlargement processing and smoothing processing at the same time, and without performing smoothing processing on the main scanning direction side, as shown in Figure 1.
After forming an intermediate enlarged image by directly dividing the target pixel into units according to At the same time as the enlargement process, the unit division signal is set in the smoothing operation described later.In other words, to summarize the present invention, main scanning enlargement and sub-scanning enlargement are sequentially and individually performed, and the sub-scanning direction in which the final image is formed is set. This method is characterized in that smoothing processing is performed only at the point of enlargement.

The smoothing process is performed by referring to the surrounding pixel group including the target pixel to be divided into units in the sub-scanning direction, but since the enlargement process has been performed in the main-scanning direction in advance, the pixel to be referenced The group is not uniformly referenced in the main/sub-scanning directions, but the reference pixels are at least W times (first set magnification) the number of reference pixels in the sub-scanning direction, taking into account the number of pixels enlarged in the main-scanning direction. It is necessary to increase the number.

Therefore, in the present invention, when the number of reference pixels in the sub-scanning direction is n (n+1 pixels including the pixel of interest), the number of reference pixels in the main scanning direction is n+(
m≧Wn+ 1, l11 = m× of pixels (including the pixel of interest)
A second feature of the present invention is that the sub-scanning direction unit division signal of the pixel of interest is set with reference to the (n+1) pixel group.

"Operation" According to this technical means, smoothing processing is performed not on the original image as it is, but on an intermediate image that is divided into units in the main scanning direction and densified in the main scanning direction, and the reference pixel group is densified. Since the number of pixels is increased by a factor of W in the main scanning direction in correspondence with the number of unit pixels, smooth smoothing processing is possible.

In addition, since the present invention suffices with smoothing processing on only one axis in the sub-scanning direction, the circuit configuration is simplified. [(7x
3)x2] or [(9x3)x2] and the prior art [
(5X 3)
Even when smoothing is attempted by increasing the number of pixels, a pixel pattern substantially the same as that of the prior art is sufficient, and efficient smoothing processing becomes possible.

In addition, since the unit pixels in the main scanning direction and the sub-scanning direction are enlarged independently, for example, when setting the top margin or left margin, it is possible to easily shift the enlargement ratio by changing one of the enlargement magnifications. Even in the case of deviation, smoothing processing only needs to be performed in the sub-scanning direction, regardless of enlargement processing in the main-scanning direction, so the number of required standard pixel patterns is not increased unnecessarily and the deviation magnification is limited. Smooth smoothing processing is possible without any problems.

"Embodiments" Hereinafter, embodiments of the present invention will be described in detail by way of example based on the drawings. However, unless otherwise specified, the dimensions, materials, shapes, and relative positions of the components described in this example are not intended to limit the scope of this invention, but are merely illustrative examples. Not too much.

FIG. 2 is an overall block diagram showing an image processing apparatus according to an embodiment of the present invention.The configuration will be briefly explained according to the flow of image signals.The interface unit 1 has a parallel input 17
Fll and a serial input 17F12, which are connected to a main scanning enlargement register via a selector 13 which can be selectively switched based on a signal from, for example, MPU I/FIO.

To briefly explain its configuration based on FIG. 3, the DMA control circuit 18 inputs, for example, image data stored in the system memory 8, which will be described later, in 16-bit increments via a data bus based on a control signal from the DMA control circuit 14. The parallel 1n10ut registers are input in parallel, and 12 is a serial in/parallel out register that serially inputs bit data read from an image reading unit such as a facsimile machine, 16 bits at a time. The 16-bit data is automatically enlarged twice in the main scanning direction (parallel copying) by a logic circuit 13 including a selector function, and inputted to the shift register 15 as 32-bit data.

The bit data expanded in the main scanning direction is serially input from the shift register 15 to the main scanning reduction section 20. Note that 16 is a data control section for controlling the parallel copying.

Since the main scanning reduction unit 20 is not an essential part of the present invention, it will be briefly explained.The 32-bit data that has been unconditionally enlarged by 2 times in the interface unit 1 is thinned out by 0.25 to 1° according to a predetermined specified mode. As a result, the bit data output from the reduction unit 20 can be subjected to 2X (0.25 to 1.0), that is, 0.5 to 2.0 scaling processing on the original image. becomes.

The scaled data is serially stored in the cyclic line buffer circuit 3.

As shown in FIG. 4, the cyclic line buffer circuit 3 has two main scanning lines capable of storing image data for three main scanning lines or more.
KWX has a RAM memory 31 having a memory area of 8 bits, and after serially transferring the scaling data output from the reduction unit 20 to the shift register 32 in 8 bits at a time, it is transferred to the specified address of the RAM memory 31 via the write buffer 33. area, and the RAM memory 3
1, main scanning line data for three lines before and after the current line data are always stored together with the current line data.

The image data stored in the RAM memory 31 is simultaneously serially transferred to the corresponding shift registers 41 to 43 on the smoothing logic circuit 4 side for three lines.

In addition, 34 in the figure is a cyclic line buffer control circuit, 3
5 is a write address designation register for the RAM memory 31; 36A, 36B, and 36C are read address designation registers for reading the same; and 37 is a read/write address switching circuit.

On the other hand, 5 is a sub-scanning enlarging/reducing circuit which controls the output of the cyclic line buffer circuit 3 via the cyclic line buffer control circuit 34, and its output.

Reduction in the sub-scanning direction is achieved by appropriately selecting and outputting the OR output and the unit-divided outputs Xu and XL from the smoothing logic circuit 4 via the output switching circuit 44 based on a selection signal from an operation mode register (not shown). Enlargement magnification can be set arbitrarily.

For example, the operation modes include a normal mode in which enlargement/reduction is realized by repeating or thinning out the image data output from the cyclic line buffer circuit 3 line by line, an OR mode in which logical OR is performed when thinning out the image data,
A smoothing mode that refers to a pixel of interest and pixels in 7×3 or 11×3 lines around it and divides the pixel of interest into two pixels in the sub-scanning direction according to a predetermined standard pattern, and a combination of a quaternary counter and repeated output, When the count value is 0 or ■, the current line data is output as is, and when the count value is 2.3, the current line data is repeatedly output. A 2/3 mode is provided in which when the count value is O12, the current line data is output as is, and when the count value is 1, the current line data is skipped without being output, and by combining these modes, sub-scanning can be performed. The reduction/enlargement in the direction can be arbitrarily set within the range of 0°5 to 4.0 times.

Next, the configuration of the smoothing logic circuit 4 will be explained. The smoothing logic circuit 4 is a circuit used to smooth out the step difference in the shaded area when the sub-scanning enlargement/reduction circuit 5 performs enlargement processing. read buffer 4
Shift registers 41 to 43 store main scanning line data for three lines before and after the current line data in 8 bits each via channels 1a to 43a.
1 to 43 are configured such that (8+11) bits of image data can be registered in correspondence with reference pixel data to be smoothed. and the shift registers 41 to 43
Based on instructions from the control circuit 47, the data stored in the smoothing logic 145A and 7 bits each are input in parallel to the smoothing logic 145A and 7 bits each to the smoothing logic 245B, respectively, and predetermined smoothing processing is performed within the logics 45A and 45B. After that, one of the logic 45A,
The smoothed data generated by 45B is output to the output switching circuit 44 via the smoothing switching circuit based on the selection signal from the MPU I/F.

The output switching circuit 44 appropriately selects the unit divided data serially outputted from the smoothing switching circuit 46 and the serial output from the shift register of the current line based on the selection signal from the operation mode register, and prints out the data.

If the data after the enlargement or reduction processing is not printed out as is, but only the enlargement/reduction processing or smoothing processing is performed, and the printout is to be performed at a later date due to running out of paper, a confidential call, or other reasons, the output switching circuit 44 is used. 1 through the serial signal conversion circuit 7A of
6-bit parallel conversion is performed and the parallel data is input to the system memory 8 via the parallel output 17F7B.

Note that 6B is a circuit that sets the top margin and left margin based on the horizontal synchronization signal and vertical synchronization signal from the engine side of the LBP, and transmits the bias control signal to the sub-scanning enlargement/reduction circuit 5 and the smoothing logic circuit. 9 is 1 of the original image data taken in from the serial input 17F
A line enable signal generation circuit indicating a line, 10 is MP
This is a UI/F generation circuit.

Next, the operation of this embodiment will be explained in relation to the present invention.

First, in order to facilitate understanding of the present invention, the operation when an original image is enlarged twice in the main scanning direction will be explained.

Bit data read by an image reading unit such as a facsimile machine is serially input into the serial in/parallel out register 12 in 16-bit units, and then input into the register 12! The 6-bit data is expanded twice in parallel in the main scanning direction by a logic circuit 13 including a selector function, and then sent to the shift register 15 as 32-bit data.
is input.

The bit data enlarged twice in the main scanning direction is serially input from the shift register 15 to the main scanning reduction circuit 20.

The main scanning reduction circuit 20 stores the data serially in the cyclic line buffer circuit 3 without performing any thinning processing.

In the cyclic line buffer circuit 3, as shown in FIG. 4, after storing image data for three main scanning lines or more in the RAM memory 31, the image data is simultaneously transferred to the corresponding respective lines in the smoothing logic circuit 4. The data is serially transferred to shift registers 41-43.

In the smoothing logic circuit 4, the shift register 41~
Based on the current line data stored in the pixel 43 and the main scanning line data for three lines before and after it, the smoothing logic 245B uses the current line data stored in the pixel of interest and the data of the 7X3 lines around it, and the smoothing logic 145A
, 3 lines of data, the target pixel is divided into two pixels in the sub-scanning direction based on the following logical formula.

QIOQ9 G8 G7 G6 G5 G4
G3 G2 QI QOXu=
ττri4)+Y (F5+F6+F7+F8)XL-X
(+ + + + + )+Y(F1+F2
+F3+F4+F7+F8)E1=nkodingTl1rA'
l B3 B687 C3 (n mouth V B4 C2+ prefecture
Ro88 G4) E2 = Kuko TIr Notification B3 B41117
C7(X7 B6 u C8+X'282 u C6
) E3 = 84 Punishment Near 1 ``a (A6 (feather + C3 + A2
Correction-)+■]rπC3)E4=U B6 STr](A
4(?17+C7+A8 TIF mouth ff)+■Cor notification C
7) Seki = A6 B411! 1 dish (830 (
] "Tomoe + B2 + C2) (Shoulder T7 + C7) + A7 r
Lower (X'J'11'Q+83+C3) (1701
+c8))E6=A4 u B6 ri1rs(B7?
l'7 (flex) "Blood+88+C8) (fflD+c3)
+A3 Dong Seiko (Shoulder) r mouth + B7 + C7) (Ω] To C
2) ) B7-A4 A5 notification B4
83 C20) B8-n A5 A6 u B67 completed
](C7+87 'n C3)F1=Wro IB6C5
(Notification (ko+A7+(B2+f7)
+(111'l+B8)(low r mouth+83 B8] +
A5 A6V] ko) F3-revised B7 C4C5 (It seal B6 C3σ
πB8 C61F4=D B31170117 C5C
6(n B4 u C7+X'2 B2 Ill'!
C4) F5-A5 A6 A7 B3
(A4 B2 π-+A8 B4101) F6-A3
A4 A5 r edition B73's drunken mouth (A6 plate B8 ?2+
A2 HB6) F7=X'K A611i'? ro IB
64C5 (shoulder = mouth + mouth C3) F8-A4 B B4'
trT7 C5C6(H'?7+C7) Then, the unit divided data is outputted to the output switching circuit 44 side via the smoothing switching circuit 46, and the output switching circuit 44 outputs the unit divided data and the shift register 42 of the current line. The serially outputted data is appropriately selected based on the selection signal from the operation mode register, and is serially outputted to the input side of the video memory 6 for data expansion.

"Effects" As described above, the present invention enables smoothing processing according to the slope of the diagonal line while avoiding complication of the circuit configuration and logical formula.

Furthermore, the present invention enables smoothing processing easily even when the enlargement magnifications in the main scanning direction and the sub-scanning direction are set independently.
This has various effects such as enabling biased distribution processing when setting the top margin and left margin.

[Brief explanation of the drawing]

Fig. 1 is a basic configuration diagram of the present invention, Fig. 2 is an overall block diagram of an image processing device according to an embodiment of the present invention, Fig. 3 is a detailed block diagram of the interface section, and Fig. 4 is a cyclic line buffer circuit. FIG. 3 is a detailed block diagram of a smoothing logic circuit.

Claims (1)

[Claims] 1) After forming an intermediate enlarged image by dividing the pixel group constituting the original image into units only in the main scanning direction based on the first setting magnification W, the intermediate enlarged image is divided into the first or second enlarged image. When forming a final enlarged image by dividing into units only in the sub-scanning direction based on the second setting magnification, n+1 pixels (n: even number) in the sub-scanning direction among the pixel group including the pixel of interest to be divided into units. , refer to m×(n+1) pixel group of n (m≧Wn+1, m: odd number) pixels in the main scanning direction, set a unit division signal in the sub-scanning direction of the pixel of interest, and perform smoothing processing. 2) Image smoothing processing method according to claim 1, characterized in that a cyclic buffer is used as a buffer memory for storing the intermediate enlarged image.