JPH0416828B2 - - Google Patents

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to an image processing device.

(Prior Art) As shown in FIG. 14, a conventional image processing device images a subject with a television camera 1, stores the video signal in a frame memory 2, and processes this with a microcomputer 3.

(Problems to be Solved by the Invention) In the above-mentioned image processing device, the video signal of two-dimensional information is stored as it is in the frame memory 2, so even when processing simple figures such as circles and straight lines, 256
It requires a frame memory with a large capacity of 256 bits or 512 x 512 bits and is expensive. Furthermore, since a video signal of two-dimensional information is processed, there is a large amount of processing data. Furthermore, the minimum resolution is limited by the capacity of the frame memory.

(Means for Solving the Problems) The present invention provides a binarization means for obtaining a binarized signal from a video signal, and a binarization means for obtaining a binarized signal from the binarization means by using one of a plurality of different frequency division ratios. a frequency divider that divides the frequency, a frequency division specifying section that selectively specifies the frequency division ratio of the frequency divider, and a signal from the frequency divider that changes from white to black;
and/or a measuring means for measuring the position of transition from black to white, and a storage means for storing the measured value of the position of transition from the measuring means.

(Operation) A binarized signal is obtained from the video signal by the binarization means, and this binarized signal is divided by one of a plurality of mutually different frequency division ratios by the frequency divider. The frequency division ratio of this frequency divider is selectively designated by the frequency division designation section. The position where the signal from the frequency divider shifts from white to black and/or from black to white is measured by the measuring means, and the measured value of the shifted position is stored by the storage means.

(Example) FIG. 1 shows an outline of the present invention, and FIG. 2 is a timing chart thereof.

A television camera images a subject and outputs a video signal, and this video signal is binarized at a reference level by a binarization means to be binarized into a black part and a white part, and the latch pulse generation circuit generates a black part and a white part. 11. This latch pulse generation circuit 11 has two
A pulse is generated by detecting the position where the binarized signal from the digitization means shifts from the white part to the black part and the position where it shifts from the black part to the white part, that is, detects the rising and falling edges of the binarized signal. occurs. On the other hand, the counter 12 receives a vertical synchronization signal (or a similar signal) separated from the video signal from the television camera by the synchronization separation circuit and starts counting the clock, and the reset pulse generation circuit 13 receives the vertical synchronization signal (or similar signal) separated from the video signal from the television camera by the synchronization separation circuit. A reset pulse is generated by a horizontal periodic signal from the counter 12 to reset the counter 12. The latch circuit 14 is the latch panel generator circuit 11.
The contents of the counter 12 are latched and transferred to a random access memory (RAM), etc. by pulses from 12 contents) are transferred to RAM and stored. As a result, the binarized signal is converted from two-dimensional information to one-dimensional information and stored in the RAM, where it is processed by a microcomputer or the like.

Further, the binarized signal from the binarizing means is passed through a frequency divider 15.
By dividing the frequency by and inputting it to the latch panel generation circuit 11, the transposition positions (rising and falling positions) of the binary signal can be selectively extracted according to the frequency division ratio of the frequency divider 15. . This frequency divider 1
5 is a well-known device, for example, one having a plurality of frequency dividing circuits and AND gates is used as described later, and different frequency division ratios are selectively specified by a plurality of frequency division specifying sections.

FIGS. 3a and 3b show an example of a subject and an image (processed image) shown by the output data of the latch circuit 14 when the frequency divider 15 is not provided. In FIG. 3b, the solid line indicates that the latch circuit 14 activates the counter 1 at the rising edge of the binary signal.
This is a processed image using data latched from 2.
The dotted line is a processed image based on data latched by the latch circuit 14 from the counter 12 at the falling edge of the binarized signal.

A, b, and c in FIG. 4 show other examples of the subject and processed images when the frequency divider 15 is provided. Fig. 4b shows the processed image when the frequency divider 15 is set to no frequency division (frequency division ratio 1), and Fig. 4c shows the processing when the frequency division ratio of the frequency divider 15 is set to 1/2. If you show the images and combine them, you get the original image.

FIGS. 5a and 5b show other examples of objects and processed images. The processed image is a composite of the processed image when the frequency divider 15 is set to no frequency division and the processed image when the frequency division ratio of the frequency divider 15 is set to 1/2.
Fig. 6 a and b show other examples of subjects and processed images, in which the frequency division ratio of the frequency divider 15 is set to 1,
A composite image of each processed image when the size is reduced to 1/2 and 1/3 is shown.

Incidentally, instead of the counter 12, a charge circuit may be used to charge the charge, and the amount of charge may be measured by a pulse from the latch pulse generation circuit 11 and stored in a RAM or the like.

FIG. 7 shows an embodiment of a workpiece positioning control device to which the present invention is applied. In this embodiment, a workpiece (workpiece) 16 is positioned at a predetermined regular position with high precision.The workpiece 16 has a simple shape, for example, a circle, and is set on a support stand 17 and placed on a television set. The image is captured by the digital camera 18.
The image processing device 19 binarizes the video signal from the television camera 18, measures the position where this binarized signal shifts from the white level to the black level, and the position where the black level shifts to the white level, and stores the data. It is sent to the microcomputer 20. The microcomputer 20 temporarily stores the data from the image processing device 19 in RAM and processes the X-axis, Y-axis,
Find the rotation angle position information, compare it with the regular position information, and use the result to drive the motor drive circuit 21.
is controlled so that the workpiece 16 moves to the normal position. The motor drive circuit 21 drives the motor 22 to move the support stand 17 in the X-axis direction, drives the motor 23 to move the support stand 17 in the Y-axis direction, and further drives the motor 24 to move the support stand 17. By rotating the workpiece 16, the workpiece 16 is moved to a normal position.

FIG. 8 specifically shows the image processing device 19, and FIG. 9 shows its timing chart.

In this image processing device 19, when the data acquisition request signal ○c is input from the microcomputer 20, the flip-flop 25 is activated by this signal ○c.
is set. A synchronization separation circuit 26 separates a synchronization signal from the video signal from the television camera 18, and an even field vertical synchronization signal is further separated from this synchronization signal by an even field vertical synchronization signal separation circuit 27. This vertical synchronizing signal is passed through the AND gate 28 by the output signal of the flip-flop 25, and is passed through the trigger circuit 2.
9 is set, whereby the output signal of the trigger circuit 29 is applied to the AND gates 30 and 31, and these gates 30 and 31 are opened. Further, the synchronization signal from the synchronization separation circuit 26 is sent to the horizontal synchronization counter 32.
It is counted by Scan area setting circuit 33, 3
4 generates output signals in mutually different scanning areas A and B according to the synchronization signal from the synchronization separation circuit 26, that is, generates an output signal when the video signal is within the scanning areas A and B, for example, each horizontal synchronization It outputs a pulse signal that rises after a certain period of time from the signal and then falls after another certain period of time. Scan area specification flip-flop and clock specification flip-flop 35
is the scan area specification from the microcomputer 20,
Latch clock designation signal ○ho and AND gate 3
By outputting an output signal to one of AND gates 6 and 37, one of the AND gates is opened, and by outputting an output signal to one of AND gates 38 and 39, one of the AND gates is opened. One of the output signals from the scan area setting circuits 33 and 34 is selected by AND gates 36 and 37 and passed through, and is sent to an OR circuit 40. This OR circuit 40
The output signal passes through an AND gate 31 and is applied to measuring means 41, 42 consisting of counters, and the counters 41, 42 count the clocks. The clock from the oscillator 43 is sent directly to the AND gate 3.
8, the frequency is divided by a frequency divider 40, and the signal is sent to an AND gate 39. and gate 38, 39
The scanning area designating flip-flop and the clock designating flip-flop 35 open only one side to pass a clock, and the clock passes through an OR circuit 45 and is counted by counters 41 and 42.

Further, the video signal from the television camera 18 is binarized into black and white parts at a reference level by the binarization circuit 46, and the binarized signal is passed through the AND gate 47 by the output signal of the OR circuit 40. are sent as they are to the AND gate 481, and the frequency division ratios are respectively 1/2, 1/3...1/
n frequency dividing circuits 492 to 49n each have 1/2,
1/3...The frequency is divided into 1/n and sent to AND gates 482 to 48n. Here, frequency divider circuit 4
92 to 49n and AND gates 481 to 48n constitute the frequency divider 15, and one of a plurality of mutually different frequency division ratios is selectively designated by the frequency division designation unit 53. Frequency dividing circuit 492-49
n is a commonly used signal that outputs an output signal with a frequency that is an integer fraction of the input signal frequency, and the binary signal from the AND gate 47 is input as the input signal.

That is, the frequency dividing circuit 492 has a frequency of 1 as shown in FIG.
The binarized signal on the scanning line (data indicating the characteristics of the shape of the workpiece 16) is divided by a frequency division ratio of 1/2 to 2.
The frequency of the value signal is converted to 1/2, and the frequency dividing circuit 4
As shown in FIG. 11, 93 divides the binary signal on one scanning line to a frequency division ratio of 1/3 to convert the frequency of the binary signal to 1/3. Therefore, 2 on one scanning line
Even if there is a transposition point in the value signal, the frequency dividing circuit 49
The output signals of the counters 41 to 49n and the output signals of the AND gates 47 can be selectively taken out by the AND gates 481 to 48n to change the division ratio for the binarized signal on one scanning line.
42 count start position can be changed, which is effective for image processing of somewhat complicated figures.
Moreover, if the frequency division specifying unit 53 is set in advance to selectively specify the frequency division ratio by selectively operating any one of the AND gates 481 to 48n, the required figure can be Only data can be retrieved. Specifically, as shown in FIG. 10, if the output signal of the frequency dividing circuit 492 with a frequency division ratio of 1/2 is taken out by the AND gate 482, the frequency is divided at the second transposition position (rising position) of the binarized signal. The output signal of the circuit 492 can be taken out, as shown in FIG.
1, if the output signal of the frequency divider circuit 493 with a frequency division ratio of 1/3 is taken out by the AND gate 483, the output signal of the frequency divider circuit 493 is obtained at the third transition position (rising position) of the binarized signal. It can be taken out. And gate 48 like this
The output signals selectively taken out by signals 1 to 48n become the count start positions of the counters 41 and 42.
Note that AND gate 481 causes AND gate 4
If an output signal of 7 is taken out, the frequency division ratio for the binarized signal becomes 1, and the first transition position (rising position) of the binarized signal becomes the counting start position of the counters 41 and 42. The frequency division designation section 53 latches the frequency division designation signal ○ from the microcomputer 20, and uses this signal ○ to output the AND gates 481 to 48n.
is selectively opened, and the binary signal from the AND gate is inputted to a positive trigger flip-flop 56 and a negative trigger flip-flop 57 through OR circuits 54 and 55. The positive trigger flip-flop 56 receives the 2 from the OR circuit 55.
It is set at the rising edge of the value conversion signal (the position at which the white level changes for the first time to the black level), and the output signal is sent to the counter 41 as a count stop signal, and the counter 41 is stopped. The negative trigger flip-flop 57 detects the falling edge of the binary signal from the OR circuit 55 (the position where it first transitions from black level to white level).
The output signal is sent to the counter 42 as a count stop signal, and the counter 42 is stopped.

The latch pulse generation circuit 58 is connected to the synchronous separation circuit 26.
A latch pulse is generated at the fall of the synchronizing signal from the trigger circuit 29, and this latch pulse is applied to the latch circuits 59 and 60 through the AND gate 30 by the output signal of the trigger circuit 29. Latch circuit 5
9 and 60 are counter 4 due to the latch pulse.
The count values of 1 and 42 are latched, and the data set flip-flop 61 is set by a latch pulse from the AND gate 30 and sends an output signal to the microcomputer 20 as a data set completion signal ○. When the microcomputer 20 receives the data set completion signal ○a, the latch circuit 5
The data set flip-flop 61 is reset by fetching data from the flip-flops 9 and 60 and then sending a data fetching completion signal ○.

Further, the reset pulse generation circuit 62 generates a reset pulse after the latch pulse based on the synchronization signal from the synchronization separation circuit 26, and this reset pulse causes the counters 41 and 42, the positive trigger flip-flop 56, and the negative trigger flip-flop 57 to operate. is reset. When the counter 41 exceeds a set value (count value corresponding to one scanning line), its output signal is input to the OR circuit 55 and the counters 41 and 42 are stopped.

The above operation is repeated for every one scanning line of the video signal, and the AND circuit 63 receives the output signal of the horizontal synchronization counter 32 so that the horizontal synchronization counter 32 becomes 26.
2, that is, when the above operation is completed for the odd field video signal, a pulse is output. The output signal of the horizontal synchronization counter 32 is input to the AND circuit 64, and the horizontal synchronization counter 32 becomes 52.
5, that is, when the above operation is completed for one frame of video signal, a pulse is output.
It can be selected manually. switch 6
The pulse from 5 resets the trigger circuit 29 and the flip-flop 25, and is sent to the microcomputer 20 as a complete data acquisition signal.

FIG. 10 shows the relationship between the subject, the binarized signal from the binarization circuit 46, and the output signal of the frequency division circuit 49 with a frequency division ratio of 1/2, and FIG. 11 shows the relationship between the subject and the binarization circuit 46.
Binarized signal from 6, frequency divider circuit 5 with frequency division ratio 1/3
The relationship between output signals of 0 is shown.

FIG. 12 shows the data import processing routine of the microcomputer 20.

The microcomputer 20 first outputs the data acquisition request signal ○C and the scanning area and clock designation signal ○H to the image processing device 19, checks the data set completion signal ○I from the image processing device 19, and processes this signal ○I. When inputted, data from the latch circuits 59 and 60 is taken in and written into the RAM, and then a data taking completion signal ○○ is output to the image processing device 19. When the number of data to be acquired reaches the set value by repeating such data acquisition operation, that is, the image processing device 19
When the all data import completion signal ○2 is input from 2
The signal ○ that advances the frequency division ratio of the value signal from 1 to 1/2 is output to the image processing device 19 and is processed by the AND gate 48.
1 is closed and the AND gate 482 is opened. Then, the data acquisition request signal ○c is outputted again to perform the data acquisition operation, and in the same manner, each time the number of data acquisition reaches the set number, the frequency division ratio of the binarized signal is changed to 1/2,
Output the signal ○ to advance sequentially like 1/3, ......1/n, and use the AND gates 482 to 4.
8n in sequence and repeat the data acquisition operation. While increasing the division ratio of the binary signal in the image processing device 19, counters 41 and 42 count the rising and falling positions of the binary signal, and the latch circuits 59 and
If this is done by latching at 60, all the binary signals become non-signal, and the values of the latch circuits 59 and 60 reach a state where they all correspond to the end of the scanning line (right side of the screen). When all of the imported data (the number of data set above) reaches the value corresponding to the right edge of the screen, this is determined to be the end of pattern recognition (processing to convert the binary signal into one-dimensional data), and the data is imported. The X-axis, Y-axis, rotation angle, and position information of the workpiece 16 are obtained by processing the data, and this is compared with the regular position information, and the motor drive circuit 21 is controlled based on the results.

In the above embodiment, the frequency division ratio of the binary signal is automatically advanced until the end of the one-dimensional data conversion process, but in other embodiments, the microcomputer 20 in the above embodiment The frequency division ratio of the conversion signal is automatically advanced to a preset value (1/3 in this case) according to the shape of the workpiece 16.

(Effects of the Invention) As described above, according to the present invention, since the video signal is binarized and the data of the transposed position is stored, the amount of processing data is reduced, the capacity of the storage means can be reduced, the cost can be reduced, and the minimum The resolution can be reduced, making it particularly suitable for processing simple shapes.
In addition, by dividing the binary signal using one of a plurality of different division ratios using a frequency divider and selectively specifying the division ratio using the division specification section, it is possible to process somewhat complex figures. It is also effective for

[Brief explanation of drawings]

Figure 1 is a block diagram showing the outline of the present invention, Figure 2 is a block diagram showing the outline of the present invention.
The figure is a timing chart of the same example, and Figures 3 to 6 are diagrams showing the subject and processed images of the same example.
FIG. 7 is a schematic diagram showing an application example of the present invention, FIG. 8 is a block diagram showing an image processing device of the same application example, and FIG.
The figure is a timing chart of the image processing device, No. 1.
Figures 0 and 11 are diagrams showing the relationship between the subject, the binarized signal, and the output signal of the frequency dividing circuit in the above application example.
FIG. 2 is a flow chart showing a data import processing routine of a microcomputer in the above application example, FIG. 13 is a flow chart showing a data import processing routine of a microcomputer in another application example of the present invention, and FIG. 14 is a flow chart showing a data import processing routine of a microcomputer in another application example of the present invention. FIG. 2 is a block diagram showing the device. 11, 58... Latch pulse generation circuit, 12,
41, 42... Counter, 14, 59, 60...
Latch circuit, 46...Binarization circuit, 492-49
n... Frequency division circuit, 53... Frequency division specification section.

Claims (1)

[Claims] 1 Binarization means for obtaining a binarized signal from a video signal, a frequency divider that divides the binarized signal from the binarization means by one of a plurality of mutually different frequency division ratios, and this frequency divider. a frequency division specifying section for selectively specifying a frequency division ratio of the frequency divider, and a signal from the frequency divider changes from white to black;
and/or an image processing device comprising: a measuring means for measuring a position of transition from black to white; and a storage means for storing a measured value of the position of transition from the measuring means.