JPH04165781A - Picture storage device - Google Patents

Abstract

PURPOSE:To prevent the output of a picture with only half field by forcedly performing field fetch when an input picture signal is a non-interlace signal, interpolating the signal of a field insufficient to the output to be a pseudo frame signal. CONSTITUTION:A means 126 deciding whether the input picture signal is an interlace signal or non-interlace signal, a writing means 16 writing the input picture signal in memory means 14K, 14G, and 14B, and a control means 22 controlling the writing means 16 according to the discrimination of the decision means 126. Therefore, the input picture signal can be written in the memory means 14K, 14G, and 14B whether the input picture signal is the interlace signal or the non-interlace signal. When the input picture signal is the non-interlace signal, the field fetch is forcedly performed and the field signal insufficient to the output is interpolated to be the pseudo frame signal. Thus, the output of the only half field picture can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image storage device, and more specifically to an image storage device that stores at least one frame of still image.

[Prior Art] Video signals are generally interlaced signals in which one frame is alternately divided into odd field signals and even field signals, and conventional image storage devices alternate between odd field signals and even field signals in one frame. It was determined whether the data was a field or not, and the write address was controlled according to the determination result.

[Problems to be Solved by the Invention] However, for example, when playing back images field-recorded on a still video floppy, which is a recording medium in an electronic still camera system, or when playing a video tape or
In the case of still playback of a recorder (VTR), the signal of one field is repeatedly supplied to the image storage device as a non-interlaced signal. Therefore, for example, in the case of a non-interlaced signal in which only odd field image signals are supplied, the input image is stored in the field memory for odd fields, but the corresponding input image is stored in the field memory for even fields. Even field signals are not stored. That is, the field memory for even fields either stores the previous image, or the previous image is cleared and nothing is stored in the field memory.

If you try to make a hard copy of the image stored in the image storage device under these conditions, one field will output the last stored image, but the other field will output an unrelated image. This could lead to a situation.

Therefore, an object of the present invention is to provide an image storage device that eliminates such inconveniences.

[Means for Solving the Problems] An image storage device according to the present invention includes means for determining whether an input image signal is an interlaced signal or a non-interlaced signal, a writing means for writing the input image signal into a memory means, and the determining means. and control means for controlling the writing means in accordance with the determination.

[Operation] The above means allows the input image signal to be written into the memory means without any problem whether it is an interlace signal or a non-interlace signal. Also, if the input image signal is a non-interlaced signal, under-field capture is forcibly performed.
At the time of output, the signal of the missing field is interpolated to create a pseudo frame signal, so it is no longer possible to output an image of only one field.

[Example code] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. 1
0 is an input terminal for a composite video signal, 12 is an input image processing circuit that converts the composite signal input to the input terminal 10 into an RGB signal, and 14R is an R that stores an R signal.
Memory, 14G is G memory that stores G signal, 14B is B memory that stores B signal, 16 is memory 14R, 14
18 is an output image processing circuit that converts the RGB signal from the memory control circuit into a composite signal, 20 is an output terminal, and 22 is a system control circuit that controls the entire system. .

Memories 14R, 14G, and 14B are each frame memories comprising two field memories.

FIG. 2 shows a detailed circuit configuration of the input image processing circuit 12. The composite video signal from input terminal 10 is Y
/C is applied to the separation circuit 100 and the synchronous separation circuit 118. The Y/C separation circuit 100 separates the composite signal into a luminance signal and a chroma signal, and the separated chroma signal is converted by a decoder 102 into a color difference signal RY and the same B-Y. The matrix circuit 104 receives the luminance signal from the Y/C separation circuit 100, the color difference signal RY from the decoder 102,
An RGB signal is formed from B-Y. Matrix circuit 1
The R, G, and B signals by 04 are each low-pass
The signal is band-limited by a filter (LPF) 106°, 108, and 110 and applied to A/D converters 111, 114, and 116.

On the other hand, the synchronization separation circuit 118 separates the composite synchronization signal from the composite signal from the input terminal 10, and the horizontal/vertical separation circuit 120 separates the composite synchronization signal into a horizontal synchronization signal HD and a vertical synchronization signal VD. 122 determines whether the composite synchronization signal output from the synchronization separation circuit 118 is an odd field or an even field. Horizontal/vertical separation circuit 120
vertical synchronization signal VD separated by
The determination result output of step 2 is applied to an interlace/non-interlace discrimination circuit 126, and the determination circuit 126 discriminates whether the image signal inputted subsequently to the input terminal 10 is an interlace signal or a non-interlace signal, as will be described in detail later. The interlaced/non-interlaced signal 44 resulting from the determination is supplied to the system control circuit 22.

The gated oscillator 124 has a horizontal and vertical separation path 1.
A sampling clock 36 of a predetermined frequency is generated by the horizontal synchronization signal outputted from 20. A/D converter 1
12. ．． 114 and 116 convert the outputs of the L P F 106, 108, and 110, respectively, into 8-bit digital signals in response to the sampling clock from the gated oscillator 124.

FIG. 5 shows an example of the circuit configuration of the interlace/non-interlace discrimination circuit 126, and FIG. 6 shows a timing chart when an interlace signal is input. Odd/even signal 4 which is the discrimination result of the odd/even discrimination circuit 122
2 is applied to the D input of the D flip-flop 128, and the vertical synchronization signal 40 from the horizontal/vertical separation circuit 120 is applied to its clock terminal. Since it is an interlaced signal, the odd/even signal 42 changes from H (high) to odd low and from L to H for each field, and the output of the D flip-flop 128 is vertical as shown in FIG. 6 (3). From H to L in response to the rise of the synchronization signal (Fig. 6 (1))
Changes from to H.

The exclusive NOR circuit 130 takes the exclusive NOR of the odd/even signal 42 and the output of the D flip-flop 128, and the output has the waveform shown in FIG.
34 D input. D flip-flop 134
A signal obtained by inverting the vertical synchronizing signal 40 is applied to the clock input of the inverter 132, and the D flip-flop 134 outputs the D input at the falling edge of the vertical synchronizing signal 40. In the case of FIG. 6, the output of the D flip-flop 7 remains at L.

On the other hand, when a non-interlaced signal is input, the odd/even signal 42 remains at H or L, and therefore the output of the D flip-flop 128 also remains at H or L in relation to the vertical synchronization signal 40.

Therefore, the output of the exclusive NOR circuit 130 is always H,
The output of the D flip-flop 134 is also always H.

In this way, the output of the interlace/non-interlace discrimination circuit 126 (i.e., the output of the D flip-flop 13
4) becomes L in the case of an interlaced signal, and becomes H in the case of a non-interlaced signal.

The system control circuit 22 uses the interlace/non-interlace signal 44 from the input image processing circuit 12 to instruct the memory control circuit 16 to take in a frame in the case of interlace, and to take in a field in the case of non-interlace.

An example of the circuit configuration of the memory control circuit 16 is shown in FIG. First, the case where input images are written into the memories 14R, 14G, and 14B will be described. Switches 136R, 136G, 136B, 144,
146, 148, and 150 are connected to a contacts. The sampling clock 36 is applied from the gated oscillator 124 via the switch 144 to the H area signal generation circuit 152, and the horizontal synchronization signal 38 is applied from the horizontal/vertical separation circuit 120 via the switch 146. Generates an area signal corresponding to the screen. Also,
■The area signal generation circuit 154 includes switches 146 and 1.
A horizontal synchronizing signal 38 and a vertical synchronizing signal 40 are applied from the horizontal/vertical separation circuit 120 via 48 to generate an area signal corresponding to an effective screen in the vertical direction.

The address counter 156 receives the sampling clock 36, the area signal output from the H area signal generation circuit 152 and the V area signal generation circuit 154, and the odd area signal under the control signal for frame acquisition or field acquisition from the system control circuit 22. /According to even signal 42, address signals 48, 54.6 of memories 14R, 14G, 14B
Generates 0. In addition, the control signal generation circuit 158 generates data from the memories 14R314G, 14B in accordance with the sampling clock 36 and the area signal output from the H area signal generation circuit 152 under the frame capture or field capture control signal from the system control circuit 22. Generates control signals 46, 52, 58 necessary for writing to. This address signal 48.54.60 and control signal 46,5
2.58, A/D converters 112, 114, 116
The R, G, and B signals 30, 32, and 34 outputted from the memory 14R, 14G, and 14B are written into the memories 14R, 14G, and 14B.

Next, the operation when reading frame signals stored in the memories 14R, 14G, and 14B and outputting them to the output image processing circuit 18 will be described. In this case, system control circuit 2
2, switches 136R, 136G
, 136B, 144°, 146, 148, 150 are connected to the B contact, and the switches 142R, 142G, 142B are always connected to the S contact.

Details will be described later, or switch 144.1'46°148
．． From the output image processing circuit 18 via 150, a sampling clock 36, a horizontal sync signal 38, a vertical sync signal 70, and a sampling clock 70, a horizontal sync signal 72, a vertical sync signal 7 similar to the odd/even signal 42, respectively.
4 and an odd/even signal 76, and the H area signal generation circuit 152, the area signal generation circuit 154, and the address counter 156 similarly receive the address signal 48°5.
Generates 4.60. The control signal generation circuit 158 generates a control signal for reading a frame of an image signal stored in a frame according to a control signal from the system control circuit 22.

According to the address output by the address counter 156 and the control signal generated by the control signal generation circuit 158, image signals are read out from the memories 14R, 14G, and 14B alternately in odd fields and even fields. Memory 14R, 1
4; the signal read from 14B is sent to switch 13
6R, 136G.

136B and switch 142. R, 142G, 142B
is supplied to the output image processing circuit 18 via.

The output image processing circuit 18 receives the RG from the memory control circuit 16.
The B signal is converted into a composite signal and outputted to the output terminal 20. A circuit example of the output image processing circuit 18 is shown in FIG. The output image processing circuit 18 includes a D/A converter 160R,
160G and 160B are R from the memory control circuit 16,
G, B digital signals 64, 66.68 are converted into analog signals, and each output is passed through a low-pass filter (LPF) 1.
The signal is band-limited by 62R, 162G, and 162B and applied to the matrix circuit 164. Matrix circuit 164
is an RGB signal, a luminance signal Y+S with a synchronization signal, and 2
The decoder 166 converts it into two color difference signals R-Y and B-Y.
forms a chroma signal from the color difference signals R-Y and B-Y.

Adder 168 superimposes the chroma signal from decoder 166 on the luminance signal with a synchronization signal from matrix circuit 164, and outputs it to output terminal 20 as a composite video signal.

Further, the synchronization signal generation circuit 170 includes the matrix circuit 16
4 and a horizontal synchronization signal 72.
, a vertical synchronization signal 74, and an odd/even signal 76 specifying a field, and the gated oscillator 172 generates a sampling clock 70 in response to a horizontal synchronization signal from the synchronization signal generation circuit 170. D/A converter 1
60R.

160G and 160B are the sampling clock 70
D/A conversion is performed accordingly. As described above, the sampling clock 70, the horizontal synchronization signal 72, the vertical synchronization signal 74, and the odd/even signal 76 are sent to the memory control circuit 16 and used to control reading of the memories 14R114G and 14B.

The operation of the memory control circuit 16 when outputting an image signal subjected to field capture will be described.

In this case, the control signal generation circuit 158 controls the memories 14R914G and 1 by the control signal from the system control circuit 22.
Generates a control signal to instruct reading from the same field memory of 4B.

Signals read from the memories 14R, 14G, 14B are directly and IH delay lines 138R, 138G, 138B.
It is applied to the averaging circuits 140R, 140G, 140B via the averaging circuits 140R, 140G, 140B.
B outputs a signal that is the average value of the signals of two adjacent lines. That is, a signal of another field is formed. Also,
The system control circuit 22 uses the odd/even signal 76 from the output image processing circuit 18 to control the switch 1 for each vertical scanning period.
42R, 142G, and 142B are alternately switched to a and b contacts. As a result, in the output image processing circuit 18, one field is a signal stored in the memories 14R114G and 14B, and the other field is a signal stored in the delay lines 138R' and 138R'.
8G, 138B and averaging circuit 140R, 140G, 1
An interlaced signal consisting of a signal formed by interpolation is supplied by 40B.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, in the case of an input image signal or a non-interlaced signal, field capture is forcibly performed, and when outputting, the signal of the missing field is Since it is interpolated to generate a pseudo frame signal, it is possible to avoid outputting an image of only one field.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of the input image processing circuit 12, FIG. 3 is a block diagram of the memory control circuit 16, and FIG. 4 is the output image 5 is a circuit configuration block diagram of the processing circuit 18, FIG. 5 is a circuit configuration block diagram of the interlace/non-interlace discrimination circuit 126, and FIG. 6 is a timing diagram of the interlace/non-interlace discrimination circuit 126. 10: Composite video signal input terminal 12, Input image processing circuit 14R: R memory 14G2G memory
14B: B memory 16: Memory control circuit 18:
Output image processing circuit 20. Output terminal 22 System control circuit 100: Y/C separation circuit 100 102: Decoder 104/Matrix circuit 106, 108, 11
0: Low bass filter 112, 114, 116: A
/D converter 118: Synchronous separation circuit 120: Horizontal/vertical separation circuit 122: Odd/even discrimination circuit 124: Gated oscillator 126: Interlace/non-interlace discrimination circuit 128: D flip-flop 1
30: Exclusive NOR circuit 132: Inverter 134:
D flip-flop 136R, 136G, 136B: Switch 138R, 138G, 138B: IH delay line
140R, 140G, 140B: Averaging circuit switch: 142R, 142G, 142B, 144, 146.1
48, 150: Switch 152: H area signal generation circuit 154: V area signal generation circuit 156: Address
Counter 158: Control signal generation circuit 160R, 16
0G, 160B: D/A converter 162R, 162G,
162B: Low-pass filter 164: Matrix circuit 166: Decoder 168: Adder 170: Synchronous signal generation circuit

Claims (2)

[Claims] (1) means for determining whether an input image signal is an interlaced signal or a non-interlaced signal; a writing means for writing the input image signal into a memory means; and a control means for controlling the writing means in accordance with the determination by the determining means. An image storage device comprising: (2) Claim 1 includes means for forming a signal of another field from a signal of one field, and when an image is captured in a field, the other field is interpolated and output. image storage device.