JPH04165517A - Interface circuit using electromagnetic induction coupling - Google Patents
Interface circuit using electromagnetic induction couplingInfo
- Publication number
- JPH04165517A JPH04165517A JP2292675A JP29267590A JPH04165517A JP H04165517 A JPH04165517 A JP H04165517A JP 2292675 A JP2292675 A JP 2292675A JP 29267590 A JP29267590 A JP 29267590A JP H04165517 A JPH04165517 A JP H04165517A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- coil
- capacitor
- power supply
- inductive coupling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010168 coupling process Methods 0.000 title claims description 30
- 230000008878 coupling Effects 0.000 title claims description 26
- 238000005859 coupling reaction Methods 0.000 title claims description 26
- 230000005674 electromagnetic induction Effects 0.000 title description 2
- 239000003990 capacitor Substances 0.000 claims abstract description 42
- 230000001939 inductive effect Effects 0.000 claims description 26
- 238000009499 grossing Methods 0.000 claims description 7
- 230000004907 flux Effects 0.000 abstract description 16
- 230000006698 induction Effects 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 11
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F38/00—Adaptations of transformers or inductances for specific applications or functions
- H01F38/14—Inductive couplings
- H01F2038/143—Inductive couplings for signals
Landscapes
- Near-Field Transmission Systems (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
本発明は、リーグ・ライタとの電磁誘導結合によりデー
タ書込み又はデータ読出しを受けるデータキャリアのイ
ンタフェース回路に関し、特に、電磁誘導結合により誘
起された信号電圧から自己の電源電圧を作り、また誘起
電圧を二値化してデジタル信号処理を行なう電磁誘導結
合を用いたインタフェース回路に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interface circuit for a data carrier that receives data writing or data reading by electromagnetic inductive coupling with a league writer, and in particular, relates to an interface circuit for a data carrier that receives data writing or data reading by electromagnetic inductive coupling with a league writer. The present invention relates to an interface circuit using electromagnetic inductive coupling that generates its own power supply voltage from a signal voltage, binarizes the induced voltage, and performs digital signal processing.
[従来の技術]
従来、データキャリアの非接触結合方式として電磁誘導
結合方式が注目されている。電磁誘導結合方式は、非接
触方式であることから、電気接続のように汚れや錆等に
対する接触不良の問題がなく、またデータキャリアのコ
イルに誘起された信号電圧を整流平滑して自己の電源を
作ることができるため、光結合方式のようにデータキャ
リアに交換を必要とする電池電源を設ける必要がないと
いう利点がある。[Prior Art] Conventionally, an electromagnetic inductive coupling method has attracted attention as a non-contact coupling method for data carriers. Since the electromagnetic inductive coupling method is a non-contact method, there is no problem of poor contact due to dirt or rust as with electrical connections, and the signal voltage induced in the coil of the data carrier is rectified and smoothed to provide its own power source. This has the advantage that unlike the optical coupling method, there is no need to provide a battery power source that requires replacement for the data carrier.
このため電磁誘導結合を用いたデータキャリアには、例
えば第4図に示すように、コイル10に誘起された信号
電圧を整流平滑して自己の直流電源電圧を作り出す電源
回路部12と、電源回路部12から電源電圧Vccの供
給を受けて動作し、コイル10に誘起された信号電圧を
二値化してデジタル出力Foulを生ずる二値化回路1
4が設けられる。For this reason, a data carrier using electromagnetic inductive coupling includes a power supply circuit section 12 that rectifies and smoothes the signal voltage induced in a coil 10 to generate its own DC power supply voltage, and a power supply circuit section 12, as shown in FIG. 4, for example. A binarization circuit 1 operates upon receiving power supply voltage Vcc from the unit 12, and binarizes the signal voltage induced in the coil 10 to generate a digital output Foul.
4 is provided.
更に詳細に説明すると、電源回路部12は、コイル10
の両端の誘起電圧をタイオードDi、D2により全波整
流してコンデンサC1に充電して平滑し、電源電圧Vc
cを作り出している。To explain in more detail, the power supply circuit section 12 includes a coil 10
The induced voltage at both ends of is full-wave rectified by diodes Di and D2, and capacitor C1 is charged and smoothed, and the power supply voltage Vc
It is creating c.
また二値化回路14は、例えばCMO8型のICが使用
され、電源電圧Vccの半分となるV cc/2を閾値
電圧としてコイル誘起電圧を矩形信号に二値化する。The binarization circuit 14 uses, for example, a CMO8 type IC, and binarizes the coil induced voltage into a rectangular signal using Vcc/2, which is half of the power supply voltage Vcc, as a threshold voltage.
[発明が解決しようとする課題]
しかしながら、このような従来の電磁誘導結合を用いた
インタフェース回路においては、第5図に示すように、
二値化回路14に入力するa点のコイル誘起電圧は、破
線で示す磁束φの大小により振幅が変化し、Vcc/2
の閾値電圧で二値化した場合、磁束か強い場合の出力波
形Foullと、弱い場合の出力波形1” out2で
はオン時間t1とオフ時間t2で決まる周期T及びデユ
ーティ比(tl/T)が変化してしまい、このような二
値化出力では安定したデータ処理を行うことができない
問題がある。[Problems to be Solved by the Invention] However, in such a conventional interface circuit using electromagnetic inductive coupling, as shown in FIG.
The amplitude of the coil induced voltage at point a input to the binarization circuit 14 changes depending on the magnitude of the magnetic flux φ shown by the broken line, and Vcc/2
When binarized at the threshold voltage of Therefore, there is a problem that stable data processing cannot be performed with such a binary output.
本発明は、このような従来の問題点に鑑みてなされたも
ので、磁束の大小に関わらず常に二値化出力の周期及び
デユーティ比を一定に保つことのできる電磁誘導結合を
用いたインタフェース回路を提供することを目的とする
。The present invention has been made in view of such conventional problems, and provides an interface circuit using electromagnetic inductive coupling that can always keep the period and duty ratio of binary output constant regardless of the magnitude of magnetic flux. The purpose is to provide
[課題を解決するための手段]
この目的を達成するため本発明にあっては次のように構
成する。尚、実施例図面中の符号を併せて示す。[Means for Solving the Problems] To achieve this object, the present invention is configured as follows. In addition, the reference numerals in the drawings of the embodiments are also shown.
まず本発明は、電磁誘導結合によりコイル10に誘起さ
れた交流信号電圧を整流して自己の直流電源電圧を作り
出す電源回路部12と、コイル誘起電圧を二値化する二
値化回路部14とを有する電磁誘導結合を用いたインタ
フェース回路を対象きする。First, the present invention includes a power supply circuit unit 12 that rectifies an AC signal voltage induced in a coil 10 by electromagnetic induction coupling to generate its own DC power supply voltage, and a binarization circuit unit 14 that binarizes the coil induced voltage. The target is an interface circuit using electromagnetic inductive coupling.
このようなインタフェース回路として本願の第1発明は
、コイル1.0の誘起電圧を整流する第1の整流素子D
1と、第1の整流素子D1の整流出力を平滑する第1の
コンデンサC1と、第1の整流素子D1に並列接続され
、コイルの誘起電圧に前記第1のコンデンサC1の充電
電圧を加算した電圧を整流する第2の整流素子D2と、
第2の整流素子D2の整流出力を平滑する第2のコンデ
ンサC2とを備え、第1のコンデンサC1でレベルシフ
トされたコイル誘起電圧を電源電圧Vccの半分の閾値
電圧をもつ二値化回路部14に入力して二値化すること
を特徴とする。As such an interface circuit, the first invention of the present application includes a first rectifying element D that rectifies the induced voltage of the coil 1.0.
1, a first capacitor C1 that smoothes the rectified output of the first rectifying element D1, and a first capacitor C1 that is connected in parallel to the first rectifying element D1, and the charging voltage of the first capacitor C1 is added to the induced voltage of the coil. a second rectifying element D2 that rectifies the voltage;
A binarization circuit section that includes a second capacitor C2 that smoothes the rectified output of the second rectifying element D2, and that converts the coil induced voltage level-shifted by the first capacitor C1 into a binarization circuit section that has a threshold voltage that is half the power supply voltage Vcc. 14 and binarized.
また本願の第2発明としてのインタフェース回路にあっ
ては、電源回路部12に、第1のコンデンサC1と第2
のコンデンサC2を直列接続した倍電圧平滑回路16と
、コイル10の正極性の半サイクルの誘起電圧を整流し
て第1のコンデンサC1を充電する第1の整流素子D1
と、コイル10の負極性の半サイクルの誘起電圧を整流
して第2のコンデンサC2を充電する第1の整流素子D
2とを設け、第2のコンデンサC2でレベルシフトされ
たコイル誘起電圧を第1と第2の整流素子D1..D2
の接続点から取出して電源電圧の半分の閾値電圧をもつ
二値化回路部14て二値化することを特徴とする。Further, in the interface circuit as the second invention of the present application, the power supply circuit section 12 includes a first capacitor C1 and a second capacitor C1.
a voltage doubler smoothing circuit 16 in which capacitors C2 are connected in series, and a first rectifying element D1 that rectifies the positive half-cycle induced voltage of the coil 10 to charge the first capacitor C1.
and a first rectifying element D that rectifies the negative half-cycle induced voltage of the coil 10 to charge the second capacitor C2.
2 are provided, and the coil induced voltage level-shifted by the second capacitor C2 is transferred to the first and second rectifying elements D1 . .. D2
It is characterized in that it is taken out from the connection point of and binarized by a binarization circuit section 14 having a threshold voltage that is half the power supply voltage.
更に第1発明及び第2発明のインタフェース回路に於い
て、電源回路部12及び二値化回路部14を、リーダラ
タイタの間の電磁誘導結合によりデータ書込ろ又は読出
しを受けるデータキャリアに組込んだことを特徴とする
。Furthermore, in the interface circuits of the first and second inventions, the power supply circuit section 12 and the binarization circuit section 14 are incorporated into a data carrier that receives data writing or reading by electromagnetic inductive coupling between the reader/titer. It is characterized by
1作用」
このような構成を備えた本発明による電磁誘導結合を用
いたインタフェース回路によれば、コイルに作用する磁
束の強さが変って誘起電圧の振幅が変化しても、誘起電
圧を電源電圧の半分となるVcc/2だけアップするレ
ベルシフトを行っていることで、誘起電圧のゼロクロス
レベルを二値化回路の閾値レベルに一致させることかで
き、従って、誘起電圧の振幅か磁束に応じて変動しても
、常に一定の周期とデユーティ比て二値化することがで
きる。According to the interface circuit using electromagnetic inductive coupling according to the present invention having such a configuration, even if the amplitude of the induced voltage changes due to the change in the strength of the magnetic flux acting on the coil, the induced voltage can be directly connected to the power supply. By performing a level shift that increases by Vcc/2, which is half the voltage, it is possible to match the zero cross level of the induced voltage with the threshold level of the binarization circuit, and therefore It is possible to always perform binarization with a constant cycle and duty ratio even if the frequency changes.
[実施例]
第1図は本発明の一実施例を示した実施例回路図である
。[Embodiment] FIG. 1 is an embodiment circuit diagram showing an embodiment of the present invention.
第1図において、10はコイルであり、コア18に所定
ターン数巻かれている。コア18としては円盤状部材の
一端に開口して1条の環状のコイル溝を備えたポットタ
イプのものが使用される。In FIG. 1, a coil 10 is wound around a core 18 with a predetermined number of turns. As the core 18, a pot-type core 18 is used, which has a single annular coil groove opened at one end of a disc-shaped member.
コア18に巻かれたコイル10に対しては例えばリーダ
・ライタ側に設けられた同しコアとコイルで成る磁気誘
導結合部に対する所定周波数信号の通電で得られた交播
磁界による磁束が加わり、磁束の強さに応じた誘起電圧
をコイル端子20,22間に発生する。A magnetic flux is applied to the coil 10 wound around the core 18 by an alternating magnetic field obtained by energizing a predetermined frequency signal to a magnetic inductive coupling unit made of the same core and coil provided on the reader/writer side, for example. An induced voltage corresponding to the strength of the magnetic flux is generated between the coil terminals 20 and 22.
コイル10に続いては電源回路部12が設けられる。電
源回路部12において、コイル10の端子20は第1の
コンデンサC1を介して第1の整流素子としてのダイオ
ードD2のアノード側が接続され、ダイオードD2のカ
ソード側には平滑用として使用される第2のコンデンサ
C2が接続される。A power supply circuit section 12 is provided following the coil 10. In the power supply circuit section 12, a terminal 20 of the coil 10 is connected to the anode side of a diode D2 as a first rectifying element via a first capacitor C1, and a second terminal used for smoothing is connected to the cathode side of the diode D2. capacitor C2 is connected.
コイル10の端子22からはグランドラインGNDが引
き出され、端子22側に第1の整流素子としてのダイオ
ードD1のアノード側を接続し、カソード側はダイオー
ドD2のアノードとコンデンサC1の接続点すに接続し
ている。A ground line GND is drawn out from the terminal 22 of the coil 10, and the anode side of a diode D1 as a first rectifying element is connected to the terminal 22 side, and the cathode side is connected to the connection point between the anode of the diode D2 and the capacitor C1. are doing.
14は二値化回路部であり、例えばCMO8型のICが
使用され、電源回路部12で作り出された電源電圧+V
ccの供給を受けて動作する。二値化回路部14には電
源回路部12におけるコンデンサC1を介して得られた
コイル10の誘起電圧がVinとして入力される。14 is a binarization circuit section, for example, a CMO8 type IC is used, and the power supply voltage +V generated by the power supply circuit section 12 is
It operates by receiving the supply of cc. The induced voltage of the coil 10 obtained via the capacitor C1 in the power supply circuit section 12 is inputted to the binarization circuit section 14 as Vin.
次に第1TI!Jの実施例の動作を第2A、2B図の信
号波形図を参照して説明する。ここで第2A。Next is the 1st TI! The operation of the embodiment J will be explained with reference to the signal waveform diagrams in FIGS. 2A and 2B. Here is the 2nd A.
2B図の信号波形図は第1図のa点のコイル10の誘起
電圧、b点の二値化回路部14に対する入力電圧Vin
、二値化回路14の出力Font及び電源電圧Vccを
示している。The signal waveform diagram in Figure 2B shows the induced voltage of the coil 10 at point a in Figure 1, and the input voltage Vin to the binarization circuit section 14 at point b.
, shows the output Font of the binarization circuit 14 and the power supply voltage Vcc.
リーダ・ライタ側から所定周波数の電磁誘導結合による
磁束をコイル10が受けると、磁束φが強い場合には第
2A図(a)の波形24て示す誘起電圧が得られ、一方
、磁束φが弱い場合には第2B図の波形26で示す信号
電圧が誘起される。When the coil 10 receives magnetic flux due to electromagnetic inductive coupling at a predetermined frequency from the reader/writer side, when the magnetic flux φ is strong, an induced voltage as shown in the waveform 24 in FIG. 2A (a) is obtained, while on the other hand, the magnetic flux φ is weak. In this case, a signal voltage shown by waveform 26 in FIG. 2B is induced.
コイル10に誘起された誘起電圧はダイオードDi、D
2.C1,C2による倍電圧半波整流されコンデンサC
2を誘起電圧の2倍の電圧Vccに充電する。このコン
デンサC2に対する充電時にコンデンサC1は電源電圧
Vccの半分となるVec/2に充電される。即ち、端
子22を(+)とする半サイクルでダイオードD1を介
してコンデンサC1はV CC/ 2 +、:充電サレ
す端子20を(+)とする次の半サイクルでコイル10
とコンデンサC1を加えたVccをコンデンサC2に充
電する。The induced voltage induced in the coil 10 is applied to the diodes Di and D.
2. Voltage doubler half-wave rectified by C1 and C2 and capacitor C
2 to a voltage Vcc twice the induced voltage. When charging the capacitor C2, the capacitor C1 is charged to Vec/2, which is half of the power supply voltage Vcc. That is, in a half cycle when the terminal 22 is set to (+), the capacitor C1 is charged to V CC / 2 + through the diode D1; and in the next half cycle when the terminal 20 is set to (+), the coil 10 is charged.
The capacitor C2 is charged with Vcc, which is the sum of the capacitor C1 and the capacitor C1.
従って第2A、2B図(a)に示すa点のコイル誘起電
圧はコンデンサCIの充電電圧Vcc/2によりレベル
アップされるレベルシフトを受けて第2A、2B図(b
)に示すb点の電圧として表われる。このb点のVcc
/2分だけレベルアップされたシフト電圧が二値化回路
部14に入力する。Therefore, the coil induced voltage at point a shown in Figures 2A and 2B (a) undergoes a level shift that is increased by the charging voltage Vcc/2 of the capacitor CI.
) is expressed as the voltage at point b. Vcc at this point b
The shift voltage whose level has been increased by /2 is input to the binarization circuit section 14.
二値化回路部14の閾値電圧は電源電圧Vccの半分と
なるVCC/2であるため、b点からの入力電圧Vin
が、例えば閾値電圧Vcc/2を上回った時に二値化出
力FoulはHレベルとなり、閾値Vcc/2を下回っ
た時に二値化出力FoulはLレベルとなる第2A、2
B図(C)の二値化された矩形波出力を生ずる。即ち、
第2A、2B図(a)のa点のコイル誘起電圧のゼロク
ロスポイントを検出して出力を反転する二値化が実質的
に行われたことになる。このコイル10の誘起電圧にお
けるゼロクロスポイントは磁束により振幅が変化し誘起
電圧が小さくなっても第2B図に示すように周波数が一
定であるため同じとなり、従って、第2B図(C)に示
すようにオン時間t1とオフ時間t2が共に等しい1対
1の関係にあり、tl+t2で定まる周期Tが一定で、
且つデユーティ比が50%を保つ安定した二値化出力を
得ることができる。Since the threshold voltage of the binarization circuit unit 14 is VCC/2, which is half of the power supply voltage Vcc, the input voltage Vin from point b
For example, when the voltage exceeds the threshold voltage Vcc/2, the binary output Foul becomes H level, and when it falls below the threshold voltage Vcc/2, the binary output Foul becomes L level.
A binarized rectangular wave output as shown in Figure B (C) is produced. That is,
Binarization in which the zero cross point of the coil induced voltage at point a in FIGS. 2A and 2B (a) is detected and the output is inverted has essentially been performed. Even if the amplitude changes due to the magnetic flux and the induced voltage becomes smaller, the zero-crossing point of the induced voltage in the coil 10 remains the same as shown in Figure 2B because the frequency is constant, and therefore, as shown in Figure 2B (C). There is a one-to-one relationship in which the on time t1 and the off time t2 are both equal, and the period T determined by tl + t2 is constant,
Moreover, a stable binary output with a duty ratio of 50% can be obtained.
また第1図の実施例にあっては、第4図の従来例におけ
るセンタータップ付きのコイル10を必要とせず、コイ
ル10の巻数を半分にできる。このようにコイル10の
巻数を減らすことができれば、コイル10の持つ浮遊容
量を減らし、その結果、電磁誘導結合における伝送可能
な周波数帯域をより広帯域にして信号波形の歪み及び損
失を低減することができる。Further, in the embodiment shown in FIG. 1, the center-tapped coil 10 in the conventional example shown in FIG. 4 is not required, and the number of turns of the coil 10 can be halved. If the number of turns of the coil 10 can be reduced in this way, the stray capacitance of the coil 10 can be reduced, and as a result, the frequency band that can be transmitted in electromagnetic inductive coupling can be made wider, thereby reducing signal waveform distortion and loss. can.
第3図は本願の第2発明に相当する本発明の他の実施例
を示した実施例回路図であり、倍電圧全波整流による電
源回路部を用いたことを特徴とする。FIG. 3 is an embodiment circuit diagram showing another embodiment of the present invention corresponding to the second invention of the present application, which is characterized by using a power supply circuit section based on voltage doubler full-wave rectification.
第3図において、電源回路部12は倍電圧平滑用の第1
のコンデンサC1と第2のコンデンサC2を直列接続し
た倍電圧平滑回路16を設ける。In FIG. 3, the power supply circuit section 12 has a first circuit for voltage doubler smoothing.
A voltage doubler smoothing circuit 16 is provided in which a capacitor C1 and a second capacitor C2 are connected in series.
倍電圧整流回路のコンデンサC1は第1の整流素子とし
てのダイオードD1によるコイル10に誘起された端子
20側をプラスとする正極性の半サイクルの誘起電圧の
整流出力で充電される。またコンデンサC2は第2の整
流素子としてのダイオードD2によるコイル10に誘起
された端子22側をプラスとする負極性の誘起電圧の半
サイクルの整流出力により充電される。従って、C1,
C2はコイルの誘起電圧に充電され、電源電圧Vccは
コイルの誘起電圧の2倍の電圧になる。The capacitor C1 of the voltage doubler rectifier circuit is charged by the rectified output of the positive half-cycle induced voltage induced in the coil 10 by the diode D1 as the first rectifier, with the terminal 20 side being positive. Further, the capacitor C2 is charged by the rectified output of a half cycle of the negative electromotive force induced in the coil 10 by the diode D2 as a second rectifying element, with the terminal 22 side being positive. Therefore, C1,
C2 is charged to the induced voltage of the coil, and the power supply voltage Vcc becomes twice the induced voltage of the coil.
二値化回路部14に対しては、コイル10の端子20、
即ちダイオードD1とD2の接続点の信号電圧がVin
として入力されている。For the binarization circuit section 14, the terminal 20 of the coil 10,
That is, the signal voltage at the connection point of diodes D1 and D2 is Vin
is entered as .
この第3図の実施例にあっても、二値化回路部14に対
する入力電圧Vinは倍電圧平滑回路16に設けたコン
デンサC2の充電電圧、即ち電源電圧VCCの半分■C
C/2分のレベルアップを受けた電圧となり、従って第
2A、2B図の信号波形図に示したと同様、コイル10
の誘起電圧のゼロクロスポイントを二値化回路部14て
検出して二値化することができる。従って、コイル10
に作用する磁束が変化しても、二値化回路部14の出力
Foujの周期T及びデユーティ比を常に一定に保つこ
とができる。Even in the embodiment shown in FIG. 3, the input voltage Vin to the binarization circuit section 14 is the charging voltage of the capacitor C2 provided in the voltage doubler smoothing circuit 16, that is, half of the power supply voltage VCC.
The voltage has been leveled up by C/2, and therefore, as shown in the signal waveform diagrams of Figures 2A and 2B,
The zero crossing point of the induced voltage can be detected by the binarization circuit section 14 and binarized. Therefore, coil 10
Even if the magnetic flux acting on the magnetic flux changes, the period T and duty ratio of the output Fouj of the binarization circuit section 14 can always be kept constant.
尚、上記の実施例は電磁誘導結合を用いたデータキャリ
アに用いられるインタフェース回路としての例をとるも
のであったが、本発明はデータキャリアに限定されず、
適宜の電磁誘導結合のインタフェース回路にそのまま適
用することができる。It should be noted that although the above-mentioned embodiment was an example of an interface circuit used in a data carrier using electromagnetic inductive coupling, the present invention is not limited to data carriers.
It can be applied as is to any suitable electromagnetic inductive coupling interface circuit.
[発明の効果]
以上説明してきたように、本発明によれば、電磁誘導結
合によりコイルに作用する磁束の変化に拘らず、二値化
回路により周期及びデユーティ比が一定となる二値化出
力を得ることができ、磁束の変動に依存した誘起電圧の
振幅変化があっても常に安定した二値化出力によりデジ
タル的なデータ処理を誤ることなく実行することができ
る。[Effects of the Invention] As explained above, according to the present invention, the binarization circuit produces a binarized output whose period and duty ratio are constant regardless of changes in the magnetic flux acting on the coil due to electromagnetic inductive coupling. Even if there is a change in the amplitude of the induced voltage depending on fluctuations in magnetic flux, digital data processing can be performed without errors due to the always stable binary output.
第1図は本発明の実施例回路図;
第2A、2B図は第1図の実施例の信号波形図;第3図
は本発明の他の実施例回路図:
第4図は従来技術の回路図;
第5図は従来回路の信号波形図である。
[符号の説明]
10:コイール
12:電源回路部
14:二値化回路部
16:倍電圧平滑回路
18:コア
20.22:コイルの端子
Dl:ダイオード(第1の整流素子)
D2:ダイオード(第2の整流素子)
C1:第1のコンデンサ
C2:第2のコンデンサ
特許出願人 株式会社トキメックFig. 1 is a circuit diagram of an embodiment of the present invention; Figs. 2A and 2B are signal waveform diagrams of the embodiment of Fig. 1; Fig. 3 is a circuit diagram of another embodiment of the invention; Fig. 4 is a circuit diagram of the prior art. Circuit diagram; FIG. 5 is a signal waveform diagram of a conventional circuit. [Explanation of symbols] 10: Coil 12: Power supply circuit section 14: Binarization circuit section 16: Voltage doubler smoothing circuit 18: Core 20.22: Coil terminal Dl: Diode (first rectifying element) D2: Diode ( (Second rectifying element) C1: First capacitor C2: Second capacitor Patent applicant Tokimec Co., Ltd.
Claims (3)
所望周波数の信号電圧を整流して自己の直流電源電圧を
作り出す電源回路部(12)と、前記コイル誘起電圧を
二値化する二値化回路部(14)とを有する電磁誘導結
合を用いたインタフェース回路に於いて、 前記電源回路部(12)は、 前記コイル(10)の誘起電圧を整流する第1の整流素
子(D1)と、 該第1の整流素子(D1)の整流出力を平滑する第1の
コンデンサ(C1)と、 該第1の整流素子(D1)に並列接続され、コイルの誘
起電圧に前記第1のコンデンサ(C1)の充電電圧を加
算した電圧を整流する第2の整流素子(D2)と、 該第2の整流素子(D2)の整流出力を平滑する第2の
コンデンサ(C2)と、 を備え、前記第1のコンデンサ(C1)でレベルシフト
されたコイル誘起電圧を電源電圧(Vcc)の半分の閾
値電圧をもつ前記二値化回路部(14)に入力して二値
化することを特徴とする電磁誘導結合を用いたインタフ
ェース回路。(1) A power supply circuit unit (12) that rectifies a signal voltage of a desired frequency induced in the coil (10) by electromagnetic inductive coupling to generate its own DC power supply voltage, and a binary value that binarizes the coil induced voltage. In the interface circuit using electromagnetic inductive coupling, the power supply circuit section (12) includes: a first rectifier element (D1) that rectifies the induced voltage of the coil (10); , a first capacitor (C1) that smoothes the rectified output of the first rectifier (D1), and a first capacitor (C1) that is connected in parallel to the first rectifier (D1) and is connected to the induced voltage of the coil. a second rectifying element (D2) that rectifies the voltage obtained by adding the charging voltage of C1); and a second capacitor (C2) that smoothes the rectified output of the second rectifying element (D2), The coil induced voltage level-shifted by the first capacitor (C1) is input to the binarization circuit section (14) having a threshold voltage half of the power supply voltage (Vcc) and binarized. Interface circuit using electromagnetic inductive coupling.
所望周波数の信号電圧を整流して自己の直流電源電圧を
作り出す電源回路部(12)と、前記コイル誘起電圧を
二値化する二値化回路部(14)とを有する電磁誘導結
合を用いたインタフェース回路に於いて、 前記電源回路部は、 第1のコンデンサ(C1)と第2のコンデンサ(C2)
を直列接続した倍電圧平滑回路(16)と、前記コイル
(10)の正極性の半サイクルの誘起電圧を整流して前
記第1のコンデンサ(C1)を充電する第1の整流素子
(D1)と、 前記コイル(10)の負極性の半サイクルの誘起電圧を
整流して前記第2のコンデンサ(C2)を充電する第1
の整流素子(D2)、 を備え、前記第2のコンデンサ(C2)でレベルシフト
されたコイル誘起電圧を前記第1と第2の整流素子(D
1,D2)の接続点から取出して電源電圧の半分の閾値
電圧をもつ前記二値化回路部(14)で二値化すること
を特徴とする電磁誘導結合を用いたインタフェース回路
。(2) A power supply circuit unit (12) that rectifies a signal voltage of a desired frequency induced in the coil (10) by electromagnetic inductive coupling to generate its own DC power supply voltage, and a binary value that binarizes the coil induced voltage. In the interface circuit using electromagnetic inductive coupling, the power supply circuit section includes a first capacitor (C1) and a second capacitor (C2).
a voltage doubler smoothing circuit (16) connected in series, and a first rectifying element (D1) that rectifies the positive half-cycle induced voltage of the coil (10) to charge the first capacitor (C1). and a first one that rectifies the negative half-cycle induced voltage of the coil (10) to charge the second capacitor (C2).
rectifying element (D2), and transmits the coil induced voltage level-shifted by the second capacitor (C2) to the first and second rectifying element (D2).
An interface circuit using electromagnetic inductive coupling, characterized in that the signal is taken out from the connection point (1, D2) and binarized by the binarization circuit section (14) having a threshold voltage half the power supply voltage.
タフェース回路に於いて、 前記電源回路部(12)及び二値化回路部(14)を、
リーダ・ライタとの間の電磁誘導結合によりデータ書込
み又は読出しを受けるデータキャリアに組込んだことを
特徴とする電磁誘導結合を用いたインタフェース回路。(3) In the interface circuit using electromagnetic inductive coupling according to claim 1 or 2, the power supply circuit section (12) and the binarization circuit section (14),
An interface circuit using electromagnetic inductive coupling, characterized in that it is incorporated into a data carrier that receives data writing or reading by electromagnetic inductive coupling with a reader/writer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2292675A JP2702602B2 (en) | 1990-10-30 | 1990-10-30 | Interface circuit using electromagnetic induction coupling |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2292675A JP2702602B2 (en) | 1990-10-30 | 1990-10-30 | Interface circuit using electromagnetic induction coupling |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04165517A true JPH04165517A (en) | 1992-06-11 |
JP2702602B2 JP2702602B2 (en) | 1998-01-21 |
Family
ID=17784846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2292675A Expired - Fee Related JP2702602B2 (en) | 1990-10-30 | 1990-10-30 | Interface circuit using electromagnetic induction coupling |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2702602B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014108772A (en) * | 2012-12-04 | 2014-06-12 | Sumitomo Rubber Ind Ltd | Storage circuit |
US20210152957A1 (en) * | 2018-07-31 | 2021-05-20 | Earlens Corporation | Demodulation in a contact hearing system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01126783A (en) * | 1987-11-12 | 1989-05-18 | Nippon Chemicon Corp | Data signal extracting device for ic card receiving circuit |
-
1990
- 1990-10-30 JP JP2292675A patent/JP2702602B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01126783A (en) * | 1987-11-12 | 1989-05-18 | Nippon Chemicon Corp | Data signal extracting device for ic card receiving circuit |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014108772A (en) * | 2012-12-04 | 2014-06-12 | Sumitomo Rubber Ind Ltd | Storage circuit |
US20210152957A1 (en) * | 2018-07-31 | 2021-05-20 | Earlens Corporation | Demodulation in a contact hearing system |
US11343617B2 (en) | 2018-07-31 | 2022-05-24 | Earlens Corporation | Modulation in a contact hearing system |
US11375321B2 (en) | 2018-07-31 | 2022-06-28 | Earlens Corporation | Eartip venting in a contact hearing system |
US11606649B2 (en) | 2018-07-31 | 2023-03-14 | Earlens Corporation | Inductive coupling coil structure in a contact hearing system |
US11711657B2 (en) * | 2018-07-31 | 2023-07-25 | Earlens Corporation | Demodulation in a contact hearing system |
Also Published As
Publication number | Publication date |
---|---|
JP2702602B2 (en) | 1998-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100471655B1 (en) | Data exchange system by contactless communication between terminal and remotely powered portable device | |
Abe et al. | A noncontact charger using a resonant converter with parallel capacitor of the secondary coil | |
JP4854604B2 (en) | Semiconductor integrated circuit, card equipped with the same, and operation method thereof | |
US10348130B2 (en) | Power harvesting for RFID/NFC-applications | |
US7339480B2 (en) | Power processing interface for passive radio frequency identification system | |
US6848620B2 (en) | Semiconductor integrated circuit | |
US6011488A (en) | Radio frequency interface device for a transponder | |
JPH11168417A (en) | Demodulator for non-contact chip card | |
JP2004518376A (en) | Low power passive transponder | |
JP2011022923A (en) | Contactless ic card and wireless system | |
TW200304265A (en) | Rectifier utilizing a grounded antenna | |
JPS59117319A (en) | Inductive proximity switch | |
KR20180118138A (en) | High Frequency Multilevel Rectification | |
US7215723B2 (en) | Demodulator for an amplitude-modulated alternating signal | |
US6731521B2 (en) | Switching power supply circuit | |
JP2702602B2 (en) | Interface circuit using electromagnetic induction coupling | |
JP4708346B2 (en) | Portable object with multiple levels of demodulation and inductively coupled to a fixed station | |
JP2702603B2 (en) | Interface circuit using electromagnetic induction coupling | |
US6828853B2 (en) | Wide dynamic range demodulator for smart cards or contactless tickets | |
JPH10256957A (en) | Device and system for transmitting power | |
JPH11168416A (en) | Radio frequency signal detector for non-contact chip card | |
TW595087B (en) | Circuit framework capable of providing stable clock | |
JP3722496B2 (en) | Power circuit | |
CN100490340C (en) | A circuit framework capable of supplying stable pulse | |
JPH1145319A (en) | Data carrier |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071003 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081003 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 12 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 12 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101003 Year of fee payment: 13 |
|
LAPS | Cancellation because of no payment of annual fees |