JPH04162634A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a point defect from being produced and hence sharply prevent parasitic effect of a transistor device by permitting a region including at least one of first and second conductivity type regions to contain at least one kind of constituent elements in a compound semiconductor layer and elements belonging to the same group in a periodic table. CONSTITUTION:A undoped n-type high resistance substrate is used and an SiO2 film 9 is deposited on a substrate crystal to mask a region excepting a part where an n-channel region 3 is formed. Mg ion for forming a p-type semiconductor region 3 is doped and then Si ion for forming the n-channel region 3 is doped, and finally phophorus ion of the same group as As is doped for preventing As lacking defect from being produced. With use of a photoresist process a part excepting regions for forming a source, a drain, and an ohmic electrode is masked and Si ion is doped. There are manufactured the n-channel region 3, the p-type semiconductor region 4 for blocking a carrier, a source electrode 7, and a drain electrode 7 forming n<+> region 2.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a compound semiconductor device in which a high-performance integrated circuit or the like is fabricated in a compound semiconductor crystal, and a method for manufacturing the same. [Prior Art] It is known that crystal defects that occur in compound semiconductor crystals due to thermal effects during the device fabrication process are mainly point defects due to lack of elements with high vapor pressure. These point defects form deep levels in the semiconductor, lowering the carrier concentration in the active layer and causing a hysteresis phenomenon in the device characteristics, leading to gradual deterioration of device performance. E.B. Stoneham, Jeannie Batterson,
G.M. Gladstone: Radiation Effect 1980, Volume 47, Pages 143-148
Page (E, B, Stoneham, G, A, Pat
terson and J, M, Gladstone:
Radiation Effects, 47 (1980
) Pp, 143-148).

[Problem to be solved by the invention]

The main purpose of the above-mentioned conventional technology is to suppress amphoteric impurities such as Si from occupying acceptor sites, so on the contrary, the composition ratio of newly introduced elements becomes relatively large, resulting in new points. There is a problem in that defects occur, resulting in new element performance deterioration. That is, even if a transistor element is manufactured using the above-mentioned conventional technique, there is a problem in that it is not sufficiently effective in suppressing parasitic effects of the transistor element such as hysteresis phenomenon. An object of the present invention is to provide a compound semiconductor device and a method for manufacturing the same in which the occurrence of point defects, which are a cause of deterioration of device characteristics, is suppressed. [Means for Solving the Problems] The above objects are: (1) a first conductivity type region provided in a compound semiconductor layer and constituting an active region; a second conductivity type region provided in contact with the first conductivity type region; In a compound semiconductor device comprising a gate electrode that controls a current flowing through the first conductivity type region, the region includes at least one of the first conductivity type region and the second conductivity type region. 2. The compound semiconductor device according to claim 1, wherein the first conductivity type region contains an element that is in the same group in the periodic table as at least one of the constituent elements of the compound semiconductor layer. is an n-type region,
(3) The compound semiconductor device according to claim 1 or 2, wherein the second conductivity type region is an n-type region, and at least one of the constituent elements of the compound semiconductor layer and a periodic rule. In the table, the peak position of the concentration of elements in the same group is the peak position of the first conductivity type impurity concentration in the first conductivity type region and the second conductivity type impurity concentration peak position in the second conductivity type region.
(4) The compound semiconductor device according to claim 1.2 or 3, wherein the first conductivity type of the first conductivity type region is present between the peak position of the conductivity type impurity concentration. The maximum concentration of impurity atoms is higher than the maximum concentration of second conductivity type impurity atoms in the second conductivity type region, and the highest concentration of an element that is in the same group in the periodic table as at least one of the constituent elements of the compound semiconductor layer. (5) Claim 2: A compound semiconductor device characterized in that it is smaller than
In the compound semiconductor device described above, the p-type region is P
(6) In the compound semiconductor device according to claim 2, the p-type region contains Be as a p-type doping impurity. Compound semiconductor device (7) In the compound semiconductor device according to claim 2,
(8) A compound semiconductor device according to any one of claims 1 to 7, wherein the n-type region contains Si as an n-type doping impurity, the constituent elements of the compound semiconductor layer The maximum concentration of an element that is homologous in the periodic table to at least one type of
01s101s or more; (9) In the compound semiconductor device according to any one of claims 1 to 8, the compound semiconductor layer has ■-V
(10) A compound semiconductor device according to claim 9, characterized in that the compound semiconductor of the ■-■ group is GaAs, (11) ) The compound semiconductor device according to claim 10, wherein the element that is the same group in the periodic table as at least one of the constituent elements of the compound semiconductor layer is phosphorus, (12) the compound semiconductor device a step of implanting second conductivity type impurity ions into the substrate to form a second conductivity type region;
The first region is implanted with conductivity type impurity ions and forms an active region.
Claims 1 to 1, comprising the steps of forming a conductivity type region and annealing the compound semiconductor substrate.
Achieved by the method for manufacturing a compound semiconductor device according to any one of 1.

[Effect]

As reported in the above-mentioned prior art, point defects that occur due to the deficiency of elements with high vapor pressure due to the thermal influence of the element manufacturing process are caused by introducing an excessive amount of elements that are predicted to be deficient in advance. It can be reduced to a lesser extent. Although the above-mentioned conventional technology suppresses at least one type of point defect, the ratio of the newly introduced excessive element to the homologous element becomes relatively excessive in the crystal, resulting in new point defects. This new point defect also causes a parasitic effect of the transistor element such as a hysteresis phenomenon, and as a result, the effect of suppressing the parasitic effect is reduced. This is because excessively introduced impurity atoms diffuse toward the substrate crystal side during the thermal process during device fabrication, causing point defects in the region adjacent to the channel region, which causes a new parasitic effect on the transistor element. By providing a carrier blocking layer adjacent to the channel region, it was possible to prevent point defects generated in the portion adjacent to the channel region from being involved in transistor operation. [Example] An example of the present invention will be described below with reference to FIG. FIG. 1 shows a field effect transistor consisting of an n-channel region 3 formed on a semi-insulating GaAs substrate crystal 1, a p-type semiconductor region 4 for carrier block provided adjacent to it, a source electrode 7, a gate electrode 8, and a drain electrode 7. FIG. This field effect transistor was manufactured as follows. An undoped n-type high resistance substrate was used as the substrate crystal. First, a 500-layer Si○2 film 9 was deposited on this substrate crystal using a thermal CVD method, and a photoresist process was used to mask the area except for the part where the n-channel region 3 would be formed, in the order shown below. Impurity ions were implanted. First, Mg ions for forming the p-type semiconductor region 4 were heated to an energy of 200ke.
V was implanted at a dose of 2×10”cm−2, and then Si ions for forming the n-channel region 3 were implanted at an energy of 30ke.
V, implanted at a dose of 3×10"cm-", and finally As
Phosphorus ions, which are in the same group as As, were implanted at an energy of 150 keV and a dose of 3×10 cm 7 to suppress void defects. This wafer was again subjected to a photoresist process to mask the area other than the source and drain ohmic electrode formation regions, and Si ions were implanted at an energy of 100 keV and a dose of 3.times.10.sup.13 C-2. After removing all the photoresist by chemical treatment
A 5in2 film 9 of the human body is deposited by thermal CVD, and this is used as a protective film to perform activation annealing at 800°C for 15 minutes in a hydrogen atmosphere to form an n-channel region 3, a P-type semiconductor region 4 for carrier block, An n+ region 2 for forming a source electrode 7 and a drain electrode 7 was produced. This annealing temperature is 7
Temperatures in the range 00 to 900 are preferred. In the figure, 5 indicates a phosphorus ion implantation region for composition control, and 6 indicates n.
It shows the distribution of crystal defects that occur after the channel region is formed and that are involved in the parasitic effects of the transistor element. The impurity concentration profile directly under the gate electrode formed by the above ion implantation and annealing process is as shown in FIG. In the figure, 10 is a Si atomic concentration profile in the n-channel region directly below the gate electrode, 11 is a phosphorus atomic concentration profile immediately below the gate electrode, and 12 is an Mg atomic concentration profile immediately below the gate electrode. In the case of this example, the phosphorus ion implantation amount is lXl0''C11 at the peak concentration.
-” order, and the peak position is between the n-type impurity concentration peak position and the P-type impurity concentration peak position, which suppresses the occurrence of point defects and also prevents the diffusion of carriers toward the substrate crystal side. After the activation of the ion-implanted impurities described above is completed, the Sio2 film 9 of each electrode forming portion is
A gate electrode 8 of Ti/Pt/Au, source and drain electrodes 7 of AuGe/Ni/Au are formed through a vapor deposition process, and MES (MEtal Sem1co) is formed.
A field effect transistor was fabricated. Note that a field effect transistor similar to the above was obtained even when Be ions were used instead of Mg ions for forming the P-type semiconductor region. Further, in the above embodiment, the second conductivity type region is provided in contact with the lower surface of the first conductivity type region (n channel region 3), but even if the second conductivity type region is provided in contact with the upper surface thereof, the same electric field can be obtained. An effect transistor was obtained. In the above embodiments, impurities were introduced through ion implantation and annealing steps, but it goes without saying that other manufacturing methods such as stacking crystals containing impurities may also be used.

【Effect of the invention】

FIG. 3 shows the frequency dependence of the transconductance g+s/g- normalized by the DC values g and e. Conventionally, when GaAs MES field effect transistors are fabricated by the ion implantation method, the curve I! The transconductance (g,) shown by 13 has a large frequency dependence, which has become a serious problem. When phosphorus ions are implanted to compensate for As defects during ion implantation,
As shown by curve 14 in the figure, the frequency dependence of the transconductance can be significantly reduced. On the other hand, song! It is clear that the value corresponding to the embodiment of the present invention indicated by 115 shows that the frequency dependence of the transconductance is greatly suppressed. Now, as shown in Figure 3, the amount of decrease in the normalized transconductance at 100kHz or higher with respect to DC is 6
g wa/g wa", 6 g in this example in which phosphorus ions were implanted and a P-type carrier block layer was provided.
ml g m. can be suppressed by about 50%. On the other hand, in the conventional technology, the suppression amount of 6g1 was 30% at most. That is, by using the element structure of the present invention, the parasitic effects of the transistor element could be increased (improved).Furthermore, the field effect transistor of the present invention could be fabricated with good controllability.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a GaAs MES field effect transistor which is an embodiment of the present invention, FIG. 2 is a diagram showing the impurity atom concentration profile directly under the gate electrode of the field effect transistor, and FIG. 3 is a diagram showing a conventional structure. The normalized transconductance (g m/g m'
). 1...Semi-insulating GaAs substrate crystal 2...N+ region...n channel region 4...p type semiconductor region 5...phosphorus ion implantation region 6...crystal defect 7...source electrode , drain electrode 8... gate electrode 9... SiC2 film 10... Si atomic concentration profile 11... phosphorus atomic concentration profile 12... Mg atomic concentration profile 13.14.15... curve (transformer Frequency-dependent characteristics of conductance)

Claims (1)

[Claims] 1. A first conductivity type region provided in a compound semiconductor layer and constituting an active region, a second conductivity type region provided in contact with the first conductivity type region, and a first conductivity type region flowing through the first conductivity type region. In a compound semiconductor device comprising a gate electrode for controlling current, the region including at least one of the first and second conductivity type regions is in the same group in the periodic table as at least one of the constituent elements of the compound semiconductor layer. A compound semiconductor device characterized by containing an element. 2. The compound semiconductor device according to claim 1, wherein the first conductivity type region is an n-type region, and the second conductivity type region is a p-type region. 3. The compound semiconductor device according to claim 1 or 2,
The peak position of the concentration of an element that is the same group in the periodic table as at least one of the constituent elements of the compound semiconductor layer is:
A compound semiconductor device characterized in that the compound semiconductor device exists between a peak position of a first conductivity type impurity concentration in the first conductivity type region and a peak position of a second conductivity type impurity concentration in the second conductivity type region. 4. In the compound semiconductor device according to claim 1, 2 or 3, the highest concentration of first conductivity type impurity atoms in the first conductivity type region is the highest concentration of second conductivity type impurity atoms in the second conductivity type region. , and lower than the maximum concentration of an element that is in the same group in the periodic table as at least one of the constituent elements of the compound semiconductor layer. 5. The compound semiconductor device according to claim 2, wherein the p
A compound semiconductor device characterized in that the type region contains Mg as a p-type doping impurity. 6. The compound semiconductor device according to claim 2, wherein the p
A compound semiconductor device characterized in that the type region contains Be as a p-type doping impurity. 7. The compound semiconductor device according to claim 2, wherein the n
A compound semiconductor device characterized in that the type region contains Si as an n-type doping impurity. 8. In the compound semiconductor device according to any one of claims 1 to 7, the maximum concentration of an element that is the same group in the periodic table as at least one of the constituent elements of the compound semiconductor layer is 1 x 10^1^8 cm. A compound semiconductor device characterized in that it is ^-^3 or more. 9. The compound semiconductor device according to claim 1, wherein the compound semiconductor layer is made of a III-V group compound semiconductor. 10. The compound semiconductor device according to claim 9, wherein the above
A compound semiconductor device characterized in that the III-V compound semiconductor is GaAs. 11. The compound semiconductor device according to claim 10, wherein the element that is in the same group in the periodic table as at least one of the constituent elements of the compound semiconductor layer is phosphorus. 12. Step of implanting second conductivity type impurity ions into the compound semiconductor substrate to form a second conductivity type region; implanting first conductivity type impurity ions to form a first conductivity type region constituting an active region. 12. The method for manufacturing a compound semiconductor device according to claim 1, further comprising a step of annealing the compound semiconductor substrate.