JPH0364029A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device, in which leakage current is reduced even under a temperature lower than the room temperature, by forming an impurity introducing layer having the same conductivity type as a semiconductor substrate and higher concentration around a P-N junction shaped on the surface of the substrate, and a halogen-element introducing layer in a region deeper than the impurity introducing layer. CONSTITUTION:An impurity introducing layer 3 having conductivity type different from a semiconductor substrate 1 is formed around a P-N junction 2 shaped on the surface of said substrate and a halogen-element introducing layer 4 is formed in a region deeper than said impurity introducing layer 3. When the P-N junction 2 is biassed in reverse direction, said impurity introducing layer 3 inhibits extension of depletion layer under the P-N junction 2 and prevents diffusion of minority carriers under said depletion layer. The halogen- element introducing layer 4 prevents thermal expansion of the layer 3 at the time of heat treatment for forming the impurity introducing layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a pn junction with low leakage current and a method for manufacturing the same.

[Conventional technology]

In a conventional semiconductor device, a well layer and a buried layer are formed around a pn junction in a source/drain region of a MOS transistor, as described in Japanese Unexamined Patent Publication No. 63-244665. The well layer is formed by implanting impurities into the substrate surface and subsequent thermal diffusion, and the buried layer is formed by epitaxial growth after impurity diffusion.

Further, as described in Japanese Patent Application No. 63-270652, the well layer and buried layer around the pn junction were formed by high energy implantation. The amount of impurity implanted at this time is determined to prevent the negative effects of residual defects after heat treatment.
It was about I x 10"/cd or less.

[Problem to be solved by the invention]

In the former conventional technology mentioned above, the performance of the constituent circuits has been improved.

Although high reliability was achieved, no consideration was given to reducing the leakage current of the pn junction, and there was a problem that the leakage current increased when the semiconductor device was used at a high temperature of about 100°C. In addition, although the latter conventional technology was able to reduce the leakage current at high temperatures to about one-third, there was a problem in that it was impossible to further reduce the leakage current because there was a limit to the amount of impurity implanted. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that not only significantly reduces the leakage current at high temperatures, but also reduces the leakage current at low temperatures, about room temperature or lower.

[Means to solve the problem]

In order to achieve the above object, the present invention provides, as shown in FIG. , an impurity-introduced layer 3 having a higher concentration than the surface side of the substrate 1, and a halogen element-introduced layer 4 in a region deeper than the impurity-introduced layer 3.

Further, as shown in FIG. 1(b), an impurity-introduced layer 5 having a conductivity type different from that of the substrate is provided around the pn junction 2;
A halogen element introduced layer 4 is provided in a region deeper than the impurity introduced M5.

Here, the above halogen elements are fluorine and chlorine.

Either bromine or iodine.

Furthermore, ion implantation and subsequent heat treatment are used to form the impurity introduced layers 3 and 5 and the halogen element introduced layer 4. This ion implantation and subsequent heat treatment may be performed either before or after forming the pn junction. Further, in forming the impurity-introduced layers 3 and 5 and the halogen element-introduced layer 5, it is possible to ion-implant the impurities and the halogen element at the same time, and then heat-treat the impurities and the halogen element. It is also possible to ion-implant the halogen elements separately and perform heat treatment after each ion implantation.

[Effect]

When the pn junction 2 formed on the surface of the semiconductor substrate 1 is biased in the opposite direction, the impurity-introduced layer 3 suppresses the expansion of the depletion layer under the pn junction 2, and also suppresses the expansion of the depletion layer under the pn junction 2. It acts to prevent carrier diffusion. Further, the halogen element introduced layer 4 under the impurity introduced layer 3 prevents the impurity introduced layer 3 from spreading during the heat treatment for forming the impurity introduced layer 3 and the subsequent heat treatment, and also prevents the spread of the impurity introduced layer 3 in the depletion layer. , an insulating film 6 around the pn junction 2
It acts to reduce the level at the center of generation and recombination of minority carriers at the interface between the substrate 1 and the substrate 1 .

Further, similarly to the above, the impurity introduced layer 5 is.

It acts to shorten the diffusion length of minority carriers in the depletion layer, and the halogen element introduced layer 4 of the impurity introduced layer 5 acts in the same manner as described above.

From the above, it is possible to simultaneously reduce the leakage current components of the pn junction 2 biased in the reverse direction, which are due to zero generation/recombination and due to diffusion. The leakage current due to the above generation and recombination dominates the leakage current of the pn junction when the operating temperature of the semiconductor device is about room temperature or lower, and the leakage current due to the above diffusion dominates when the operating temperature is as high as about 100°C. Since this governs the leakage current of the pn junction,
The semiconductor device of the present invention can reduce leakage current at any operating temperature.

Furthermore, when forming the impurity-introduced layers 3 and 5 by ion implantation, residual defects may exist even if heat treatment is performed after ion implantation, and the defects may reach the pn junction and increase leakage current. However, the presence of the halogen element introduction layer 4 during the heat treatment after the impurity implantation prevents the defects from reaching the pn junction.

Therefore, even when the impurity-introduced debris 3 and 5 are formed using ion implantation, the defects are not created in the active region of the semiconductor substrate due to the effect of the halogen element.

〔Example〕

Embodiments of the present invention will now be described with reference to FIGS. 2 to 5.

[Embodiment 1] The present invention is applied to a dynamic random access memory (1) R
An example in which the present invention is applied to an AM) element and its manufacturing method will be described with reference to FIGS. 2 and 3.

cz, (100) plane orientation, resistivity 10Ω.

A p-type well layer 8 formed by thermal diffusion with a surface concentration of 2×101 B/d and a silicon oxide film (S iOx film) 9 and the above 5iOz[9
Element isolation consists of a p-type layer 10 with a concentration of 2X1017/a# at the bottom, and a film thickness of 30 mm formed by thermal oxidation method.
After forming a 5ins film 11 of 5 nm, boron (B) was added to 0.
．． The ion implantation layer 12 was formed by implanting ions of 1×10"4/cI# at 8 MeV.

Thereafter, fluorine (do) was ion-implanted at 3 M e V by lXl0'/d to form a do implantation layer 13 (
Figure 2(a)).

This was followed by heating at 10°C in a dry nitrogen atmosphere (N2).
A heat treatment was performed for 0 minutes to electrically activate the B implantation layer 12 to form a high concentration p-wall buried layer 14. After forming a gate 5iOz film 15 with a film thickness of 18 nm, a phosphorus CP> Doped polycrystalline Si with a thickness of 300 nm
Form the electrode 16 and apply Him(As) to lX at 100ksV.
After ion implantation by 10"/ai, 10"/ai was implanted in N2.
00℃.

A heat treatment was performed for 60 minutes to form an n-type layer 17.

Furthermore, the second gate electrode 18 is formed by polycrystalline 5iW4 doped with phosphorus, and As is
Ion implantation was performed by ×105 B/d at 950°C in Nz.
A heat treatment was performed for 10 minutes to form an n◆ type layer 19 (FIG. 2(b)).

Next, phosphorus glass [20] with a film thickness of 500 nm was deposited,
After drilling contact holes for electrodes, aluminum (AQ
) The electrode 21 was formed and l) a RAM element was manufactured (second
Figure (Q') ).

According to this embodiment, compared to the case where the B implantation layer 12 and the F implantation layer 13 are not formed,
There were effects like 1) to (4).

(1) The leakage current in the bulk components of the n-type layer 17 and the n-type layer 19 is 9M from room temperature (approximately 27°C) to 150°C.
We were able to reduce this by more than an order of magnitude.

(2) The leakage current at the end of the selective oxide film 9 of the n-type layer 17 and the n-type layer 19 is 2.
It was possible to reduce it by about 0 to 40%.

(3) The hot carrier resistance of MO3F14T was improved by about twice.

(4) MO3? ``We were able to improve the drain breakdown voltage of the HiT by about 1V.

The above effects can lengthen the information retention time of the memory device, contributing to improving the reliability of the device. especially,
The information retention time can be increased when the operating temperature of highly integrated elements is high.

Further, according to this example, the following effects (5> to (8)) were obtained compared to the case where the F implantation layer 13 was not formed.

(5) In the case of the above implantation amount for forming the B implantation layer 12, there are many residual defects after heat treatment, so the n-type [1
7 and the n-type layer 19, whereas the junction breakdown voltage is significantly lower, there is no deterioration in the junction breakdown voltage.

(6) The leakage current in the bulk components of the n-type J1117 and the n-type 19 can be reduced by one order of magnitude or more at room temperature. Incidentally, on the still-temperature side, the respective differences are no longer observed.

(7) The spread of the distribution of the p-type grains 14 can be suppressed, and a steep grain M distribution as shown in FIG. 3 can be obtained.

(8) In order to avoid the influence of residual defects on the -1111-112-111-112-11-11-11-11-11-11-11-11-11-11-11-11-11-11-11-11-11-11-11-11-11-11-20-11-12-11-12-12
Although it has been suppressed to below I.sub.X I Qi4/d or more, it is possible to manufacture devices without the influence of residual defects.

The above-mentioned effects make it possible to easily select the conditions for forming the p-wall buried N14, and to realize device fabrication without deterioration of the junction characteristics.

[Embodiment 2] The present invention is applied to a static random access memory (
The fourth example shows the implementation of the SRAM) element and its manufacturing method.
This will be explained using FIG. 5.

Using a Si substrate 22 with the same specifications as in Example 1 above, a p-type well layer 2 with a surface concentration of 2×10”/d and a depth of 3 μm is used.
3, and the surface concentration is 5X1016/d and the depth is 3μ
After forming an n-type well layer 24 of m by thermal diffusion method,
After forming element isolation with the same specifications as in Example 1 above, a 5iOz film 25 with a thickness of 20 nm was formed.
P is ion-implanted at 3 M e V with a thickness of 5×10”/ffl, and F is ion-implanted with 5×10 steps/d at 4 M e V to form an F implantation layer 26-2. (Figure 4(a)).

Next, heat treatment was performed at 1000°C for 30 minutes in Nz,
After forming the n-type buried layer 27, a gate 5ift film 28 with a 1M thickness of 10 nm and a phosphorus-doped film 28 with a thickness of 200 nm are formed.
A gate polycrystalline Si electrode 29 with a thickness of 100 nm was formed (see FIG.
b)).

After that, As and boron fluoride () (F) were added to 25
After ion implantation by k s Vte2 After depositing the phosphor glass film 32, a contact hole is opened, an Aff electrode 33 is formed, and the S
I want to fabricate a RAM element (Fig. 4(C)).

According to this embodiment, the following effects (1) and (2) were obtained compared to the case where the n-type buried layer 26 was formed by thermal diffusion.

(1) By using ion implantation in the n-type buried M26 type layer, a p-type well layer with about 50% lower resistance could be formed without lowering the concentration of the p-type well layer 23 (Table 2). . Therefore, there is no difference in the threshold voltage of MO8l'l+T when there is an n-type buried layer 27 under the p-type well layer 23 and when there is no n-type buried layer 27, and the formation conditions for the P-type well layer 23 are Since it can be selected independently of the formation conditions of N27, process design becomes easy. Furthermore, since the parasitic bipolar operation based on the p-type well layer 23 can be suppressed, the noise current level required for 0MO8 latch-up to occur can be approximately doubled.

(2) An n-type buried layer 27 with a low resistance of about 1/10 was formed. Therefore, MO8? with the p-type layer 31 as the source/drain? ``The drain breakdown voltage of the E-type can be improved by about 0.5 mm, and the parasitic bipolar operation based on the n-type buried layer 27 can be suppressed.

As a result, it is possible to reduce the holding voltage at which latch-up of 0MO8 occurs, thereby providing greater resistance to substrate noise.

Also, compared to the case where there is no C entry, (3) of the C entry
There were effects as shown in ~(6).

(3> The distribution spread of the n-type buried layer 27 could be reduced as shown in FIG. 5. As a result, the MOS ?' ?4
It was possible to suppress the fluctuation in the threshold value of T and the increase in resistance of the p-type well layer 23.

(4) Normally, under the above F implantation conditions, residual defects are generated after heat treatment, resulting in significant deterioration of bonding properties, but by F implantation, the influence of residual defects could be eliminated.

(5) The leakage current of the bulk component in the n-type layer 30 and the p-middle layer m31 could be reduced to about 115, and the leakage current around the selective oxidation 1IA9 could be reduced to about 1/2.

(6) The hot carrier life of each MOS-type MT could be approximately doubled.

As described above, in this example, it was possible to improve the corrosion performance and reliability of the SRAM element, and also to simplify the element manufacturing process and achieve island control.

Note that in this embodiment, only F implantation was described, but F
The same halogen elements chlorine, bromine, and iodine have similar effects. However, in consideration of damage during implantation, the light element Do is a desirable element.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the leakage current of the pn junction, improve the drain breakdown voltage of the MO8 element, improve the hot carrier resistance of the MO8 element, and improve the latch-up resistance of the 0MO8 element, thereby achieving high performance. It is effective in providing crystal reliable elements.

In addition, it is possible to form a buried layer with a high quality concentration without the influence of residual defects from implantation, and it is possible to suppress the spread of the distribution, which is effective in simplifying the buried layer formation process and improving controllability. .

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the basic configuration of the present invention, FIG. 2 is a sectional view showing the L) RAM element manufacturing process of the embodiment of the present invention,
Figure 3 is a distribution diagram of boron (B) concentration in the p-type buried layer,
FIG. 4 is a cross-sectional view showing the SRAM element manufacturing process, and FIG. 5 is a distribution diagram of phosphorus (P) concentration in the n-type buried layer. 1... Semiconductor substrate, 2... PN junction, 3... Impurity introduced layer having the same conductivity type as the semiconductor substrate, 4... Halogen element introduced layer, 5... Impurity having a different conductivity type from the semiconductor substrate. Introduction layer, 6... Absolute film, 7, 22... P-type silicon substrate, 8.23... P-type well pair, 9, 11, 15
゜25.28...Silicon oxide film, 10...P type channel stopper layer, 12...Boron implantation layer, 13゜26-2...Fluorine implantation layer, 14...P type buried layer, 16.18,29...Gate polycrystalline silicon film. 17-n type layer, 19.30-n+ type layer, 20°32.
...phosphorus glass film, 21. :3:3... Aluminum electrode, 24... N-type well layer, 26-1... Phosphorus implantation layer, 27... N-type buried layer, 31... P◆ type layer. Whisper! Mouth 2nd concave (a) 2nd (2) (Suto 4 Sand (0,) (1)) (0)

Claims (1)

[Claims] 1. A material having the same conductivity type as the semiconductor substrate and having a higher concentration than the concentration on the surface side of the semiconductor substrate is formed around the pn junction formed on the main surface side of the semiconductor substrate. 1. A semiconductor device comprising: an impurity-introduced layer; and a halogen element-introduced layer in a region deeper than the impurity-introduced layer. 2. A semiconductor device characterized in that an impurity-introduced layer having a conductivity type different from that of the substrate is provided around a pn junction on a substrate, and a halogen element-introduced layer is provided in a region deeper than the impurity-introduced layer. 3. The semiconductor device according to claim 1 or 2, wherein the halogen element is selected from fluorine, chlorine, bromine, and iodine. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity-introduced layer and the halogen element-introduced layer are formed by ion implantation and subsequent heat treatment.