JPH04160431A - Numeral decision device - Google Patents

Abstract

PURPOSE:To eliminate the need to reset a range value from outside the device, to shorten the processing time and to improve the throughput by providing a decision control circuit, etc., and deciding a numeral by combining comparison results of numeral elements. CONSTITUTION:A range value A memory 12a and a B memory 12b are stored with range values A and B to be compared with the value to be decided and a comparator 14 makes a one-bit comparison between the value to be decided and the value A or B. A comparison condition memory 17 is stored with conditions for deciding 'coincidence' according to the comparison result and a comparison control circuit 18 compares the comparison result between the value to be decided and the value A or B according to the contents of a memory 17. A decision condition memory 21 makes a decision by combining results of comparisons with plural numeral elements and is stored with the conditions for deciding 'coincidence' finally and a decision control circuit 22 decides the results of comparisons with the numeric elements according to the contents of the memory 21 and the decision result is outputted through a decision result output line 23. Consequently, the processing time is shortened and the throughput is increased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a numerical determination device that can continuously determine the size of a numerical value and whether or not it matches a plurality of numerical specifications by combining the same determination. It is related to.

[Conventional technology]

FIG. 2 shows a conventional numerical determination device of this type.

In FIG. 2, 30 indicates the determined value and the range value A.

This is a comparison stage that compares B in units of predetermined bits (in units of 1 bit in this device). 12b is a second range value memory that also stores another range value B, and 14 is the value to be determined and the range value. A comparator that performs a 1-bit comparison with A or range value B; 15 and 16 are a decision signal line and a logic large signal line that transmit the comparison results, respectively; Is it different from (1) or not (0
), and the logic large signal line 16 is a signal line that indicates whether the value to be determined is larger than the range value A or B (1) or not (0).

13 is a signal transmission control circuit that controls the transmission of these two signals from each comparison stage; 17 is a determined value and a range value A;
18 is a comparison condition memory that stores the conditions for determining a "match" based on the comparison results between the target value and the range values A and B. Comparison control circuit that compares according to the contents of 17, 1
9 is a comparison result output line that outputs the comparison result to the outside of the device; 2
0 is a clock generation circuit that supplies the signal transmission control circuit 13 with timing common to the device.

Next, the operation will be explained.

In FIG. 2, the judged value input line 11 is a signal line that inputs binary digitized data to be judged by this device, and of the two lines in the figure, the one on the left has a larger numerical weight. . That is, when there are n determined value input lines 11, the leftmost line has a weight of 2''-1, and the rightmost line has a weight of 2° (=
1). Range value A memory 12a
, the range value B memory 12b is a memory that stores a binary value to be compared with the determined value, and has the same weighting as the determined value input line 11. Note that range values that serve as conditions for determination are set in these two memories before the start of operation of this device.

These two range values A and B are set to have the following relationship.

Range value B≦range value A The comparison condition memory 17 is used to store, before the apparatus starts operating, the conditions for determining a match based on the comparison results between the determined value and range values A and B. It holds the 2-bit data shown in the table below.

Table 1 (Part 1) Table 1 (Part 2) Note that the clock generation circuit 20 generates a clock signal for synchronizing the device, and this clock signal is supplied to the signal transmission control circuit 13.

First, the to-be-determined value input to this device is input to the to-be-determined value input line 11.
is inputted to the comparator 14 by. The value to be determined to be input at this time is delayed one cycle at a time in advance from the left side of the data bits in synchronization with the clock signal from the clock generation circuit 2°. That is, 1 compared to the bit on the left side of the value to be determined.
Input with a cycle delay, and then delay one cycle at a time to the right. When the data bit length is n, the rightmost bit is inputted with a delay of (n-1) cycles compared to the leftmost bit.

The value to be determined is input to two comparators 14 by the value input line 11 to be determined.
are input into the range value A memory 12a and range value B, respectively.
It is compared with each location in the memory 12b.

The comparison results are input to the signal transmission control circuit 13 as two signal lines, a decision signal line 15 and a logic high signal line 16, respectively.

The comparator 14 changes the contents of the decision signal line 15 and the large logic signal line 16, which are its outputs, based on the content of the decision signal line 15 input to the comparator and the determination result thereof. When the input determination signal line 15 is 1 (high), that is, "determined", the comparator 14 inputs the contents of each input signal line regardless of the comparison result between the determined value and range value A or range value B. is output as is to the decision signal line 15 and the logic large signal line 16 for output. In addition, if the input decision signal line 15 is O (low), that is, [undecided J, the comparator 14 outputs the decision signal line 15 for output and the logic The contents of the value signal line 16 are changed as shown in the table below.

Table 2 (Note) In Table 2, range value is range value A or range value B.
means.

The signal transmission control circuit 13 transmits the signals on each of the two signal lines to the next-stage comparator 14 in synchronization with the clock signal from the clock generation circuit 2°.

At this time, the data bit of the value to be determined is inputted to the next stage comparator 14 with a delay of one cycle.

The comparator 14 similarly transmits the comparison results between the determined value and the range values A and B through two signal lines, a decision signal line 15. A logic large signal line 16 is output.

Thereafter, bits on the right side are sequentially compared in the same way.

Also, at this time, the comparator 14 of one left bit receives the next determined value and starts comparison.

In this way, after the two signal lines have passed through all the comparators 14, they have a comparison result between the determined value and range value A or range value B.

This state is shown in Table 3.

(Hereinafter, blank spaces) Table 3 (Note I) Range value refers to range value A or range value B.

(Note 2) The case where the decision signal = o and the logical large signal = 1 does not exist due to the circuit configuration.

The comparison control circuit I8 controls the contents of the judgment result output line 19 according to the contents of the comparison condition memo river 7 and the states of the two sets of signal lines, the decision signal line 15 and the logic large signal line 16.

This state is shown in Table 4.

Table 4 (Part 1) Table 4 (Part 2) Table 4 (Part 3) Table 4 (Part 4) The comparison result output line 19 is for transmitting the comparison result of this device to the outside. Note that, as described above, in this device, the determination signal = 0. Is there no case where the logical large signal = 1?
In order to prevent the device from malfunctioning even if such a combination of signals is input, the determination signal is set to 0. The judgment result output is also set for the logical large signal -1.

Since the present device is configured as described above, the result is output with a delay of the number of cycles corresponding to the bit length of the value to be determined. However, after that, the determination result of the next determined value is output for each cycle.

[Problem to be solved by the invention]

Conventional numerical determination devices are configured as described above, so when it is necessary to combine and make a determination by comparing multiple numerical specifications, that is, when the numerical specification X (for example, height) is within the range and the numerical When determining whether the specification Y (for example, body weight) is within the range, it is necessary to perform these determinations sequentially using an external device, and even if the system is configured so that the determination results can be output for each cycle. However, there was a problem in that the final judgment took a long time.

This invention was made to solve the above-mentioned problems, and it has a high throughput rate that can simultaneously compare multiple numerical specifications and make judgments by combining the comparison results for each cycle. The purpose is to obtain a numerical determination device.

[Means to solve the problem]

A numerical determination device according to the present invention includes a plurality of numerical determination device bodies, compares a plurality of numerical specifications in synchronization with the same clock generation circuit, and makes a determination by combining the comparison results with the plurality of numerical specifications. Each comparison stage is newly provided with a determination control circuit for performing the determination, a determination condition memory for storing the determination conditions, and a determination result output line for outputting the determination results to the outside of the apparatus.

[Effect]

In this invention, the determination control circuit performs a determination combining the comparison results with each numerical specification, that is, a logical sum, a logical product, etc., so that a high-throughput determination can be performed by combining the comparisons of multiple numerical values. It can be done in trays. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a numerical determination device according to an embodiment of the present invention. In the figure, 11 is a determined value input line for inputting a determined value into the device of this embodiment, and 12a is a line for inputting a determined value to a range value to be compared with the determined value. 12b is a range value B memory, 14 is a comparator that performs a 1-bit comparison between the value to be determined and range value A or range value B, and 15 and 16 are each transmitting the comparison results. A decision signal line and a logic large signal line.

13 is a signal transmission control circuit that controls the transmission of these two signals; 17 is a comparison condition that stores a condition for determining "match j" based on the comparison result between the determined value and range value A and range value B; 18 is a comparison control circuit that compares the comparison results between the determined value and range value A and range value B according to the contents of the comparison condition memo IJ 17; 19 is a comparison result signal line that transmits the comparison results; 20 is a signal This is a clock generation circuit that supplies common timing to the transmission control circuit 13.

In addition, 21 is a judgment condition memory that stores the conditions for determining a match J by combining the comparison results with multiple numerical specifications, and 22 is a judgment condition memory that stores the conditions for determining a match J. 22 is the comparison result with multiple numerical specifications. A determination control circuit makes a determination according to the contents of the determination condition memory 21, and 23 is a determination result output line that outputs the determination result to the outside of the apparatus.

Next, the operation will be explained.

In FIG. 1, the judged value input line 11 is a signal line for inputting binary digitized data to be judged by this device, as in the case of the prior art, and in FIG. Let's make it big.

That is, when there are n determined value input lines 11, the leftmost line has a weight of 2s-1, and the rightmost line has a weight of 2' (=1). The range value A memory 12a and the range value B memory 12b are memories for storing binary values to be compared with the determined value, and have the same weighting as the determined value input line 11, as in the case of the prior art. Note that in these two memories, that is, the range value A memory 12a and the range value B memory 12b, range values serving as conditions for determination are set before the start of operation of the apparatus. These two range values A and B are set to have the following relationship.

Range value B≦range value A Similar to the conventional technology, the comparison condition memory 17 stores the conditions for determining "match" based on the comparison results between the value to be determined and range values A and B. The settings shall be made in the memory stored before the start of operation of this device. The clock generation circuit 20 generates a clock signal for synchronizing the apparatus, and this clock signal is supplied to the signal transmission control circuit 13.

First, a determined value to be determined by this device is input to the comparator 14 through the determined value input line 11.

At this time, the input target value is delayed one cycle at a time in advance from the left side of the data bits in FIG. 1 in synchronization with the clock signal from the clock generation circuit 20.

That is, the input timing of the second bit from the left side of the value to be determined is delayed by one cycle compared to the bit on the leftmost side, and thereafter is delayed by one cycle to the right side. Therefore, when the bit length of data is n, the rightmost bit is inputted with a delay of (n-1) cycles compared to the leftmost bit.

The bit data of the value to be determined inputted to the present device is inputted to two comparators 14, and compared with range value A and range value B stored in range value A memory 12a and range value B memory 12b, respectively. The comparison results are transmitted to the signal transmission control circuit 13 through two signal lines, ie, a decision signal line 15 and a logic high signal line 16. As in the case of the prior art, the signal transmission control circuit 13 synchronizes with the clock signal from the clock generation circuit 20 and transfers a pair of signals from two signal lines, a decision signal line 15 and a logic large signal line 16, to the next comparator. control the timing of transmission.

At this time, the next bit data of the value to be determined is input to the next stage comparator 14 with a delay of one cycle. Next stage determiner 14
Similarly to the comparator 14 in the previous stage, it compares the value to be determined with the range value A and the range value B, and outputs the comparison results through a pair of signal lines, a decision signal line 15, and a large logic signal line 16, respectively. .

Also, at this time, the comparator 14 at the previous stage inputs the determined value at the next stage and performs comparison.

Thereafter, the comparison of all bits between the value to be determined and range value A or range value B is completed while sequentially transmitting the pair of signals, the decision signal line 15 and the logic large signal line 16 to the right bits in the same way.

As in the case of the prior art, the comparison control circuit 18 controls the comparison result signal line 1 according to the contents of the comparison condition memory 17 and the states of two sets of signal lines, the decision signal line 15 and the logic large signal line 16.
Controls the contents of 9. □The above comparison operation is performed simultaneously for a plurality of numerical specifications in synchronization with the clock generation circuit 20.

In FIG. 1, one dimension each is shown symmetrically on the left and right.

The judgment condition memory 21 is a memory that stores conditions for making a judgment by combining the comparison results of a plurality of numerical specifications, and is set in advance before the start of operation of the apparatus.

Table 5 shows the settings.

Table 5 The judgment control circuit 22 controls the contents of the judgment result output line 23 based on the comparison results of a plurality of numerical specifications according to the contents of the judgment condition memory 21, and the status is as shown in Table 6.

The determination result output line 23 transmits the determination result of this device to the outside.

Table 6 (Part 1) Table 6 (Part 2) In this way, in this embodiment, a plurality of numerical determination device main bodies are provided, and a determination is made by combining the comparison results of each of them in each cycle. At first, the determination result is output with a delay of the number of cycles corresponding to the bit length of the determined value, but thereafter, the determined result of the next determined value is output every cycle.

Furthermore, in the above embodiment, the device was constructed by providing a 1-bit comparator like the comparator 14 shown in FIG.
The device can also be constructed using a comparator with multiple bits, such as 3-bit, 3-bit, 4-bit, etc., and the same effect as described above can be obtained.

In addition, in the above embodiment, as shown in FIG. 1, the apparatus was configured to compare and judge two types of numerical specifications. It may be configured to do so.

〔Effect of the invention〕

As described above, according to the present invention, the device is configured so that a numerical value can be determined by combining the comparison results of a plurality of numerical specifications, so that the range value can be reset from outside the device,
Since there is no need to repeatedly use the same numerical determination device, it is possible to provide a numerical determination device with short processing time and high throughput rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a numerical determination device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a numerical determination device according to the prior art. In the figure, 11 is a determined value input line, 12a is a range value A
12b is a range value B memory (second range value memory); 13 is a signal transmission control circuit;
14 is a comparator, 15 is a decision signal line, 16 is a logic large signal line, 17 is a comparison condition memory, 18 is a comparison control circuit, 19 is a comparison result signal line, 20 is a clock generation circuit, 21 is a judgment condition memory, 22 2 shows a judgment control circuit, and 23 shows a judgment result output line. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A device that performs comparative judgment on data converted into binary values, which includes a judgment value input line for inputting the judged value and a comparison target 2 to determine whether the judged value belongs to the range. first and second range value memories that store two range values; a comparator that compares and determines the magnitude of the target value and the two range values for single or multiple bits; signal lines and a signal transmission control circuit that controls the transmission timing of these signals. a comparison stage, a clock generation circuit for synchronizing the signal transmission control circuit of each comparison stage, and a relationship between the determined value and the first and second range values using the output of the final comparison stage as input. a comparison control circuit for determining, a comparison condition memory used for the determination and storing a comparison condition for determining whether or not the determined value and the two range values are in a predetermined relationship, and transmitting the comparison result. a plurality of sets of numerical determination device bodies each having a comparison result output line; a determination control circuit that makes a determination by combining the comparison results of a plurality of specifications from the plurality of numerical determination device bodies; The device is characterized by comprising a judgment condition memory that stores conditions for how to combine the comparison results to make a judgment, and a judgment result output line for outputting the judgment result of the judgment control circuit to the outside of the device. Numerical judgment device.