JPH04158581A - Film transistor - Google Patents

Abstract

PURPOSE:To see that the current path by the carrier of the same conductivity type as those of a source region and a drain region is hard to be made and that the leak current during off is small by elevating the concentration of the impurities of a conductivity type opposite to that of the source region and the drain region, on the side opposite to a gate electrode out of a channel region. CONSTITUTION:In a bottom gate type transistor, a gate electrode 17 is lower than the polycrystalline Si film 12 where a channel region 15 is provided. But, the concentration of the n-type impurities in the channel region 15 becomes higher as it goes away from the gate region 17 in the thickness direction of the polycrystalline Si film 12, so positive holes are hard to generate on the side opposite to a gate electrode 17 out of the channel region 15. Accordingly, the current path by these positive holes are hard to be made, and the operation of the accumulation mode is suppressed, and the leak currents between the source and the drain during off are small. What is more, the concentration of the n-type impurities is low on the side of the gate electrode 17 out of channel region 15, so the inversion layer is not hard to be formed, and the threshold voltage becomes large to negative side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a thin film transistor in which a channel region is provided in a semiconductor thin film on an insulator.

[Summary of the invention]

The present invention reduces leakage current when off by making the impurity concentration of the channel region different between the gate electrode side and the opposite side of the thin film transistor as described above.

[Conventional technology]

As a structure for high integration and low power consumption of MOS-3RAM, stacked CMO uses P-channel thin film transistors as flip-flop load elements instead of resistive load type.
Type 3 is considered.

FIGS. 7 and 8 show a conventional example of a so-called top gate type P-channel thin film transistor.

In this conventional example, a source region 13 and a drain region I4 are formed on a polycrystalline Si film 12 on an SiO
and a channel region 15 are provided.

A gate oxide film 16, which is a 5i02 film, and a gate electrode 17, which is a polycrystalline Si film doped with impurities, are sequentially provided on the polycrystalline Si film 12.

For such thin film transistors, stacked CM0S type S
In order to realize RAM, etc., the current when on is ■. Leakage current I when N is large and off. A characteristic of small FF is required.

[Problems to be Solved by the Invention] By the way, FIG. 9 shows the V6-I characteristics of the conventional example shown in FIGS. 7 and 8.

The downward sloping curve in the left half of FIG. 9 indicates the inversion mode of operation. In this operating region, as in the Nork transistor, as shown in FIG. 7, an inversion layer is formed directly under the gate electrode 17, and this inversion layer becomes a channel through which current flows.

On the other hand, the upward-sloping curve in the right half of FIG. 9 indicates an accumulation mode operation that is not seen in bulk transistors. In this operating region, as shown in FIG. 8, an accumulation layer is formed directly under the gate electrode 17, but holes remain in the side of the channel region 15 that is close to the SiO□ film 11. A current bus is formed by

Therefore, the leakage current when off is I. I instead of FF'. FF becomes large, and as an SRAM, current consumption increases and data retention characteristics deteriorate.

[Means for Solving the Problems] In the thin film transistor according to the present invention, the channel region 15
On the side opposite to the gate electrode 17 and at least in a region near the source region 13 or the train region 14, the concentration of impurities having a conductivity type opposite to that of the source region I3 and the train region 14 is higher than that in the region other than the near region. higher than the concentration in the region of .

[Effect]

In the thin film transistor according to the present invention, in the accumulation mode,
On the side of the channel region 15 opposite to the gate electrode 17, a current bus is difficult to be formed by carriers having the same conductivity type as the source region 13 and the drain region 14.

〔Example〕

Hereinafter, first to fifth embodiments of the present invention applied to P-channel thin film transistors will be described with reference to FIGS. 1 to 6.

1 and 2 show a first embodiment.

This first embodiment is of the so-called bottom gate type, and the gate electrode 17 is located lower than the polycrystalline Si film 12 in which the channel region 15 is provided.

However, in the first embodiment, the concentration of N-type impurities in the channel region 15 increases as the distance from the gate electrode 17 increases in the thickness direction of the polycrystalline Si film 12.

Such a change in the concentration of the N-type impurity may be continuous as shown in FIG. 2A, or may be stepwise as shown in FIG. 2B.

In the first embodiment, holes are less likely to be generated on the side of the channel region 15 opposite to the gate electrode 17 than in the case of FIG. Therefore, a current bus is less likely to be formed by these holes, and the operation in the accumulation mode is suppressed, resulting in less leakage current between the source and drain when off.

Moreover, since the concentration of N-type impurities is low on the gate electrode 17 side of the channel region 15, the formation of an inversion layer does not become difficult (and the dark value voltage does not increase to the negative side).

Note that the concentration of N-type impurities shown in Figure 2 is not the concentration of only N-type impurities, but the concentration of net N-type impurities when compensation is made for impurities.
It shows the concentration of type impurities.

FIG. 3 shows the second embodiment in the manufacturing process. In order to manufacture this second embodiment, a residual polycrystalline Si film 12a with a thickness of about 200 layers is first formed on the SiO□ film 11,
20ke of As'' ions are introduced into this polycrystalline Si film 12a.
The implantation is performed at an energy of about V and a dose of about 5×10” cm −2 .

Next, a remaining polycrystalline Si film 12b with a thickness of about 200 layers is added on the polycrystalline Si film 12a, and then conventionally known processes are performed.

That is, the gate oxide film 16 is grown by CVD, and the polycrystalline S
After growing an i film and patterning the gate electrode, a source region and a drain region are formed by ion implantation of B.
Form electrode wiring using a first grade.

In the second embodiment manufactured in this manner as well, the polycrystalline S1 film 1
The polycrystalline S which is farther from the gate electrode among 2a and 12b
Since the i-film 12a is doped with N-type impurities, holes are generated in the polycrystalline Si film 1.2a, resulting in less leakage current between the source and drain when off.

Also, since the polycrystalline Si film 1.2b is formed after doping the N-type impurity into the polycrystalline Si film 12a,
The process is simpler and easier to control than the case where the impurity concentration is changed in the single-layer polycrystalline Si film 12 as in the first embodiment described above.

Note that arsenic doped into the polycrystalline Si film 12a has a smaller diffusion coefficient than, for example, phosphorus, which is the same N-type impurity.
Moreover, the dose is as small as 5X10” mark -2, so
Difficult to spread. Therefore, this arsenic is less likely to diffuse directly under the gate electrode and affect the threshold voltage.

FIG. 4 shows a third embodiment. In this third embodiment, the polycrystalline Si film 12 in which the channel region 15 etc. are provided is a single layer, but the N region 18 doped with N type impurities in the channel region 5 is a contradictory region. It is provided only in the vicinity of the source region 13 and the train region 14 instead of the entire surface under the region 15 .

In this third embodiment as well, the N 91 region 18 prevents the formation of a current bus due to holes on the side of the channel region 15 opposite to the gate electrode 17 . Therefore, there is little leakage current between the source and the train when it is off.

By the way, if the polycrystalline Si film 12 becomes extremely thin,
In the second embodiment shown in FIG. 3, impurities diffuse from the polycrystalline S1 film 12a into the polycrystalline Si film 1.2b over the entire surface under the gate electrode, causing variations in characteristics such as dark voltage. .

However, in the third embodiment shown in FIG. 4, the N region 18 is provided only in the vicinity of the source region 13 and drain region 14, and the impurity is diffused over the entire surface under the gate electrode 17. Therefore, there is little variation in characteristics such as threshold (!voltage).

FIG. 5 shows a fourth embodiment. This fourth embodiment has substantially the same structure as the third embodiment shown in FIG. 4, except that N region 18 is provided only in the vicinity of drain region 14.

Even in such a fourth embodiment, the same effects as in the third embodiment can be achieved. Note that the N%M region 18 may be provided only in the vicinity of the source region 13.

FIG. 6 shows a fifth embodiment. This fifth embodiment is similar to the second embodiment shown in FIG. This embodiment has substantially the same structure as the fourth embodiment shown in the example and FIG.

Even in such a fifth embodiment, the same effects as in the second and fourth embodiments can be achieved. In this fifth embodiment as well, the N 1,7J region 18 is formed only in the vicinity of the source region 13 and the drain region 14 or in the vicinity of the source region 13.
may be provided.

〔Effect of the invention〕

In the thin film transistor according to the present invention, in the accumulation mode,
On the side of the channel region opposite to the gate electrode, a current path is less likely to be formed by carriers of the same conductivity type as the source region and the train region, so leakage current during off-time is small.

[Brief explanation of drawings]

FIG. 1 is a side sectional view of the first embodiment of the present invention, and FIG. 2 is a side sectional view of the first embodiment of the present invention.
A graph showing the distribution of impurity concentration in the channel region of the example, FIG. 3 is a side sectional view of the second example in the manufacturing process, and FIGS. 4 to 6 are side cross sections of the third to fifth examples, respectively. It is between. 7 and 8 are side sectional views of a conventional example of the present invention in inversion mode and accumulation mode, respectively, and FIG. 9 is a side sectional view of a conventional example of V
It is a graph showing c'-1o characteristics. In addition, in the symbols used in the drawings, 13-1------- Source region 14---11-- Drain region 15----- Channel area 17---1 -----------...Gate electrode.

Claims (1)

[Claims] On the side of the channel region opposite to the gate electrode and at least in the vicinity of the source or drain region, the concentration of impurities having a conductivity type opposite to that of the source and drain regions is higher than that of the region other than the vicinity region. A thin film transistor whose concentration is higher than the above concentration.