JPH04158480A - Minimizing method for incomplete designation sequential circuit - Google Patents

Abstract

PURPOSE:To accelerate processing speed by generating a sequential circuit by generating the characteristic information of a set of pairs of internal states obtained from the data of an inputted state transition table, and selecting and applying the optimum method out of plural methods prepared in advance corresponding to the information. CONSTITUTION:A user inputs a transition table, and obtains the information for a pair of compatibility and a pair of incompatibility to retrieve the maximum compatible class generation program optimum for an inputted transition table by a judgement information generating means 1. A discriminating means 3 applies applies the pair of compatibility to a method when the number of pairs of compatibility is less than that of pairs of incompatability, and the maximum compatible class by the optimum method can be obtained, and the minimum internal state can be obtained. Thereby, the processing speed can be increased by two to five times.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for minimizing sequential circuits, and in particular, a method for minimizing the number of registers, etc. in a circuit by inputting data of a state transition table of the circuit from a terminal. This paper relates to a method for minimizing the number of states for sequential circuits.

[Conventional technology]

Conventionally, this type of method, as shown in FIG. 4, first generates compatible pairs and incompatible pairs from sequential circuit data input from a terminal, that is, state transition table data, in step C2. A fixed program was used for sequential circuits to generate the minimum state without considering circuit-specific characteristics such as the number of compatible pairs and incompatible pairs.

[Problem to be solved by the invention]

However, conventionally, a fixed program, that is, a program that is effective only for data that has circuit-specific characteristics obtained from data in a specific state transition table, is used. A state transition table that is suitable for this method has a high processing speed because it processes only the minimum number of pairs of internal states required, but a state transition table that is not suitable for this method is difficult to minimize the number of states. Processing is performed even if there are no pairs of internal states that are not needed, so the processing becomes redundant, and the processing speed is about 2 to 5 times slower than processing using the optimal method. There is a drawback.

An object of the present invention is to provide an incompletely specified sequential circuit minimization method with high processing speed.

[Means to solve the problem]

The incompletely specified sequential circuit minimization method of the present invention is a method for minimizing an incompletely specified sequential circuit by inputting data of a state transition table of the incompletely specified sequential circuit. A sequential circuit with the minimum number of states is generated by means of generating characteristic information of the set of internal state pairs obtained, and by selecting and applying an optimal method from among a plurality of methods prepared in advance according to the information. It is characterized by having means for

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a configuration diagram for explaining one embodiment of the present invention. As shown in the same figure, it is composed of a judgment information generation means 1, a search means 2, a judgment means 3, an application means 4, and a minimum solution generation means 5. This is a diagram. As shown in the figure, the judgment information generation means 1 includes a transition table input step A1, a compatible pair and incompatible pair generation step A
2, the search means 2 and the determination means 3 have an optimal maximum compatibility class generation program search step A3, the application means 4 has a maximum compatibility class generation step A4, and the minimum solution generation means 5 has It consists of step A5 of generating a minimum state machine.

FIG. 3 is a flowchart showing the configuration of the determining means 3. As shown in the figure, the determining means 3 includes a step B1 of comparing the number of compatible pairs and incompatible pairs obtained from the transition table, a step B2 of determining the configuration state of the incompatible pairs, and a step B3 of selecting method 1.
, selection step B4 of method 2, selection step B of method 3
It consists of 5.

Next, the operation of the present invention will be explained with reference to the drawings.

First, the user inputs a transition table from the transition table input step A1, and the judgment information generation means 1 generates a list of compatible pairs, incompatibles, etc., in order to search for the optimal maximum compatibility class generation program for the input transition table. Obtain information about the number of sex pairs and whether or not they are in an incompatible pair state. Based on this information, the determining means 3 compares the number of compatible pairs and incompatible pairs in step B1, and if the number of compatible pairs is less than the number of incompatible pairs, then in selection step B5 of method 3, compatibility is determined. By applying the pair to method 3, the maximum compatibility class is obtained by the maximum compatibility class generation step A4 using the optimal method, and the minimum internal state is obtained by the minimum solution generation step A5.

As an example, for a state transition table input in which the number of incompatible pairs obtained from the input state transition table is 12 and the number of compatible pairs is 9, the minimum solution is found using the incompatible pairs. The S, R, Das method is used to obtain the minimum solution, and the E, Ftoffer method is used to obtain the minimum solution using compatible pairs. K to do.

E. It cannot be confirmed that the 5toffer method is about twice as fast.

Selection B of method 1 from state determination B2 of incompatible pairs in Figure 3
3. The steps up to selection B4 of method 2 are for explaining the second embodiment of the present invention. This embodiment is the same as the first embodiment except that an incompatibility class is used to generate a maximum compatibility class.

In step B1 of determining the number of compatible pairs and incompatible pairs,
If the number of incompatible pairs is less than the number of compatible pairs, in incompatible pair state determination step B2, if the set of incompatible pairs has all the states and there are no overlapping states. obtains the maximum compatibility class by selection step B3 of method 1; otherwise obtains the maximum compatibility class by selection step B4 of method 2.

To give an example, input a state transition table in which the number of compatible pairs obtained from the input state transition table is 28 and the number of incompatible pairs is 8, and in order to minimize the incompatible pairs, Comparing the processing speeds using the S, R, Das method and the E,5toffer method using compatible pairs, we find that it uses incompatible pairs with a small number of pairs. It was confirmed that adopting the S, R, Das method was about three times faster.

〔Effect of the invention〕

The present invention doubles the processing speed by allowing the system to automatically select the optimal method for generating maximum compatibility classes by simply inputting a transition table by the user. It will be about 5 times faster. Furthermore, by having the system make the decision to select the optimal method,
This has the effect that the user can perform processing without being conscious of the decision.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a flowchart showing the configuration of the determining means 3 of FIG. 1, and FIG. 4 is a flowchart showing a conventional technique. 1... Judgment information generating means, 2... Searching means, 3...
- Determination means, 4... Application means, 5... Minimum group generation means.

Claims (1)

[Claims] In a method for minimizing an incompletely specified sequential circuit by inputting data of a state transition table of the incompletely specified sequential circuit, characteristic information of a set of internal state pairs obtained from the input state transition table data is generated. and a means for generating a sequential circuit with a minimum number of states by selecting and applying an optimal method from a plurality of methods prepared in advance according to the information. Circuit minimization method.