JPH04158480A - Minimizing method for incomplete designation sequential circuit - Google Patents

Minimizing method for incomplete designation sequential circuit

Info

Publication number
JPH04158480A
JPH04158480A JP28484090A JP28484090A JPH04158480A JP H04158480 A JPH04158480 A JP H04158480A JP 28484090 A JP28484090 A JP 28484090A JP 28484090 A JP28484090 A JP 28484090A JP H04158480 A JPH04158480 A JP H04158480A
Authority
JP
Japan
Prior art keywords
compatibility
information
pairs
pair
transition table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28484090A
Inventor
Shigeki Sakai
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP28484090A priority Critical patent/JPH04158480A/en
Publication of JPH04158480A publication Critical patent/JPH04158480A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To accelerate processing speed by generating a sequential circuit by generating the characteristic information of a set of pairs of internal states obtained from the data of an inputted state transition table, and selecting and applying the optimum method out of plural methods prepared in advance corresponding to the information.
CONSTITUTION: A user inputs a transition table, and obtains the information for a pair of compatibility and a pair of incompatibility to retrieve the maximum compatible class generation program optimum for an inputted transition table by a judgement information generating means 1. A discriminating means 3 applies applies the pair of compatibility to a method when the number of pairs of compatibility is less than that of pairs of incompatability, and the maximum compatible class by the optimum method can be obtained, and the minimum internal state can be obtained. Thereby, the processing speed can be increased by two to five times.
COPYRIGHT: (C)1992,JPO&Japio
JP28484090A 1990-10-23 1990-10-23 Minimizing method for incomplete designation sequential circuit Pending JPH04158480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28484090A JPH04158480A (en) 1990-10-23 1990-10-23 Minimizing method for incomplete designation sequential circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28484090A JPH04158480A (en) 1990-10-23 1990-10-23 Minimizing method for incomplete designation sequential circuit

Publications (1)

Publication Number Publication Date
JPH04158480A true JPH04158480A (en) 1992-06-01

Family

ID=17683701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28484090A Pending JPH04158480A (en) 1990-10-23 1990-10-23 Minimizing method for incomplete designation sequential circuit

Country Status (1)

Country Link
JP (1) JPH04158480A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054147A (en) * 2007-07-02 2009-03-12 Cadence Design Systems Inc Method, system, and computer program product for generating automated assumption for compositional verification

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054147A (en) * 2007-07-02 2009-03-12 Cadence Design Systems Inc Method, system, and computer program product for generating automated assumption for compositional verification

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