JPH04157675A - Digital signal recording device - Google Patents

Abstract

PURPOSE:To enable an equipment exclusive to recording to determine whether the operation is proper or not by adding a check code for detecting an error corresponding to a predetermined test signal pattern to a recording signal as an AUX code signal. CONSTITUTION:A test signal pattern for detecting failure diagnosis is generated by a test signal generation means 4 and an output of a test signal generation means 4 is selected as an input signal by a selection means 3 when performing test. Also, a check code corresponding to the predetermined test signal pattern is set as the AUX code signal by a setting means 10 and error detection means 15 and 16 detect presence or absence of errors according to an added recording signal output of the check code, thus enabling presence or absence of the equipment or whether the operation is proper or not to be detected momentarily before shooting with a camera recorder.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to digital signal recording devices such as digital camera recorders.

2. Description of the Related Art In recent years, digital processing of audio and video has progressed rapidly with advances in LSI technology, and audio and video equipment that can record and reproduce digital signals has been actively developed. Among them, rotary head recording type digital VTR
has been developed for a variety of uses, from commercial use at broadcasting stations to home use. VTR for business use
For this purpose, a model suitable for each purpose is required, from outdoor news gathering to studio editing and transmission, and in terms of performance and functionality, specifications are required to suit each purpose.

Among these, camera recorders for outdoor reporting that integrate a camera and a VTR are designed to achieve low power consumption, the ability to operate for as long as possible within the constraints of limited battery capacity, and the ease of movement of the photographer. Two major challenges are weight reduction to reduce the burden of fatigue.

In general, when using a digital method compared to a conventional analog method, simply replacing the analog part with a digital one increases the circuit scale, and with current process technology, it is possible to avoid an increase in power consumption. do not have.

Therefore, in order to solve the above-mentioned problems, a digital camera recorder eliminates a large-scale playback circuit in its circuit configuration, has only the minimum necessary recording function, and achieves low power consumption and weight reduction.

Generally, with video camera equipment, if it is not known whether the equipment is malfunctioning or operating normally before taking a picture, it may happen that what you thought was a decisive moment was not actually captured.

The most reliable way to check whether the cassette is working properly is to take a test shot, then rewind and play it back, and check the playback image using the viewfinder, or insert the cassette into the player and monitor the playback image. There is a way to check this, but it is time-consuming and cannot be said to be an easy method.

An easy way to check is to check only the signal processing part, but connect the recording signal output to the playback signal input, configure a so-called E-E system, and check the camera input image with the viewfinder. There is also a method of inserting a specific signal pattern from the recording signal input and determining whether the reproduced signal output matches the expected value to detect the presence or absence of a failure.This also instantly detects the presence or absence of a failure with fairly high accuracy. can be detected.

Problems to be Solved by the Invention However, in the above-mentioned digital camera recorder,
Since this is a recording-only device that does not have a playback function, failures cannot be diagnosed using conventional methods that use a playback signal processing system.

In view of the above-mentioned problems, it is an object of the present invention to determine whether or not the operation of a recording-only device is normal or not, and to provide a user with the information that there is no problem in using the device for recording.

Means for Solving the Problems In order to achieve the above object, test signal generating means generates a test signal pattern for detecting fault diagnosis;
At the time of testing, selecting means selects the output of the test signal generating means as an input signal; setting means sets a check code corresponding to the predetermined test signal pattern as an AUX code signal; and error detection means for detecting the presence or absence of errors from the recording signal output.

Operation With the above configuration, the present invention inputs the output of the test signal generating means that generates the test signal pattern to the recording signal processing circuit during a test for fault diagnosis, and performs error detection corresponding to the predetermined test signal pattern. A check code for this purpose is set as an AUX code signal and added to the recording signal.

Error detection is performed on the recorded signal output to which the check code has been added, and failure diagnosis can be realized from the results.

Embodiment Hereinafter, a digital signal recording apparatus of the present invention will be explained with reference to the drawings.

FIG. 1 shows a block diagram of the audio processing system portion of a digital signal recording apparatus in one embodiment of the present invention.

In the same figure, 1 is an analog audio signal input terminal, 2 is an A
The D converter 3 is a switch for switching input signals during normal use and during failure diagnosis testing. 4 is a test signal generator that generates a test signal pattern determined for a certain period of time during testing, for example, one field period of a video signal, and is a test signal generator using a feedback shift register.
- By using a series random number generator, it is possible to easily generate complex data patterns with a small-scale configuration. 5 is a microcomputer that performs system control of the entire recording device;
It is possible to transfer arbitrary data to the recording signal processing system and embed this data in the recording signal train as control data. 6 and 7 are A memory and B memory, which are two-page field memories that store audio signals for one field period, and 8 is an address for switching the address supplied to A memory 6 and B memory 7 for each field. A multiplexer 9 is an interface RAM for receiving data asynchronously with the microcomputer 5.

10 is AUX, which is a control code interpolated into the recording signal string.
Additional circuit for the hood, 11 is a timing generation circuit that performs timing processing for the audio signal recording system, 12 is an address counter that supplies write and read addresses to the A memory 6 and B memory 7, and 13 is an error detection and correction circuit. Error correction code generation circuit that generates a correction code; 14 is a demultiplexer (DE-MUX) that divides the recording signal string into two systems; 15 and 16 are CRCC error detection units that detect errors in the recording signal during test mode. 17 and 18 are recording audio signal output terminals, 19
indicates the range included inside the LSI when the entire audio recording signal processing system is configured with one chip of LSI.

FIG. 2 is an example of a configuration diagram of a signal format used in an embodiment of the present invention, which also matches the configuration of data stored in the A memory 6 and the B memory 7.

FIG. 3 is an example of the structure and timing waveform diagram of the recording audio signal output used in one embodiment of the present invention, and shows the signal format at the recording audio signal output terminals 17 and 18.

Next, the operation of this embodiment will be explained using the drawings. 1st
In the figure, an audio signal input from an analog audio input terminal 1 is converted into a digital signal by an AD converter 2, and is temporarily written into an A memory 6 and a B memory 7 via a switch 3.

FIG. 2 shows the structure of audio sample data for one field period and the mapping state on the field memory. For example, in the NTSC system, the video field frequency is 59.
．． 48kHz audio with 94Hz period as one division
800 to 8 per channel when sampled with
01 samples of time-series audio data (Da, D+, ・
..., Dl) represents the arrangement method. Total of 3 blocks (816 samples) consisting of 8 rows x 34 columns
The time-series audio data is interleaved and distributed to the signal slots, and the control code for audio data control (A
UX code: AUXO, . . . , AUX14) is embedded and recorded along with the audio data.

Examples of AUX codes include selection of whether or not to record with pre-emphasis that emphasizes high frequencies on the audio frequency characteristics, audio channel mode information, sampling frequency information, etc. in the AES/EBtJ standard digital audio interface. A common method is to transcribe the specified status information as is and write it to a recording medium.

Furthermore, in FIG. 2, regarding the generation of correction codes for error correction, eight correction codes (Pa, . . . . , P7) is also shown in the vertical direction.

Returning to FIG. 1, the AUX code will be explained. In the same figure, although not shown, the microcomputer 5 that controls the entire system of the recording device sends an AUX code for audio data control to the interface R based on the operation result of the recording device's selection switch and predetermined setting conditions.
Transfer and write to AM9. The interface RAM 9 reads out the set AUX code once per field at the timing of the audio recording processing system supplied from the timing generation circuit 11, and inserts it into the time-series audio data string input by the AUX code adding circuit 10. Some AIJX codes remain initially set and do not change, while others change via the microcomputer 5 if the user changes the settings, and can be freely changed by the microcomputer 5's program.

A memory 6 and B memory 7 alternately in 1 field units.
The audio data and AUX code written in are read out in order to generate a correction code for error detection and correction.

The error correction code generation circuit 13 first initializes internal registers for arithmetic processing according to the timing supplied from the timing generation circuit 11, inputs the read audio data and AUX code, and performs an arithmetic operation based on a predetermined polynomial. Perform the operation to generate an error correction code. The generated error correction code is written into the A memory 6 and the B memory 7 again. In these write and read operations, the clock pulses supplied from the timing generation circuit 11 are counted by the address counter 12, and the clock pulses are supplied as address data to the MUX 8, and the clock pulses are switched and supplied to the A memory 6 and the B memory 7 for each field. Controlled by address signals. That is, according to the address map shown in FIG. 2, discrete interleaved address values are assigned when writing the first time-series audio signal, and then read out in the vertical direction (column direction) when generating the error correction code. Then write,
This is sequentially shifted in the horizontal direction (row direction).

When the generation of the error correction code for one field period is completed, the recorded signal string is read out from the A memory 6 and the B memory 7, and is divided into two systems by the DE-MUX 14.
The recorded audio signal is outputted from the output terminals 17- and 18, is time-division multiplexed with a video signal (not shown), and is actually recorded on a recording medium through addition of a synchronizing signal, modulation processing, parallel-to-serial conversion, etc. .

Figure 3 mainly shows the structure of the digital audio recording signal, and furthermore, part of the shaded area of the data block consisting of the audio data and error correction code shown in Figure 2 is shown horizontally in the figure. An example will be shown in which blocks are sequentially read out in the direction and recorded in two tracks.

Generally, when recording together with a video signal, the amount of data for audio is overwhelmingly smaller, so the method for recording audio data is to group multiple audio blocks together and record them intermittently at the edge of the tape. method is adopted. In the example shown in FIG. 3, recording signal configurations for simultaneous recording on two tracks are shown in (a) and (b) in units of eight data blocks. The block configuration of the recorded signal read out is as follows:
As shown in the figure, the audio data block has a structure in which the AUX code is located at the end of the data string.

The above is the audio recording signal processing system 19 in the normal recording function.
The following is an explanation of the operation of the A memory 6 and the B memory 7, and the operation during a test to realize the fault diagnosis according to the present invention will be described below.

The test signal generator 4 generates M-sequence random numbers as a test signal pattern.
By supplying the initial setting pulse at the beginning timing of the field period, the generated data pattern at each time can be made known. The generated test signal pattern is written to A memory 6 and B memory 7 via switch 3. As mentioned above, since the test signal pattern input to the audio recording signal processing system 19 instead of audio data is known, errors generated from the test signal pattern sequence in the AUX code located at the end of this audio data block are A CRCC (shortened cyclic code) having a detection function is calculated in advance and transferred and set from the microcomputer 5 to the interface RAM 9. The CRCC generated from the test signal pattern sequence is handled by the signal processing system as an AUX code, and is sent to the DE-MUX through the recording signal processing described above together with the test signal treated as audio data.
It is output from 14.

The error detection function using CRCC performs error detection on a block-by-block basis.The data string in a block and the remainder obtained by dividing that data string by a predetermined generator polynomial are used as a check code, and the data is used when checking errors. It is based on the principle that the column and check code are divided again by the original generator polynomial, and if no remainder occurs, it is determined that there is no error.It is generally used as a code with a simple circuit configuration and high error detection ability. There is. The CRCC error detectors 15 and 16 receive the clock pulses supplied from the timing generation circuit 11 and shown in FIG.
Error detection by CRCC is performed at the start timing shown in FIG. 3(d). In addition, Fig. 3(d) and below are shown in Fig. 3(a).
This corresponds to the recording signal shown in >. The output of the feedback shift register inside the CRCC error detectors 15 and 16, which performs division processing, is set to a high level if there is an error, and to a low level if not. Error detection is performed by reading this with a detection pulse supplied from the timing generation circuit 11 shown in FIG. 3(e).

The results are transferred to the microcomputer 5 that controls the system, and the user is finally notified of the presence or absence of a failure.

In the case of camera recorders, the audio recording signal processing system is a one-chip LS119 to achieve compactness, light weight, and low power consumption.
The A memory 6, the B memory 7, and the AD converter 2 generally constitute the audio system of the device. Therefore, the main electrical failures that occur in the audio processing system are defective deterioration of memory and signal processing LSI, disconnection and contact in high-density wiring patterns, and these can be detected with a high probability of failure by error detection according to the present invention. Nothingness can be detected.

Furthermore, since the embodiment shown in FIG. 1 performs processing in units of bytes, it is possible to detect in which bit an abnormality occurs by error detection using CRCC, and it is also possible to investigate the cause of the failure in detail.

The above is an explanation of the operation during the test used for failure diagnosis.
By simply adding the CC error detectors 15 and 16, it is easy to realize an LSI including them without changing the configuration of the original signal processing system.

In the embodiments described so far, we have explained how to implement failure diagnosis using audio signal processing as an example, but this concept can be applied to all recording devices without a playback function and transmitters without a reception function. Yes, even if the target is not audio but video. By using the control hood or user data that is provided separately from the original recording and transmission data, during failure diagnosis tests, an error detection hood corresponding to the test data input to the recording and transmission signal processing system is set to detect the signal. This realizes failure detection in the processing system.

Effects of the Invention As described above, the present invention has the advantage of adding this function to the original recording signal processing circuit in order to instantly detect whether the device is malfunctioning or not and whether it is operating normally before taking a picture with a camera recorder. Highly accurate failure diagnosis can be achieved by simply adding a small circuit to the input/output section without changing the configuration, and it can be easily integrated into an LSI, which is highly effective in making camera recorders smaller, lighter, and lower in power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital signal recording device in an embodiment of the present invention, FIG. 2 is a configuration diagram of a signal format used in the embodiment, and FIG. 3 is a block diagram showing the configuration of a recording signal in the embodiment. It is a timing waveform diagram. 3...Switch, 4...Test signal generator, 5
...Microcomputer, 6...A memory, 7...
B memory, 8...Interface RAM1 10...
・AUX hood addition circuit, 11...timing generation circuit, 15...CRCC error detector, 16...
・CRCC error detection circuit.

Claims (1)

[Scope of Claims] Digitally encoded audio signals, etc., such as video signal fields, etc. are distributed every fixed unit time into a plurality of blocks, and an AUX code signal is provided in the margin of the blocks, and the digital audio signals, etc. A digital signal recording device for recording data with a test signal generating means for generating a test signal pattern for detecting a failure diagnosis; and a selection means for selecting an output of the test signal generating means as an input signal during a test; a setting means for setting a check code corresponding to the predetermined test signal pattern as the AUX code signal; and an error detection means for detecting the presence or absence of an error from the recorded signal output to which the check code has been added; A digital signal recording device that performs failure diagnosis of the recording signal processing system based on detection results.