KR100261079B1 - Analysis of dvc - Google Patents

Abstract

PURPOSE: An analyzing device of a DVC(Digital Video Cassette) system is provided to utilize a recording clock speed and a signal format, and to display an analyzed result on the basis of a standard DVC data format. And the device enables regenerated data to be automatically analyzed, to analyze the performance of an object system. CONSTITUTION: A capture unit(20) captures data regenerated through a DVC(Digital Video Cassette) system(10), or transmits captured data to an analyzing unit(40). The operation of the capture unit(20) is decided according to a mode setting signal provided from the analyzing unit(40). An interface unit(30) interfaces the capture unit(20) and the analyzing unit(40). The analyzing unit(40) compares original data with captured data according to loaded programs, to analyze waveform, error rate and jitter. A graphic processor(50) receives analysis data generated according to an analyzed result of the analyzing unit(40), to generate a video signal displayed to a user.

Description

Analysis device of digital video cassette system

The present invention relates to an analysis apparatus of a digital video cassette (DVC) system, and more particularly, to record predetermined data through a DVC system to be analyzed, and to reproduce data reproduced through the DVC system. The present invention relates to an analysis apparatus capable of performing error comparison during reproduction, calculating analysis data of a servo control system, and the like, in comparison with data.

In digital recording / playback systems such as DVC, Compact Disk-ROM (CD-ROM), and Digital Video Disk (DVD), measurement equipment that analyzes the bit stream during recording / playback is an oscilloscope or logic analyzer ( logic annalizer).

However, they were not designed to fully reflect the clock speed and signal format of each system, so only limited measurements were possible. For example, a logic analyzer can compare the waveforms, timings, etc. of two bit streams, but the range in which the original data compared with the reproduced data can be set is narrow, and it is difficult to compare and analyze continuously. Furthermore, in order to obtain statistics by dividing the difference between the two bit streams, for example, by bit error intervals, a process such as a calculation that combines observation or segmented measurement results is separately required.

In addition, since it provides only its own standardized monitor screen, it is difficult to construct an analysis screen suitable for DVC. For example, the position currently being analyzed cannot be expressed relative to the original data, and it is difficult to graph the error rate or the like.

Moreover, it is not possible to automatically analyze the reproduced data and analyze the performance of the system being measured from various angles.

The present invention has been made to solve the above problems, and an object thereof is to provide an analysis system sufficiently reflecting the recording clock speed and signal format of a DVC system.

Another object of the present invention is to provide an analysis apparatus for displaying the analyzed result based on a standardized DVC data format.

It is still another object of the present invention to provide an analysis device capable of automatically analyzing reproduced data to analyze the performance of a system to be measured from various angles.

1 shows a sync block of a DVC.

2 is a block diagram showing a simplified configuration of an analysis device according to the present invention.

3 is a block diagram showing a detailed configuration of the capture unit shown in FIG.

4 is a block diagram showing a detailed configuration of the analysis unit shown in FIG.

FIG. 5 is a block diagram illustrating a detailed configuration of the buffer shown in FIG. 4.

6 is a flowchart showing the operation of the apparatus shown in FIG.

7 shows an example of a screen displayed through the display device.

In the analysis apparatus of the DVC system according to the present invention for achieving the above object is a device for recording predetermined data through the DVC system to be analyzed, and comparing the data reproduced from the system with the original data, A capture unit for capturing or transmitting data reproduced from the DVC system; An analysis unit for comparing and analyzing the reproduced data transmitted through the capture unit and the original data; And a graphic processor configured to display the result analyzed by the analyzer.

The analysis apparatus of the present invention having the above-described configuration may provide an analysis apparatus that considers the clock speed and signal format of the DVC system by recording predetermined data through the DVC system and then comparing the reproduced data with the original data. . Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In the DVC system, one frame of data is recorded in 10 tracks in the NTSC system. Video / audio data of each track is recorded in sync block units as shown in FIG. Each sync block is composed of 750 bits, and every 25th bit of the sync block is a bit inserted as a result of 24/25 modulation and is ignored when decoding. Therefore, only 720 bits are to be decoded.

The sync block consists of two bytes of SYNC signal, one byte of ID0 / ID1 / IDP signal, and 85 bytes of data. SYNC has a specific pattern that distinguishes it from other data. ID0 and ID1 are identification data for identification of a sync block, and IDP is parity data for parity check of ID0 and ID1.

Figure 2 is a block diagram showing a simplified configuration of an embodiment of the analysis device according to the present invention. The apparatus shown in FIG. 2 includes a capture unit 20, an interface unit 30, an analyzer 40, and a graphic processor 50. The apparatus shown in FIG. 2 records predetermined data on a tape through the DVC system to be measured, and reproduces the data again through the DVC system. Then, the reproduced data is compared with the original data to analyze the waveform, error rate, jitter, and the like. The analyzed result is displayed through a monitor (not shown).

The capture unit 20 determines an operation to be performed according to the mode setting signal provided from the analyzer 40, and captures the reproduced data through the DVC system 10 to be analyzed or analyzes the captured data. 40).

The interface unit 30 performs an interface between the capture unit 20 and the analyzer 40.

The analyzer 40 compares original data and captured data according to a program loaded therein, and performs waveform analysis, error rate analysis, jitter analysis, and the like.

The graphic processor 50 inputs analysis data generated as a result of the analysis of the analyzer 40 to generate an image signal displayed to the user.

3 is a block diagram showing a detailed configuration of the capture unit shown in FIG. The apparatus shown in FIG. 3 includes a serial-to-parallel converter 200, a memory 202, an address generator 204, a reference signal detector 206, selectors 208.210, and buffers 212, 214.

The output of the serial-to-parallel converter 200 is provided as an input of the first buffer 212, and the output of the first buffer 212 is provided as an input of the memory. The output of the memory 200 is provided as an input of the second buffer 214 and the output of the second buffer 214 is provided to the bus 60.

The operation of the first buffer 212 and the second buffer 214 is controlled by the mode setting signal provided from the measurement unit 40 as described later.

The first selector 208 selects the reset signal generated based on the reference signal provided by the DVC system to be measured or the reset signal provided from the measurement unit 40 as described later. ) As a reset signal.

The second selector 210 selects the reproduced clock signal provided from the DVC system to be measured or the clock signal provided from the analyzer 40 as described later, and provides the selected clock signal as the clock input of the address generator 204. .

The selection operation of the first selector 208 and the second selector 210 is controlled by the mode setting signal provided from the measurement unit 40 as described later.

The address generator 204 starts an address generation operation in synchronization with the reset signal, and the address is synchronized with the clock input.

The read / write operation of the memory 202 is determined by the mode setting signal provided from the analyzer 40 as described later.

The serial-to-parallel converter 200 inputs data reproduced by the DVC system to be measured in the form of a serial bit stream and converts the data reproduced into parallel data having a predetermined length, for example, 8 bits.

The reference signal detector 206 detects a reference signal generated at a predetermined time interval, for example, a frame synchronization signal. The reference signal detector 206 generates a reset signal when a frame sync signal is detected.

The capture unit 20 captures the playback data provided from the DVC system 10, which is an analysis target in the capture mode, and provides the captured data to the analysis unit 40 in the upload mode.

The capture unit 20 operates in the capture mode or the upload mode according to the mode set signal provided from the analyzer 40. The mode set signal is a binary signal, for example, a capture mode when high, and an upload mode when low.

First, the operation in capture mode is explained. If the mode setting signal provided from the analyzer 40 is set to the high state, the capture mode is set. In the capture mode, the first buffer 212 is activated, the second buffer 214 is deactivated, and data output from the serial-to-parallel converter 200 is provided to the memory 202. On the other hand, the first selector 208 selects the reset signal provided from the reference signal detector 206, and the second selector 210 selects the reproduction clock. In addition, the memory 202 is set to the write mode.

The memory 202 stores the parallel data provided by the serial-to-parallel converter 200 at a position designated by an address signal applied thereto. At this time, the address signal and the operation of the serial-to-parallel converter 200 are synchronized. That is, the period in which the serial-to-parallel converter 200 performs the serial-to-parallel conversion and the period in which the address generator 204 generates the address signal are synchronized.

Next, the operation in the upload mode will be described. When the mode setting signal provided from the analyzer 40 is set to the low state, the upload mode is set. In the upload mode, the first buffer 212 is deactivated, the second buffer 214 is activated, and data output from the memory 202 is displayed on the bus 60. The first selector 208 and the second selector 210 select the reset signal and the clock signal provided from the analyzer 40. In addition, the memory 202 is set to the read mode.

The address generator 204 generates and provides an address signal to the memory 202 according to a predetermined pattern sequentially defined in response to the reset signal applied thereto.

The memory 202 reads the data of the position designated by the address signal applied thereto and provides it to the bus.

4 is a block diagram showing a detailed configuration of the analysis unit shown in FIG. The apparatus shown in FIG. 4 includes a buffer 400, a microprocessor 402, a write data memory 404, a ROM 406, a RAM 408, a key input 410, and a mouse 412.

The buffer 400 receives and stores captured data provided from the capture unit 20 through the interface unit 30 in sync block units.

The write data memory 404 stores original data. The write data memory 404 may be embodied as a RAM, a hard disk, a floppy disk, or the like.

ROM 406 stores programs for waveform analysis, random error rate analysis, burst error rate analysis, jitter analysis, and the like.

The microprocessor 402 is controlled by a program stored in the ROM 406 to compare the original data stored in the write data memory 404 with the sync block stored in the buffer 400. The compared result is stored in the RAM 408. The analysis data stored in the RAM 408 is provided to the graphic processor 50 and displayed to the user.

The key input unit 410 and the mouse 412 input a mode setting command, parameter designation data, etc. provided from the user.

FIG. 5 is a block diagram illustrating a detailed configuration of the buffer shown in FIG. 4. The apparatus shown in FIG. 5 includes a shift register 500, a sink detector 502, derandomizers 504, 506, and 508, an ID parity checker 510, and an endgate 512.

The shift register 500 sequentially shifts and stores data provided from the capture unit 20. The sync detector 502 checks whether the first two bytes of the data stored in the shift register 500 are the sync signal. The derandomizers 504, 506, and 508 extract and derandomize the third to fifth bytes of data stored in the shift register 500. In general, all data of the DVC is randomized except for the sync signal in units of bytes. Here, randomization means randomizing in order to avoid data having a direct current component.

The ID parity checker 510 checks the ID0, ID1, and IDP provided by the de-randomizers 504, 506, and 508 to determine whether the correct ID is detected.

Correct detection of sync data and ID data by the sync detector 502 and the ID parity checker 510 means that one sync block is input to the shift register 500. This state is detected by the AND gate 512.

When the AND gate 512 confirms that one sink block is stored in the shift register 500, the microprocessor 402 reads data stored in the shift register 500 through derandomize 504-508. This is compared with the original data stored in the write data memory 404 and the result is stored in the RAM 416.

6 is a flowchart showing the operation of the apparatus shown in FIG. 4. 6 includes an initialization process s60, an analysis process s70, and an expression process s80.

The initialization process (s60) includes a file initialization process (s600) for opening a file to use the original data recorded, a display initialization process (s602) for drawing a sketch for display on the screen, and a detailed sketch for the display on the screen. A scope initialization process (s604), a trace initialization process (s606) for initializing a position value displayed on a screen, and a cursor initialization process (s608) for selecting a cursor are provided.

The analysis process s70 may include a sample mode set process s700 for switching the interface unit 30 to a capture mode, a mode set process s702 for switching the interface unit 30 to a capture mode, and initialization of a bit error calculation value. Bit error initialization process (s704), clock providing process for providing the clock to the interface unit 30 (s706), input process for reading data from the interface unit 30 by one byte (s708), parallel data serial data Parallel-sequence conversion process (s710) for converting the data into a serial data storage process (s712) for discarding the 25th bit and storing the data so far, sync signal detection process (s714) for detecting a sync signal, and sync interval checking process (s716). ), An ID extraction process (s718), a data read process of reading original data corresponding to the sink block ID (s720), and a process of calculating an error by comparing the original data with the reproduced data (s722). do.

In the sample mode set process s700 and the mode set process s702, the analyzer 40 provides the capture unit 20 with a high level mode setting signal through the interface unit 30. Accordingly, in the capture unit 20, the first buffer 212 is activated, and the second buffer 214 is deactivated. On the other hand, the first selector 208 selects the reset signal provided from the reference signal detector 206, and the second selector 210 selects the reproduction clock. In addition, the memory 202 is set to the write mode.

In the input process s708, the analyzer 40 provides the capture unit 20 with a low level mode selection signal through the interface unit 30. Accordingly, in the capture unit 20, the first buffer 212 is deactivated, and the second buffer 214 is activated. Meanwhile, the first selector 208 selects a reset signal provided from the analyzer 40, and the second selector 210 selects a clock provided from the analyzer 40. In addition, the memory 202 is set to the read mode.

In the sync signal detection process s714, the analyzer 40 checks whether the correct sync is detected through the sync detector 502 in the buffer 400.

In the ID extraction process s718, the analyzer 40 checks whether the correct ID is detected through the ID parity checker 510 and the end gate 512 in the buffer 400.

In the data read process s720, the analyzer 40 reads data stored in the shift register 500 in units of bytes through the derandomizers 504 to 508 in the buffer 400.

The display process (s80) is a servo jitter display process (s800) for displaying the position of the reference signal, which is measured servo-related information, and the start position value of the data stream, and the bit error rate per run length (rum length), which is the measured equalizer-related information. An equalizer display process of displaying a value (s802), a sink block display process of displaying a bit error rate value for each measured sync block position (s804), a bit error display process of displaying a measured total error rate variation value (s806), A key check process s808 for checking a user's key input to check a performance mode, and a mouse test process s810 for determining a trace position for display by checking a user's mouse input.

The operation of the apparatus shown in FIG. 4 will be described in detail with reference to the flowchart shown in FIG. 6. When the program starts, the capture unit 20 first checks whether a reference signal is generated. If no problem, capture mode is executed. Upload captured data at the end of capture mode. Find the sink at the same time you upload. If sink data is found, ID0, ID1, and IDP are immediately found, and their reliability is comprehensively evaluated, and if there is reliability, the sync block data of the recording data corresponding to the reproduced data is read out from the stored disk and compared. During this process, the display is processed in units of sync blocks, and the bit error rate is calculated and then displayed. During execution, the required parameters can be changed and the display mode can be switched according to the user's keystrokes and mouse operation. These processes are repeated sequentially.

7 shows an example of a screen displayed through a monitor. The screen illustrated in FIG. 7 includes a main display area 90, a trace display area 100, a trace positioning area 110, and an error display area 120.

The trace position display area 100 displays the position of the data currently being analyzed as a point relative to the original data. The position currently being analyzed may be designated through the trace position display designation region 110.

The trace positioning region 110 is divided into a data delay region 110a, a sync block delay region 110b, and a track selection region 110c.

Each area 110a, 110b, 110c has an area for displaying icons and positions for up / down adjustment.

The error display area 120 includes a servo jitter display area 120a, an equalizer display area 120b, a sync block error display area 120c, and a bit error display area 120d.

The apparatus shown in FIG. 2 may be implemented via a computer. The interface unit 30 may be implemented as an I / O input / output unit on a computer. The analyzer 40 may be implemented by a RAM, a ROM, a microprocessor, or the like, and the graphic processor 50 may be implemented by a graphics card.

In addition, although the apparatus shown in FIG. 2 is configured to compare in units of sync blocks, it may be implemented in units of frames. This problem is related to the capacity of the buffer 400 of the capture unit 20 and the analyzer 40.

As described above, the DVC analysis apparatus according to the present invention may trigger and display specific data contained in a bit stream, and may extract only necessary data by applying a specific bit stream format.

The extracted data can be compared with the original data to check the error on a bit-by-bit basis to calculate random and burst error rates, and to separate the errors by type. This can be seen.

In addition, by analyzing the position of the error and the absolute position can also know the characteristics of the servo system indirectly. Therefore, this apparatus has the flexibility applicable to all parts including the recording / reproducing section.

Claims (11)

An apparatus for recording predetermined data through a DVC system to be analyzed and comparing the data reproduced from the system with the original data. A capture unit for capturing or transmitting data reproduced from the DVC system; An analysis unit for comparing and analyzing the reproduced data transmitted through the capture unit and the original data; And And a graphic processor configured to display a result analyzed by the analyzer. The method of claim 1, wherein the capture unit A memory for recording reproduced data provided from the DVC system or reading recorded data in response to a mode setting signal provided from the analyzer; A first buffer controlled by the mode setting signal and intermittently providing the reproduced data to the memory; A second buffer controlled by the mode setting signal and intermittently providing the reproduced data from the memory to the analyzer; A first selector for selecting a reset signal generated based on a reference signal provided from the DVC system or a reset signal provided from the measurement unit and providing the reset signal as a reset signal of an address generator; A second selector for selecting a reproduction clock signal provided from the DVC system or a clock signal provided from the analyzer and providing the selected clock signal as a clock input of the address generator; And an address generator for generating an address signal provided to the memory in synchronization with a reset signal provided by the first selector and a clock signal provided by the second selector. The method of claim 2, wherein the capture unit And a serial-to-parallel converter for converting the serial bit stream provided from the DVC system into parallel data having a predetermined length and providing the same to the memory. The method of claim 2, wherein the capture unit And a reference signal detector for generating a reset signal provided to the first selector in response to a reference signal provided from the DVC system. The method of claim 1, wherein the analysis unit A buffer for inputting and storing captured data provided from the capture unit 20 in sync block units; A recording data memory for storing original data recorded through the DVC system; A storage device for storing a program for waveform analysis, random error rate analysis, burst error rate analysis, jitter analysis, etc. for the sync blocks stored in the buffer; A microprocessor controlled by the analysis program stored in the storage means to compare the original data stored in the recording data memory with the sink block stored in the buffer; RAM which stores the result compared by the microprocessor and provides it to the graphics processor; And And a key input unit for inputting a mode setting command, parameter designation data, etc. provided from a user. The apparatus of claim 5, wherein the storage device is a ROM. 7. The apparatus of claim 6, wherein the ROM stores a program for waveform analysis, random error rate analysis, burst error rate analysis, jitter analysis, and the like. The method of claim 5, wherein the analysis unit And a mouse for inputting a mode setting command, parameter designation data, and the like provided from a user. The method of claim 5, wherein the buffer A shift register configured to sequentially shift and store data provided from the capture unit; A sync detector for checking whether a first two bytes of the data stored in the shift register are a sync signal; An ID parity checker that checks whether the correct ID is detected by checking ID0, ID1, and IDP, which are the third to fifth bytes from the data stored in the shift register; And And an AND gate for checking whether the sink data and the ID data are correctly detected by referring to the test result of the sink detector and the ID parity checker. The method of claim 9, wherein the buffer is And a derandomizer which derandomizes the data stored in the shift register (500) in units of bytes to provide the ID parity checker or the microprocessor. The method of claim 1, wherein the analysis unit A buffer for inputting and storing captured data provided from the capture unit 20 in sync block units; A recording data memory for storing original data recorded through the DVC system; A storage device for storing a program for waveform analysis, random error rate analysis, burst error rate analysis, jitter analysis, etc. for the sync blocks stored in the buffer; A computer controlled by an analysis program stored in the storage means for comparing original data stored in the record data memory with a sink block stored in the buffer; RAM which stores the result compared by the microprocessor and provides it to the graphics processor; And And a key input unit for inputting a mode setting command, parameter designation data, etc. provided from a user.

Images