JPH04156612A - Multiplier - Google Patents

Abstract

PURPOSE:To reduce an input offset voltage by forming first to eighth differential pairs by means of the eight pairs of transistors having different W/L ratios and setting the W/L ratios of the respective transistors to be a specified value. CONSTITUTION:The first to eighth differential pairs are formed by the eight pairs of TrM1-M8 having the different W/L ratios (the ratio between a gate width and a gate length). A first input voltage is inputted to the first to fourth differential pairs M1-M4 in such a way that the phases of the first and the second differential pairs M1 and M2 and those of the third and the fourth differential pairs M3 and M4 become opposite. A second input voltage is inputted to the fifth to eighth differential pairs M5-M8 in order to make the phases to be same. One output of the fifth and the sixth differential pairs M5 and M6 is set to be the current source of the second differential pair M2 and the other output to be the current source of the fourth differential pair M4. One output of the seventh and the eighth differential pairs M7 and M8 is set to be the current source of the first differential pair and the other output to be the current source of the third differential pair M3. The input offset voltage is reduced by setting the W/L ratios of respective Tr to be the specified value.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to multipliers, and more particularly to multipliers formed on MO8 integrated circuits.

[Conventional technology]

Conventionally, multipliers formed on MO3 integrated circuits include a multiplier called a Gilbert cell in which differential pairs are stacked vertically, and a fault Gilbert cell in which differential pairs are stacked horizontally. ing.

[Problem to be solved by the invention]

The above-mentioned conventional multiplier has a configuration in which normal differential pairs are stacked vertically or horizontally, so when formed on an MO8 integrated circuit, the disadvantage is that the input offset of the differential pair becomes large. There is.

[Means to solve the problem]

The multiplier of the present invention has a source connected in common, a gate connected in correspondence with the first and second input terminals inputting the first input voltage, and a drain connected in correspondence with the first and second load resistors, respectively. first and second differential pairs that are connected to each other and have different ratios of gate width and gate length to form a first differential pair.
transistors, whose sources are commonly connected, whose gates are connected correspondingly to the first and second input terminals, and whose drains are connected correspondingly to the first and second load resistors, and a gate width and a gate length. A third and a fourth transistor forming a second differential pair having different ratios from each other have their sources connected in common, their gates connected to the second and first input terminals in correspondence with each other, and their drains connected to the second and first input terminals, respectively. fifth and sixth transistors which are connected correspondingly to the first and second load resistors and have different ratios of gate width and gate length and form a third differential pair; are connected to the second and first input terminals, respectively, and the drains are connected to the first and second load resistors, respectively, and the gate width and gate length ratios are different from each other, and a fourth difference is formed. Seventh and eighth transistors forming a dynamic pair, their sources commonly connected to the first current source circuit, and their gates respectively connected correspondingly to third and fourth input terminals into which the second input voltage is input. and the drain is connected to the third drain. the source of the fourth transistor and the seventh transistor. Ninth and tenth transistors are connected to the source of the eighth transistor in a corresponding manner and have mutually different ratios of gate width and gate length to form a fifth differential pair, and the source is connected to the second current source circuit. common connection to
The gates are connected to the third and fourth input terminals, respectively, and the drains are connected to the third and fourth input terminals, respectively. the source of the fourth transistor and the seventh transistor. Eleventh and twelfth transistors are connected correspondingly to the source of the eighth transistor and have mutually different ratios of gate width and gate length to form a sixth differential pair, and the source is connected to a third current source. common connection to the circuit,
The gates are connected to the third and fourth input terminals, respectively, and the drains are connected to the first and second input terminals, respectively. the source of the second transistor and the fifth. Thirteenth and fourteenth transistors are connected to the source of the sixth transistor in a corresponding manner and have mutually different ratios of gate width and gate length to form a seventh differential pair, and the source is connected to the fourth current source circuit. , gates are connected to correspond to the third and fourth input terminals, and drains are connected to the sources of the first and second transistors and the sources of the seventh and eighth transistors, respectively. The present invention is characterized in that it has fifteenth and sixteenth transistors that are connected to each other and have different ratios of gate width and gate length to form an eighth differential pair.

Also, the ratio of the gate width to gate length of the first and second transistors, the ratio of the gate width to gate length of the third and fourth transistors, and the gate width of the fifth and sixth transistors. and the gate length, and the ratio of the gate width and gate length of the seventh and eighth transistors are equal to each other, and the ratio of the gate width and gate length of the ninth and tenth transistors is equal to each other. , the ratio of the ratio of the gate width to the gate length of the 11th and 12th transistors, the ratio of the ratio of the gate width to the gate length of the 13th and 14th transistors, and the gate width of the 15th and 16th transistors. and the gate length are configured so that the ratios of the gate length and the gate length are equal to each other.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In this embodiment, first and second input terminals T, , T2 whose sources are commonly connected and whose gates are input to the first input voltage vl
first and second load resistors R1 and R2, respectively, have drains connected correspondingly to first and second load resistors R1 and R2, and have different ratios of gate width and gate length to form a first differential pair. The sources of the second transistors Ml and M2 are connected in common, the gates are connected to the first and second input terminals Tl and T2, respectively, and the drains are connected to the first and second load resistors R1 and R2, respectively. Third and fourth transistors M3 and M4, which are connected together and have different gate width and gate length ratios and form a second differential pair, have their sources commonly connected and have their gates connected to the second and first inputs. Terminal T2. A fifth resistor having a drain connected to the first and second load resistors R1 and R2 in a corresponding manner and having a gate width and a gate length different from each other and forming a third differential pair.
and a sixth transistor M5. M6, the source is commonly connected, the gate is connected correspondingly to the second and first input terminal T2゜T1, and the drain is connected correspondingly to the first and second load resistor R1, R2, respectively, and the gate width is and the gate length of the seventh and eighth transistors M7 . M8, the first to fourth current sources 1 to 4, and the third and fourth current sources whose sources are commonly connected to the first current source 1 and whose gates input the second input voltage v2.
input terminal T3. Connect the drains of T4 and T4 in correspondence with each other. Fourth transistor M3. Source of M4 and 7th. Eighth transistor M7. Ninth and tenth transistors M9.M8, which are respectively connected to the source of M8 and have mutually different ratios of gate width and gate length, form a fifth differential pair. MlO and the sources are commonly connected to the second current source 2, and the gates are connected to the third and fourth input terminals T3. T,
and the drains are connected correspondingly to the third. Fourth transistor M3. Source of M4 and 7th. Eighth transistor M7. Eleventh and twelfth transistors Mll and M12 are respectively connected to the source of M8 and have mutually different ratios of gate width and gate length and form a sixth differential pair.
, the sources are commonly connected to the third current source T3, and the gates are connected to the third and fourth input terminals T3. Tl are connected correspondingly to the drains of the first . second transistor Ml,
Source of M2 and 5th. Sixth transistor M5. M6
13th and 14th transistors M13°Ml4 are connected correspondingly to the sources of the transistors and have mutually different ratios of gate width and gate length to form a seventh differential pair, and the sources are connected to the fourth current source 4 are commonly connected to the third and fourth input terminals T3. T4 and the drains are connected correspondingly to the first. The second transistor Ml, the source of M2 and the seventh and eighth transistors M7. 5. 15th and 16th transistors M1 are connected to the source of M8 in a corresponding manner and have mutually different ratios of gate width and gate length, forming an eighth differential pair; Ml 6 and the first and second
The ratio of the gate width to gate length ratio of the transistors M1 and M2, the third and fourth transistors M3. The ratio of the gate width to gate length ratio of the fifth and sixth transistors M5. M6's gate width to gate length ratio, and the seventh and eighth transistors M7. The gate width and gate length ratios of M8 are equal to each other, and the ninth and tenth transistors M9. Ratio of gate width to gate length of MIO, 11th and 12th transistor Ml 1. Ml
2, the ratio of the gate width to the gate length, the 13th and the 1st
4 transistor M13. The ratio of the gate width to gate length of M14, and the 15th and 16th transistor M
15 and M160, the gate width and gate length ratios are equal to each other.

Next, the operation and effects of this embodiment will be explained.

First, if we set the gate width ratios W/L of transistors Ml to M16 as hW, /L, ~W r s / L 16, then (W2/L2)/(Wl/L, ) = (W, / L,)
/, (W3/Lri=...=(W,/Ls)/(w,/
Lt) = > t ... (1) (W+./L,
. )/(W9/L,)=(W11/L+2)/(Wll
/Lll)=...:(W+6/L16)/(W15
/L12)=k r> 1 (2).

Further, assuming that the mobility of the transistor is μn and the gate oxide film thickness is C6, the drain current Id1~Id16 of each transistor M1 to M16 is Id! "αt(V-, +Vf)2
......(5) 1, +z= +α+(V, -z
V-)2 ・-・16)Id3=+α+(V
,,3 V-)2--(7)■,4=αl(
V,,4-Vt)2 ・・・・・・(8
)I4g”k+αl(V,,5-V,)2-・
...-(9)x, 6=a1cv,, a-v,)"
・----・QQLy=α1(V-, T
V-)2 ”・-Ql)Ias=to+αl
cV, 5a-Vt) 2-・-・-QZ Engineering 4. =α2(V
yo,,-v,)2...0ΦIa
+o=2α2 (V −, 1o −V −) 2...
・・・・αΦId++=2ff2(Vg, ++ v
J2・−・・(1511a+2=”2(Vgs+2vt
)2...-asIa+3=α2(V, s+s vt
)" ...-...-a?)Ia+4=2
αz (Vista Vt)”・-”Q8I
a+5=kzαz(v,,+s−v,)2 ・−
...-09Ia+s=(rz(Vista Vt)
2--QO. However, Vt is the pinch-off voltage of the transistor.

Here, Ias+Ia+o=L+++Ia+2=Iau+L+4
=I, us+I, us=I. ...
...Ql)V2"Vga@VgalO=Vt+l
+-■,,12=Vgs13 Vgs14=V'gs
15 Vista ・・・・・・@Also, 21, □=L L = (Le+Ln) (L+o+I+z)= (I
au+Ia+a) (Ltt+L+s)=I a
+ + I a @ where I, +L=2I. ...
...Since Gυ, from equation (c), I, = I. +■v2 1. =I. It can be expressed as -L+.

Similarly, L+= (Ia++Idx) (L2+L4)Le
+Ia++=L+x+Id+s=L・
...@I dlo+ I, ++z= I a1
4+ I a+e= I z...
... can be expressed as (to). Here, L l=L s −L + .

L +=L + + -1i 12 I=+ +L2=L:++La=I+...
...(5) I a5+ I -6= I a7+ I
as= I 2 ...@I, 12=2I. ...It's a rocky shore.

Here, transistor M9. A differential pair consisting of MIO and a transistor Ml 1. The differential pair consisting of transistors Ml 2 constitutes a first differential amplifier whose output current is Ill I2, respectively, and the transistors Ml 3. Differential pair consisting of M14 and transistor M15. The differential pair consisting of Ml 6 constitutes a second differential amplifier with output currents II and I2, respectively.

I21= (Ls+Idy) (Ias+Ia
s).

Here I3-I. = I +++ I 21 then...
...017).

If set here, it becomes...G9...(4I). Here, f(x) v'west - 1...39 g (x) = v'seal -X...
...(A [exist] h(x) = f(x) - g(x)
Let's say ・・・・・・H and expand it into a series: ・・・・・・0Q Here, f (0)= g (0)= 1,
, ', h (0) = O...St) Therefore, h
(x) = a x + -x 2+... ・
...In other words, if you display up to the quadratic terms of ■ and □...Q.

+ Substituting the formula 38, 09... (support) The second term and below, and ■1'≠0 and ignoring the term Vl'', I3 I4≠-・Eng7,・Iv□
・・・・・・6■I.

That's what I find.

Here, Ivl corresponds to the output current (transfer curve) of the differential amplifier with respect to the input voltage ■1, and ■ and □ represent the output current (transfer curve) of the differential amplifier with respect to the input voltage v2.

The output current (transfer curve) of a differential amplifier can be regarded as a straight line if the input voltage is small.

Therefore, it can be seen that Equation 69 functions as a multiplier in a range where the input voltages V t and V 2 are small. In particular, from equation (b), it is expected that the range in which multiplier characteristics with good linearity can be obtained for input voltage vI is narrower than for input voltage v2.

Regarding Iv+JIV2, for example, if we look at IV2 of the CIQ formula, it represents the difference in drain current of the MO3 differential pair. -For a differential pair with equal W/L, it can be found by setting 2=1 in equation (to).

The 6Q type represents a case where two equal differential pairs are connected in parallel, and the current value is doubled.

Now, if we think about k2, equation (c), c! Since Equation 6'r) and Equation 3 represent deviations in characteristics due to deviations in the W/L ratio of transistor pairs in each differential pair, they can be considered as offset currents generated in the output.

Figure 2 shows the characteristic diagrams of the 1ri7) formula and the cis formula.

As can be seen from FIG. 2, the slope of the curve is large around k 2 = 1, and the slope of the curve decreases as k 2 increases.

In other words, when the value of k2 is increased, the characteristics of the paired transistors in the differential pair deteriorate, and furthermore, the deviation from the design value of the W/L ratio (R2) of the transistors forming the differential pair is due to the difference between the two pairs of differential amplifiers. It can be seen that in the case of this circuit, there is almost no effect on the offset current on the output side.

The offset current at this time is I, 1V2=o.

This sum is expressed as the sum of I dt l V2 = O, but this sum also becomes almost small and can be ignored by increasing 2 for the deviation of the W/L ratio (R2) of the transistor from the design value. . Therefore, this circuit has the effect of reducing offset.

The above also applies to each of the two differential pair groups consisting of transistors M1 to M4, transistors M5 to M8, and transistors M13 to M16. Therefore, this embodiment is a circuit with reduced offset.

The results of a simulation performed on Equation 69 are shown in FIGS. 3 and 4.

〔Effect of the invention〕

As explained above, the present invention forms first to eighth differential pairs using eight pairs of transistors having different W/L ratios, and
~The fourth differential pair has the first input voltage connected to the first input voltage. a second differential pair and a third differential pair; The input voltages are inputted to the fourth differential pair so that they are in an opposite phase relationship with each other, the second input voltages are inputted to the fifth to eighth differential pairs so that they are in phase with each other, and 5. One output of the sixth differential pair is used as a current source for the second differential pair, the other output is used as a current source for the fourth differential pair, and the seventh. One output of the eighth differential pair is configured as a current source for the first differential pair, and the other output is configured as a current source for the third differential pair, and the W/L ratio of each transistor is set to a predetermined value. By doing so, there is an effect that the input offset voltage can be reduced.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIGS. 3 and 4 are characteristic diagrams of a predetermined current for explaining the operation of the embodiment shown in FIG. 1. FIGS. be. ■1~Step 4...Current source, M1~M16...
...Transistor, R1, R2...Load resistance. Agent Patent Attorney Susumu Uchihara CQX=320λ (13-14) fil-ta 2.5 Fig. 4

Claims (1)

[Claims] 1. The sources are commonly connected, the gates are connected correspondingly to the first and second input terminals into which the first input voltage is input, and the drains are connected to the first and second load resistors, respectively. first and second transistors that are connected in a corresponding manner and have different ratios of gate width and gate length forming a first differential pair; their sources are commonly connected and their gates are connected to the first and second input terminals; third and fourth resistors whose drains are connected correspondingly to the first and second load resistors and whose gate width and gate length ratios are different from each other and form a second differential pair; transistors, whose sources are commonly connected, whose gates are connected correspondingly to the second and first input terminals, and whose drains are connected correspondingly to the first and second load resistors, respectively, and a gate width and a gate length. The ratio is different from each other and the third
A fifth and a sixth transistor forming a differential pair have their sources connected in common, their gates connected to the second and first input terminals, respectively, and their drains connected to the first and second input terminals, respectively.
seventh and eighth transistors that are connected in correspondence with the load resistance of the transistors and have different ratios of gate width and gate length to form a fourth differential pair, and their sources are commonly connected to the first current source circuit. and its gates are connected to third and fourth input terminals into which the second input voltage is input, respectively, and its drains are connected to the sources of the third and fourth transistors and the sources of the seventh and eighth transistors. Ninth and tenth transistors are connected correspondingly and have different ratios of gate width and gate length to form a fifth differential pair, and the sources are commonly connected to the second current source circuit, and the gates are connected in common. The drains are connected to the third and fourth input terminals in correspondence with the sources of the third and fourth transistors and the seventh and eighth transistors, respectively.
Eleventh and twelfth transistors which are respectively connected to the sources of the transistors and have mutually different ratios of gate width and gate length forming a sixth differential pair, and whose sources are common to the third current source circuit. the gates are connected to the third and fourth input terminals, respectively, and the drains are connected to the sources of the first and second transistors and the fifth and sixth input terminals.
13th and 14th transistors which are respectively connected to the sources of the transistors and have mutually different ratios of gate width and gate length forming a seventh differential pair, and whose sources are common to the fourth current source circuit. the gates are connected to the third and fourth input terminals respectively, and the drains are connected to the sources of the first and second transistors and the seventh and eighth input terminals.
A multiplier comprising fifteenth and sixteenth transistors which are respectively connected to the sources of the transistors and have different gate width to gate length ratios and form an eighth differential pair. 2. The ratio of the gate width to gate length of the first and second transistors, the ratio of the gate width to gate length of the third and fourth transistors, and the gate width of the fifth and sixth transistors. and the gate length, and the ratio of the gate width and gate length of the seventh and eighth transistors are equal to each other, and the ratio of the gate width and gate length of the ninth and tenth transistors is equal to each other. , the ratio of the gate width to gate length of the eleventh and twelfth transistors, the ratio of the gate width to gate length of the thirteenth and fourteenth transistors, and the first
2. The multiplier according to claim 1, wherein the ratio of gate width to gate length of the fifth and sixteenth transistors is equal to each other.