JPH04156005A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To output a desired pulse signal only by setting values equivalent to arbitrary pulse width and a frequency by providing a flip-flop which obtains a prescribed pulse signal set by the output of a first comparison means and reset by the output of a second comparison means, and feeds back it to a selection means. CONSTITUTION:The first comparison means 5 which compares the output of a first counter means 4 with data stored and held in a first storage holding means 3, and the second comparison means 8 which compares the output of a second counter means 7 with data stored and held in a second storage holding means 6 are provided. The flip-flop 9 set by the output of the first comparison means 5 and reset by that of the second comparison means 8 is provided, and the prescribed pulse signal can be obtained from the flip-flop 9, and also, it is fed back to the selection means 2. thereby, it is possible to obtain the desired pulse signal only by setting a pulse signal with arbitrary pulse width and arbitrary frequency on the storage holding means in a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides an on/off (ON) switch using an electronic switch.
Regarding the digital signal processing circuit when performing FF) control,
In particular, the present invention relates to a digital signal processing circuit that can arbitrarily set the on-time and off-time of a pulse signal.

[Background Art] Conventionally, as a method for generating pulse signals in a digital signal processing circuit, a pattern of changes in the pulse signal is written in advance on a memory in a control circuit, and this is written in advance by the output of a counter counted by a reference clock. The device is configured to read out a pattern specified by a predetermined address and generate the pulse by outputting the data.

L Problems to be Solved by the Invention] However, in the conventional pulse signal generation method,
In order to generate a pulse signal with an arbitrary pulse width and an arbitrary frequency, there is a drawback that all the data in the memory must be rewritten in advance.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and is a digital signal processing method that can output a desired pulse signal by simply setting values corresponding to an arbitrary pulse width and an arbitrary frequency. The purpose is to provide a circuit.

[Means for Solving the Problems] The present invention provides a reference clock generation section that generates a reference clock, a monostable mode, an astable mode, or a pulse width modulation mode that can be switched by a selection command from an output control section, and a trigger mode. a selection means that generates an output signal in response to a signal; a first counting means that is activated by the output of the selection means and starts counting in response to the reference clock; and a memory holding data arbitrarily set in advance by the output control section. a first memory holding means for comparing the output of the first counting means with the data stored in the first memory holding means; a second memory holding means for arbitrarily setting and storing data different from the stored data by the output control unit; and a second memory holding means that is activated by the output of the first comparing means and starts counting according to the reference clock. a second counting means for comparing the output of the second counting means with the data stored in the second memory holding means;
and a flip-flop that is set by the output of the first comparison means and reset by the output of the second comparison means, and a predetermined pulse signal is obtained from the flip-flop and fed back to the selection means. It is composed of

Further, the present invention includes a reference clock generation section that generates a reference clock, a selection command of monostable, astable, or pulse width modulation from an output control section, and an output signal that is controlled by a trigger signal. a first counting means that is activated by the output of the selecting means and starts counting according to the reference clock; and a first memory that stores and holds data arbitrarily set in advance by the output control section. a holding means; a first comparing means for comparing the output of the first counting means with the data held in the first memory holding means; and the data held in the first memory holding means. a second memory holding means for arbitrarily setting and storing different data in advance by the output control section; and a second counting means that is activated by the output of the first comparing means and starts counting by the reference clock. and a second comparing means that compares the output of the second counting means with the data stored and held in the second memory holding means, and a second comparing means that performs setting based on the output of the first comparing means, and a flip-flop which is reset by the output of the second comparison means to obtain a predetermined pulse signal and fed back to the selection means; By arbitrarily changing the set data value, a pulse signal of an arbitrary frequency and pulse width can be output.

[Embodiment] Next, an embodiment of the digital signal processing circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a digital signal processing circuit according to the present invention, and FIG. 2 shows a pulse signal p and data 1 set in the D-register 3 and D-register 6 in FIG. FIG. 3 is a diagram showing a state in which the pulse signal obtained in FIG. 2 is continuously output.

In FIGS. 1 to 3, the reference clock generator 1 is
It generates a reference clock for controlling the timing of the digital signal processing circuit according to this embodiment. The output of this reference clock generator 1 is output to the counter 4.
and 7. In addition, the selector 2 is configured to be monostable by a command from the output control unit 10.
It has a configuration that can be selected by selecting a multivibrator circuit, an astable multivibrator circuit, or a pulse width modulation circuit. When the selector 2 is triggered by the trigger signal t output from the output control section 10, the output of the selector 2 is input to the counter 4. Further, the output control section 10 includes:
The selection control of the aforementioned circuit of the selector 2 and the setting of the pulse width are performed by an external operation means (not shown), and the output pulse signal p
The OFF time of the low level data 1 shown in FIG. 2 is set and outputted to the D-register 3 as a memory holding means for storage.

The output of this D-register 3 is output to a comparator 5 as comparison means. In this embodiment, the D-register 3 is composed of a multi-bit circuit.

The counter 4 counts the clocks generated from the reference clock generator 1 (counting means) for the OFF time of the data l set in the D-register 3 and outputs the counted clocks to the comparator 5 . Then, the comparator 5 compares the set value of the D-register 3 and the count value of the counter 4, and when the two values match, the comparator 5 compares the set value of the D-register 3 and the count value of the counter 4,
It is output to F (D-flip-flop) 9. Since the output of the comparator 5 is also output to the D-FF9 at the same time, this output signal S sets the D-FF9. This set signal S causes the data h of the pulse signal p shown in FIG. 2 to rise. Further, in this embodiment, the D-FF 9 is constituted by a 1-bit circuit.

Further, the output control unit 10 sets the ON time of the data h shown in FIG.
- Output to register 6 and store. The output of this D-register 6 is output to a comparator 8 as comparison means. This D-register 6 is composed of a multi-bit circuit.

The counter 7 counts the clocks generated from the reference clock generator 1 for the ON time of the data h set in the D-register 6. Then, the comparator 8 compares the set value of the D-register 6 and the count value of the counter 7, and when the two values match, outputs the result to the D-FF 9. This output signal becomes the reset signal r of the D-FF9. This reset signal r causes data h shown in FIG. 2 to fall. Therefore, D-F F 9 is set by the output signal S of the comparator 5 and reset by the output signal r of the comparator 8, thereby outputting desired data. Further, the output of the pulse signal p of the D-FF 9 is fed back to be input to the selector 2.

Next, the operation of this embodiment having the above configuration will be explained.

(2) First, the operation of a seven-nostable (monostable) multi-pie break circuit will be explained.

The output control unit 10 shown in FIG. 1 sets the OFF time of data 1 in FIG. The selector 2 is selectively controlled to accept only the trigger signal t output from the output control section 10. Further, the counter 4 and the counter 7 are set so that their outputs are in a clear state.

Now, when the trigger signal t is input to the selector 2, the counter 4 starts counting using the clock generated by the reference clock generator 1. Thereafter, when the count value of the counter 4 matches the value set in the D-register 3, the comparator 5 detects the match. Since the comparator 5 outputs the output to the counter 7 and the D-FF 9 at the same time, the D-FF 9 is set at the same time when the counter 7 is triggered and starts counting by the clock generated by the reference clock generator 1. Then, the data h of the pulse signal p shown in FIG. 2 rises.

Thereafter, when the count value of the counter 7 matches the value of data h set in the D-register 6, the comparator 8
detects the match and outputs it to D-FF9. D-FF
9 is reset by the output signal r from the comparator 8, so that the data h shown in FIG. 2 falls.

The on time of the pulse signal at this time is the value preset in the D-register 6 multiplied by the period of the reference clock 1, and the off time of the data 1 is the value set in advance in the D-register 6. The reference clock generator 1 is set to a preset value.
Multiplying the period of the clock generated by the time is the total time.

Through the above operations, a series of pulse signals as shown in FIG. 2 are outputted once, and the operation as a monostable multi-by-break is completed.

(2)0 Next, the operation when performing an astable (unstable) multi-pie break circuit will be explained.

First, the output control section 10 shown in FIG. 1 selects and controls the selector 2 by specifying the astable multivibrator circuit. The output control unit 10 activates the first pulse output in response to the trigger signal t, and causes the selector 2 to output it. The second and subsequent pulse outputs are the pulse signals p fed back at the falling timing of the output p of the D-FF9.
The selection is controlled so that it is activated by.

That is, the pulse signal p shown in FIG. When the D-FF9 falls in response to the reset signal r, the high level data h shown in FIG. 2 is obtained. is triggered again to obtain the pulse signal p shown in FIG. By performing this loop continuously, the output of a pulse signal of an arbitrary frequency and pulse width as shown in Fig. 3 is continuously output from D-F.
It is output as a pulse signal p by F9.

(2) Next, the operation of the pulse width modulation circuit will be explained.

The selector 2 is selectively controlled by the output control section 10 shown in FIG. Then, the first pulse output of the selector 2 is activated by the trigger signal t, and the second and subsequent pulse outputs are selectively controlled at the falling timing of the output p of the D-FF 9. When the pulse signal p is outputted continuously as shown in FIG. 3, the output p of the D-FF 9 is fed back to the selector 2 as described above.

Further, the D-register 3 and the D-register 6 are continuously set to a value that always satisfies the following formula by commanding the output control unit 1o by an external operation means (not shown) every time the pulse width is modulated. You can set it to .

1 +h=constant (1) As a result, the desired pulse signal p, which is pulse width modulated with the same frequency and arbitrary duty ratio, can be continuously obtained from the D-FF 9.

In this embodiment, a 1-bit circuit is used for the D-FF 9, but it goes without saying that a multiple-bit circuit may also be used. As long as the width of h and 1 can be changed and stored, it can be used with appropriate changes within the scope of this embodiment.

[Effects of the Invention] As explained above, according to the present invention, it is possible to obtain the output of a desired pulse signal by simply setting a pulse signal of an arbitrary pulse width and an arbitrary frequency in the memory storage means on the circuit. It has the effect of Therefore, for example, on/off control of a timer and generation of a gate signal for an electronic circuit can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital signal processing circuit according to the present invention, FIG. 2 is a diagram showing the relationship between the pulse signal p and data l and h in FIG. 1, and FIG. , second
FIG. 3 is a diagram showing a state in which the pulse signal obtained in the figure is continuously output. 1... Reference clock generation section, 2... Selector, 3.
6...D-register, 4,7...Counter, 5,8
...Comparator, 9...D-FF, 1o...Output control section. 1o Figure 1

Claims (1)

[Claims] (1) A reference clock generation section that generates a reference clock;
a selection means that is switched by a selection command of monostable, astable, or pulse width modulation from an output control section and generates an output signal in response to a trigger signal; and a selection means that is activated by the output of the selection means and is activated by the reference clock. a first counting means that starts counting; a first memory holding means that stores and holds data arbitrarily set in advance by the output control section; and an output of the first counting means and the first memory holding means. a first comparing means for comparing the data stored and held in the means; and a first comparing means for arbitrarily setting and storing data different from the data stored in the first storage means by the output control section. a second counting means that is activated by the output of the first comparing means and starts counting according to the reference clock; and an output of the second counting means and the second memory holding means. a second comparing means for comparing the data stored and held in the first comparing means;
1. A digital signal processing circuit comprising: a flip-flop which is reset by the output of the comparing means; a predetermined pulse signal is obtained from the flip-flop and fed back to the selecting means. (2) The first comparing means is configured to output at a timing when the output of the first counting means and the value of data set in the first memory holding means coincide. The digital signal processing circuit according to claim (1). (3) The second comparing means is configured to output at a timing when the output of the second counting means and the value of the data set in the second memory holding means coincide. The digital signal processing circuit according to claim (1). (4) The first comparing means opens the gate with a delay corresponding to the data set in the first memory holding means with respect to the trigger signal output from the output control section. The digital signal processing circuit according to claim (1) or claim (2), characterized in that: (5) A reference clock generation section that generates a reference clock, and a selection means that is switched by a selection command of monostable, astable, or pulse width modulation from the output control section and that generates an output signal in response to a trigger signal. , a first counting means that is activated by the output of the selection means and starts counting according to the reference clock; a first storage holding means that stores and holds data arbitrarily set in advance by the output control section; a first comparing means for comparing the output of the first counting means with the data stored and held in the first storage holding means; and outputting the data different from the data stored and held in the first storage holding means. a second memory holding means that stores and stores arbitrary settings in advance by a control unit;
A second counting means is activated by the output of the comparison means and starts counting according to the reference clock, and the output of the second counting means is compared with the data stored and held in the second storage holding means. Setting is performed by the outputs of the second comparing means and the first comparing means, and resetting is performed by the output of the second comparing means, thereby obtaining a predetermined pulse signal and feeding back to the selecting means. A flip-flop is provided, and by arbitrarily changing the data values set in the first and second storage means by the output control section, a pulse signal of an arbitrary frequency and pulse width can be output. A digital signal processing circuit characterized by: (6) The digital signal according to claim (5), wherein the digital signal is configured to repeatedly output a pulse signal of an arbitrary frequency and pulse width by feeding back the output signal of the flip-flop to the selection means. processing circuit. (7) Set the data values set in the first and second storage means by the output control unit so that they are pulse signals of the same frequency and arbitrary duty ratio, and continuously output the pulse signals. The digital signal processing circuit according to claim 5 or 6, characterized in that the digital signal processing circuit is configured to be able to perform the following functions.