GB1184932A - Sequence of Operations Performance Controller - Google Patents
Sequence of Operations Performance ControllerInfo
- Publication number
- GB1184932A GB1184932A GB31089/67A GB3108967A GB1184932A GB 1184932 A GB1184932 A GB 1184932A GB 31089/67 A GB31089/67 A GB 31089/67A GB 3108967 A GB3108967 A GB 3108967A GB 1184932 A GB1184932 A GB 1184932A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bits
- field
- elapsed time
- performance
- s1sr
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4818—Priority circuits therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Exhaust Gas Treatment By Means Of Catalyst (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Time Recorders, Dirve Recorders, Access Control (AREA)
Abstract
1,184,932. Timed control of electric circuits. INTERNATIONAL BUSINESS MACHINES CORP. July 6, 1967 [July 15, 1966], No. 31089/67. Heading G3T. Apparatus for controlling the performance of a series of operations, of, for example, traffic signals, comprises (a) means for measuring elapsed time (b) a recirculatory storage system for storing representations of the nature and specified time duration of each operation, (c) means for selecting and initiating performance of an operation (d) means for comparing the measured elapsed time from the initiation of the performance with the specified time duration of a selected operation, and (e) means for terminating said performance when the measured elapsed time equals said specified time duration. The described embodiment utilizes the techniques of an electronic digital computer and comprises a clock pulse generator 7, Fig. 1, controlling the flow of data in a memory loop including a shift register, having cells CSC-1 to CSC-10, and a delay line 233. The data is represented in Fig.2 as arranged in ten fields A to J of twelve bit positions BP1 to BP12. The bits SC in Field A represent sixtieths of a second, and the bits ETC in Field B seconds, of elapsed time. In Fields C to J the bits SSLI sequence the loading of the memory from the computer interface 13, the bits S1FA, S2FA, &c., denote the first and second functions, &c., to be performed, the bits S1SR denote which state is active, and the bits S1TO, S2TO, etc. denote the scheduled durations of the various functions. The bits SC and ETC are produced by a "sidereal time control" 11, the time base of which is derived from a 60 cycle power supply. At the commencement of a programme the S1FA bits are stored in an output function buffer 14 and a register 15, and the S1TO bits stored in a buffer 16. The S1SR bit in Field C is a binary one to indicate that the Field C is active. Elapsed time is counted in Field B in response to timing pulses produced by the "sidereal time control" 11, and when the elapsed time equals the scheduled duration stored in the buffer 16 a comparator 17 activates the active state control 18 to stifle the S1SR-1 bit from Field S to Field D, so that the operations controlled by the Field C are terminated and those controlled by the Field D commanded, to be terminated and followed in a similar manner by those controlled by Fields E to J.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US56548766A | 1966-07-15 | 1966-07-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1184932A true GB1184932A (en) | 1970-03-18 |
Family
ID=24258823
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB31089/67A Expired GB1184932A (en) | 1966-07-15 | 1967-07-06 | Sequence of Operations Performance Controller |
Country Status (4)
Country | Link |
---|---|
US (1) | US3434115A (en) |
DE (1) | DE1588344A1 (en) |
FR (1) | FR1529036A (en) |
GB (1) | GB1184932A (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3967245A (en) * | 1970-03-06 | 1976-06-29 | Omron Tateisi Electronics Co. | Traffic signal control device with core memory |
US3629844A (en) * | 1970-06-01 | 1971-12-21 | Allied Management & Systems Co | Multifunction routing network |
US3651477A (en) * | 1970-06-18 | 1972-03-21 | Struthers Dunn | Process control system |
FR2145427B1 (en) * | 1971-07-15 | 1976-09-17 | Sfim | |
US3731282A (en) * | 1971-08-27 | 1973-05-01 | Allied Management & Systems Co | Multifunction routing network |
US4008404A (en) * | 1975-12-29 | 1977-02-15 | Honeywell Inc. | Interval timer |
US4139900A (en) * | 1976-10-21 | 1979-02-13 | Rca Corporation | Ground station data storage system |
US4077011A (en) * | 1976-12-20 | 1978-02-28 | International Business Machines Corporation | Uncertain interval timer using a variable length shift register |
US4161787A (en) * | 1977-11-04 | 1979-07-17 | Motorola, Inc. | Programmable timer module coupled to microprocessor system |
US4326207A (en) * | 1977-11-18 | 1982-04-20 | Hitachi, Ltd. | Programmable sequence controller |
US4231106A (en) * | 1978-07-13 | 1980-10-28 | Sperry Rand Corporation | Performance monitor apparatus and method |
US4262331A (en) * | 1978-10-30 | 1981-04-14 | Ibm Corporation | Self-adaptive computer load control |
US4321687A (en) * | 1979-10-01 | 1982-03-23 | International Business Machines Corporation | Timing pulse generation |
US4677541A (en) * | 1984-09-24 | 1987-06-30 | Rauland-Borg Corporation | Programmable clock |
KR102521054B1 (en) | 2017-10-18 | 2023-04-12 | 삼성전자주식회사 | Method of controlling computing operations based on early-stop in deep neural network |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3254324A (en) * | 1961-01-13 | 1966-05-31 | Casciato Leonard | Traffic signal systems |
US3275989A (en) * | 1961-10-02 | 1966-09-27 | Burroughs Corp | Control for digital computers |
US3206721A (en) * | 1962-05-28 | 1965-09-14 | Bunker Ramo | Traffic control system |
US3275994A (en) * | 1963-12-30 | 1966-09-27 | Sperry Rand Corp | Data processing system |
US3281782A (en) * | 1964-01-17 | 1966-10-25 | Gen Signal Corp | Traffic signal controller |
US3302170A (en) * | 1964-04-28 | 1967-01-31 | Ibm | Traffic light control buffer |
US3333246A (en) * | 1964-07-08 | 1967-07-25 | Ibm | Delay line clock |
-
1966
- 1966-07-15 US US565487A patent/US3434115A/en not_active Expired - Lifetime
-
1967
- 1967-06-12 FR FR8554A patent/FR1529036A/en not_active Expired
- 1967-07-06 GB GB31089/67A patent/GB1184932A/en not_active Expired
- 1967-07-14 DE DE19671588344 patent/DE1588344A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
FR1529036A (en) | 1968-06-14 |
US3434115A (en) | 1969-03-18 |
DE1588344A1 (en) | 1970-10-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PCNP | Patent ceased through non-payment of renewal fee |