JPH04155863A - Cmos type semiconductor device - Google Patents

Abstract

PURPOSE:To enhance CMOS circuits in degree of integration by a method wherein P-channel transistors different in source voltage are formed on the same N-type well when the CMOS circuits correspondent to power supply voltage systems are formed on the P-type silicon substrate. CONSTITUTION:A P-channel transistor 24 serving as a CMOS inverter of a 5V power supply system circuit 21 of a CMOS semiconductor device is composed of an active region 33a and a gate region 34a which serve as a source and a drain respectively enabling an N-type well 32 to which a voltage of 5V is supplied from a 5V wiring region 37a through the intermediary of a well connection region 35 to serve as a substrate voltage. A P-channel transistor 26 serving as a CMOS inverter of a 3.3V power supply system circuit 23 is composed of an active region 33b and a gate region 34b which serve as a source and a drain respectively enabling the N-type well 32 to which a voltage of 5V is supplied from the 5V wiring region 37a through the intermediary of the well connection region 35 to serve as a substrate voltage. N-channel transistors 25 and 27 serving as CMOS inverters are formed on a region kept at a ground potential other than the N well 32 on a P-type silicon substrate 31.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in CMOS type semiconductor devices.

(Prior Art) In recent years, semiconductor devices, especially DRAM (Dyna
sic Random Access Mellory
), the channel length of transistors has also been reduced. As the channel length becomes shorter,
Deterioration of transistor reliability due to hot carrier effects has become a problem. To obtain a highly reliable transistor, it is necessary to reduce the voltage difference between the source and the train of the transistor.

Therefore, for example, in a 16M bit DRAM, in addition to the standard power supply voltage of 5V, a voltage lower than 5V,
For example, a power supply voltage system of 3.3 V is provided, and this voltage is used in a region of the transistor channel length where the hot carrier effect is likely to occur.

FIG. 7 shows an example of the circuit of this conventional CMO8 type semiconductor device. The CMO8 type semiconductor device is a 5V power supply system CMO.
This is a circuit configuration diagram of a semiconductor device having two types of circuits: an S inverter and a 3.3■ power system CMOS inverter.

In the same figure, 1 is a 5V power supply line, 2 is a grounding line, 3 is 3,
3 ■ Power line, 4 is the P channel (hereinafter referred to as Pch) of the 5V power system CMOS inverter between the 5V power line 1 and the ground line 2.
The substrate voltage of the P ch transistor 4 is connected to the 5V power supply line 1. 5 is 5
■N channel of power system CMOS inverter (hereinafter referred to as
(abbreviated as Nch) transistor. Also, 6 is 3.3
There is a 3.3V Pch transistor of a CMOS inverter in the power supply system between the V power line 3 and the ground line 2, and the substrate voltage of the Pch transistor 6 is connected to the 3.3V power line 3. Further, 7 is an Nch transistor of a CMOS inverter of a 3.3V power supply system.

FIG. 8 is a mask layout diagram of a CMO5 type semiconductor device used when forming a circuit of the CMO3 type semiconductor device shown in FIG. Two independent N-type wells are formed on a P-type silicon substrate, and a 5V power supply CMOS
It has two types of circuits: an inverter and a 3.3V power system CMOS inverter.

In the same figure, 11 is a P-type silicon substrate, 12a is a 5V
12b is an N-type well with a voltage of 3.3V; 13a, 1'3b, 13c, and 13d are transistor active regions; 14a, 14b;

14c and 14d are gate regions, 15g is a well voltage connection region of the N-type well with a voltage of 5V, 15b is a well voltage connection region of the N-type well 12a with a voltage of 3°3V, 16 is a contact region, 17a is a 5V wiring region, 17b is the 3.3v wiring area, 17c is the ground voltage wiring area, 18a, 18b,
18c and 18d are other wiring areas.

The P ch transistor 4 of the 5V power system CMOS inverter shown in the circuit of FIG. 7 is composed of an active region 13a serving as a source/drain and a gate 14a.

In addition, the P ch transistor 4 has a wiring area 17 of 5.
The N-type well 12a, to which a voltage of 5cm is supplied from a to the well connection region 15a, is used as the substrate voltage.

In addition, the Pch transistor 6 of the 3.3V power system CMOS inverter has an active region 13b that becomes the source and drain.
and a gate 14b, and the Pch transistor 6 is configured from a 3.3V wiring region 17b to a well connection region 15b.
N-type well 12b supplied with a voltage of 3.3V through
is taken as the substrate voltage.

(Problem to be solved by the invention) However, in the conventional configuration as described above, the N-type well 12a in which the Pch transistor 4 of the 5V power supply system is formed.
and the N-type well 12b where the Pch transistor of the 3.3V power supply system is formed.
There are type wells, and it is necessary to provide an isolation region on the layout to separate the wells of different voltages. Furthermore, it is necessary to provide power supply lines for supplying voltages to the two types of N-type wells. In this way, securing isolation regions between wells with different voltages and adding power supply lines for the wells imposes layout constraints, and these points are important for semiconductor devices to become highly integrated. This was a problem above.

In view of this point, the present invention provides a C with two power supply systems with the same well voltage, which conventionally differs depending on the power supply system.
The purpose is to provide an MO8 type semiconductor device.

(Means for Solving the Problem) In order to achieve the above object, the solving means of the present invention includes a silicon substrate of one conductivity type, a well formed in the silicon substrate and of a conductivity type opposite to that of the silicon substrate, A first transistor and a second transistor formed in the well and having the same conductivity type as the silicon substrate, a first power supply line to which the well and the source of the first transistor are connected, and the second transistor a second power supply line to which a source of the transistor is connected; a third transistor and a fourth transistor formed in a region of the silicon substrate other than the well and having a conductivity type opposite to that of the silicon substrate; a third power line to which the source of the transistor is connected; a fourth power line to which the source of the fourth transistor is connected; the first transistor, the third transistor, and the second transistor; Each of the fourth transistors has a connected drain, and the potential of the second power supply line is set between the potential of the first power supply line and the potential of the third power supply line, and The potential of the fourth power line is set between the potential of the second power line and the potential of the third power line, and the potential of the area other than the well of the silicon substrate is
The potential is the potential of the third power supply line.

(Function) With the above-described configuration, the present invention allows a plurality of Pch transistors having different source voltages to be connected to the same NMOS circuit when forming a CMOS circuit corresponding to a plurality of power supply voltage systems on a P-type silicon substrate. By forming the N-type well on the N-type well, N-type wells can be formed.
Since there is no need to provide isolation regions between mold wells, it is possible to improve the degree of integration of a plurality of CMOS circuits.

Similarly, N
When forming on a type silicon substrate, multiple Nch transistors with different source voltages are connected to the same P-type silicon substrate.
To improve the degree of integration of a plurality of CMOS circuits by forming it on the mold well, thereby eliminating the need for a separation region between the P-type wells when forming a plurality of P-type wells as in the past. I can do it.

In that case, if the third power line and the fourth power line are commonly connected and the source voltages of the plurality of transistors formed in areas other than the wells of the silicon substrate are the same voltage, one power line can be omitted, and integration of layers can be achieved. Similarly,
If the first power supply line and the second power supply line are commonly connected and the source voltages of the plurality of transistors formed in the well region of the silicon substrate are set to the same voltage, one power supply line can be connected in the same way as above. Since it can be omitted, the integration of layers can be achieved.

(Embodiment) FIG. 1 shows a circuit configuration diagram of a CMOS type semiconductor device in a first embodiment of the present invention.

In the figure, 21 is a 5V power line as a first power line, 22 is a ground line as a third power line and a fourth power line, and 23 is a second line having a potential between 5V and Ov. This is a 3.3v power line as a power line.

Further, 24 is a Pch transistor as a first transistor constituting a CMOS inverter of a 5V power system between the 5V power line 21 and the ground line 22, and the substrate voltage of the Pch transistor 24 is connected to the 5V power line 21 and Its source is connected to a 5V power supply line 21. In addition, 25
is an Nch transistor serving as the third transistor of the CMOS inverter of the 5V power supply system, and its source is connected to the ground line 22.

Also, 26 is 3.3 ■ 3.3 between the power line 23 and the ground line 22.
A Pch transistor 26 is used as a second transistor of a CMOS inverter in a 3V power supply system, and the substrate voltage of the Pch transistor 26 is connected to a 5V power line 21, and its source is connected to a 3.3V power line 23. 27 is 3
．． This is an Nch transistor as a fourth transistor constituting a CMOS inverter of a 3V power supply system, and its source is connected to the ground line 22.

FIG. 2 is a diagram showing a first example of the mask layout of the circuit configuration diagram of the CMOS type semiconductor device shown in FIG. 1. A P-type silicon substrate is provided as a silicon substrate of one conductivity type, an N-type well is formed on the substrate, and a 5V power supply system CM
It has two types of circuits: an OS inverter and a 3.3V power system CMOS inverter.

In the figure, 31 is a P-type silicon substrate, 32 is formed on the P-type silicon substrate 31, and 32 is formed on the P-type silicon substrate 31.
A well of 5V voltage of the opposite conductivity type, that is, N type, 33
a, 33b, 33c, and 33d are active regions of transistors, and 34a, 34b.

34c and 34d are gate regions, 35 is a well voltage connection region of an N-type well, 36 is a contact region, and 37a is a 5.
The wiring area 37b is a 3.3V wiring area, and 37c is a ground voltage wiring area 38a, 38b.

38c and 38d are other wiring areas.

The first embodiment of the above CMOS type semiconductor device and the mask
The configuration will be described in more detail based on the first example of the layout.

The Pch) transistor 24 of the CMOS inverter in the 5V power supply system of the CMOS semiconductor device circuit shown in FIG.
5V from the 5V wiring region 37a through the well connection region 35.
■The N-type well 32 supplied with voltage is used as the substrate voltage, and the active region 33a and the gate region 34, which become the source train,
It is composed of a.

In addition, Pch of CM OS inverter of 3.3v power supply system
The transistor 26 is also connected to the N-type well 3 to which a 5V voltage is supplied from the 5V wiring region 37a through the well connection region 35.
2 is the substrate voltage, and the active region 3 becomes the source train.
3b and a gate region 34b. In addition, Nch transistors 25 and 27 of both CMOS inverters
is formed in a region of ground potential other than the N-type well 32 in the P-type silicon substrate 31, and includes an active region 33c or 33d that becomes a source/drain, and a gate region 34.
c or 34d, respectively.

Therefore, in this embodiment, in a circuit of a CMOS type semiconductor device having a plurality of power supply systems, a plurality of Pch transistors 24 and 26 corresponding to different power supply systems are provided on the same well 32, so that N-type There is no need to form multiple wells. As a result, there is no need to provide an isolation region that electrically isolates a plurality of N-type wells, which was necessary in the past.

In addition, since there is no need to provide connection wiring for supplying well voltage, which was required in the past when there are multiple wells, the area on the mask layout can be reduced, allowing semiconductor devices to be more highly integrated. can be converted into

Moreover, since the third power line and the fourth power line are shared by the ground line 22, one power line can be omitted, and higher integration is possible.

FIG. 3 shows a circuit configuration diagram of a CMOS type semiconductor device according to a second embodiment of the present invention.

In the figure, 41 is a 5V power line as a first power line and a second power line, 42 is a grounding line as a third power line, and 43 is a 1°7V power line as a fourth power line. be.

Also, 44 is grounded to the 5V power line 41! 5■ between 1!42
The substrate voltage of the Pch transistor 44 of the power system CMOS inverter is 5.
It is connected to the power supply line 41. Further, 45 is an Nch transistor of a CMOS inverter of a 5V power supply system,
The source of the Nch) transistor 45 is connected to the ground line 42. Furthermore, 46 is the P of the CMOS inverter of the 3.3v power supply system between the 5v power line 41 and the 1.7V power line 45.
ch transistor, the Pch transistor 46
The substrate voltage of is connected to a 5V power supply line 41. 47 is an Nch transistor of a CMOS inverter for a 3.3V power supply system, and the source of the Nch transistor 47 is 1.
．． It is connected to the 7V power supply system 43.

FIG. 4 is a second embodiment showing the mask◆layout of the circuit of the CMOS type semiconductor device shown in FIG. An N-type well is formed on a P-type silicon substrate, and a C
It has two types of circuits: a MOS inverter and a 3.3V power system CMOS inverter.

In the figure, 51 is a P-type silicon substrate, 52 is an N-type well with a voltage of 5V, 53a, 53b, 53c, and 53d are transistor active regions, and 54a.

54b, 54c, 54d are gate regions, 55 is a well voltage connection region of an N-type well, 56 is a contact region, 57
a is a 5V wiring area, 57b is a ground voltage wiring area, 57c
is the 1.7v wiring area, 58a.

58b, 58c, and 58d are other wiring areas.

The second embodiment of the above CMOS type semiconductor device and the mask
The configuration will be described in more detail based on the second example of the layout.

The Pch transistor 44 of the CMOS inverter in the power supply system of the circuit of the CMOS type semiconductor device shown in FIG.
5 from the 5V wiring region 57a through the well connection region 55.
An active region 53 is formed in the N-type well 52 to which V voltage is supplied.
a and a gate region 54a.

The Pch transistor 46 of the CMOS inverter for the 3.3V power supply system is also connected from the 5V wiring region 57a to the well connection region 5.
In the N-type well 52 to which a 5V voltage was supplied through 5,
It is configured to have an active region 53b and a gate region 54b.

In addition, CMOS for both 5V power system and 3.3V power system
The Nch transistors 45 and 47 of the inverter are located in a P-type silicon substrate 51 and are each configured to have active regions 53c and 53d serving as sources and drains, and gate regions 54c and 54d.

As described above, in the circuit of a CMOS semiconductor device having multiple power supply systems, multiple P
Since the ch transistors 44 and 46 are provided in the same N-type well 52, eliminating the need to form another N-type well, an isolation region is provided to electrically isolate the two N-type wells as in the conventional method. There's no need. Further, since there is no need to provide connection wiring for supplying well potential to a plurality of wells, no extra mask layout area is required, and the semiconductor device can be more highly integrated.

Moreover, the first power line and the second power line are connected to the 5v power line 4.
Since it is shared by one power supply line, one power supply line can be omitted, and furthermore, it is possible to increase the integration of the negative layer.

FIG. 5 shows a circuit configuration diagram of a CMOS type semiconductor device according to a third embodiment of the present invention.

In the figure, 61 is a 5V power line as a first power line, 62 is a ground line as a third power line, 63 is a 4.15V power line as a second power line, and 64 is a fourth power line. This is a 0.85V power supply line. Further, 65 is a Pch transistor of a 5VuJ CMOS inverter between the 5V power line 61 and the ground line 62, and the substrate voltage of the transistor 5 is connected to the 5V power line 61. Further, 66 is an Nch transistor of a CMOS inverter of a 5V power supply system, and the source of the Nch transistor 66 is connected to the ground line 62. Furthermore, 67 is 4.1
A Pch transistor of a CMOS inverter in a 3.3V power system between a 5V power line 63 and a 0.85V power line 64, and the substrate voltage of the Pch transistor 7 is connected to the 5V power line 61. Further, 68 is an Nch transistor of a CMOS inverter for a 3.3V power supply system, and the source of the Nch transistor 68 is connected to the 0.85V power supply line 6.
Connected to 4.

FIG. 6 shows a third embodiment of the mask layout of the CMOS semiconductor circuit shown in FIG. 5, in which an N-type well is formed on a P-type silicon substrate and
It has two types of circuits: an S inverter and a 3.3v power system CMOS inverter. In the same figure, 71 is P
type silicon substrate, 72 is an N-type well with a voltage of 5V, 73a
, 73b.

73c and 73d are active regions of transistors, 74a,
74 b, 74 c, and 74 d are gate regions, 75 is a well voltage connection region of the N-type well 72, 76 is a contact region, 77 a is a 5V wiring region, 77b is a ground voltage wiring region, 77c is a 4.15V wiring region, 77d is a 0.85V wiring area. Also, 78a, 78b, 7
8c and 78d are other wiring areas.

The above CMOS type semiconductor device is combined with the third embodiment and the mask φ
The configuration will be explained in more detail based on the third example of the layout.

The Pch transistor 5 of the CMOS inverter in the 5V power supply system of the CMOS semiconductor device circuit shown in FIG.
5V through the well connection area 75 from the 5V wiring area 77a.
■Active region 73 in N-type well 72 supplied with voltage.
a and a gate region 74a.

Also, Pch of 3.3V power system CMOS inverter)
The transistor 7 also has an N-type well 72 to which a 5V voltage is supplied from the 5V wiring region 77a through the well connection region 75.
It is configured to have an active region 73b and a gate region 74b therein.

Furthermore, CMOS for both 5V power system and 3.3V power system
The Nch transistors 66 and 68 of the inverter are located in a P-type silicon substrate 71 and are each configured to have active regions 73c and 73d serving as sources and drains, and gate regions 74c and 74d.

As described above, in a CMOS circuit having multiple power supply systems, a plurality of Pch transistors 5, 67 corresponding to different power supply systems are provided in the same well 72, eliminating the need to form multiple N-type wells. Therefore, there is no need to provide an isolation region to isolate the plurality of N-type wells. Further, since there is no need to provide connection wiring for supplying well voltage to a plurality of wells, an extra area on the mask layout is not required, and the semiconductor device can be highly integrated.

In addition, the above 1. In the second and third embodiments, the substrate voltage of the Nchh transistor is set to the ground voltage, or
An appropriate voltage other than the ground voltage may be applied.

In addition, although 3.3V was used as a power supply system lower than the 5V power supply system, it goes without saying that a power supply system lower than 5■ and different from 3.3■ may be used. It is sufficient to have a plurality of power supply voltages that can configure a low power supply system.

Furthermore, in the above embodiments, an N-type well is formed on a P-type silicon substrate, or a P-type well is formed on an N-type silicon substrate.
Needless to say, a configuration in which a mold well is formed may also be used.

(Effects of the Invention) As explained above, according to the CMOS type semiconductor device of the present invention, when forming a plurality of circuits corresponding to a plurality of different power supply systems on a silicon substrate, Since the conductivity type well is shared regardless of multiple power supply systems, there is no need for a conventional isolation region to separate multiple wells, making it possible to improve the degree of integration of multiple CMOS circuits. Its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a CMOS type semiconductor device showing a first embodiment of the present invention, FIG. 2 is a diagram showing a first embodiment of the mask layout of a CMOS type semiconductor device, and FIG. A circuit configuration diagram of a CMOS type semiconductor device showing a second embodiment of the invention, FIG. 4 is a diagram showing a second embodiment of the mask layout of a CMOS type semiconductor device, and FIG. 5 shows a third embodiment of the invention.
FIG. 6 is a diagram showing a third embodiment of the mask layout of a CMOS semiconductor device, and FIG. 7 is a circuit diagram illustrating a conventional CMOS semiconductor device. 8 are diagrams showing the mask layout of a conventional CMOS type semiconductor device. 21.61...5 ■Power line (first power line), 22.
...Grounding wire (3rd and 4th shared power supply line), 23...
3, 3■ Power supply line (second power supply line), 24...5V power supply system PCh transistor (first transistor), 25
...5V power supply system Nch transistor (third transistor), 26...3.3■ power supply system Pch transistor (second transistor), 27...3°3V power supply system Nch transistor (third transistor) 4 transistors), 31
... P-type silicon substrate, 32...5■ Voltage N-type well, 37a...5■ Wiring area, 37b, ...3.3
■Wiring area, 37c... Ground voltage wiring area, 41...
・5V power line (first and second shared power line), 42.6
2...Grounding wire (third power line), 43...1°7V
Power line (fourth power line), 63...4.15V power line (second power line), 64...0.85V power line (fourth power line)
power line). Patent applicant Matsushita Electronics Co., Ltd.

Claims (3)

[Claims] (1) a silicon substrate of one conductivity type, a well formed in the silicon substrate and of a conductivity type opposite to that of the silicon substrate, and a first well formed in the well and of the same conductivity type as the silicon substrate;
a first power line to which the well and the source of the first transistor are connected; a second power line to which the source of the second transistor is connected; and the silicon substrate. a third transistor and a fourth transistor formed in a region other than the well and having a conductivity type opposite to that of the silicon substrate; a third power supply line to which the source of the third transistor is connected; a fourth power supply line to which the sources of the four transistors are connected; the first transistor and the third transistor;
and a drain connected to each of the second transistor and the fourth transistor, and the potential of the second power supply line is equal to the potential of the first power supply line and the potential of the third power supply line. The potential of the fourth power line is set between the potentials of the second power line and the third power line, and the potential of the fourth power line is set between the potentials of the second power line and the third power line, and the potential of the fourth power line is set between the potentials of the second power line and the third power line. A CMOS type semiconductor device, wherein the potential is the potential of the third power supply line. (2) The CMOS type semiconductor device according to claim (1), wherein the third power line and the fourth power line are commonly connected. (3) The CMOS type semiconductor device according to claim (1), wherein the first power line and the second power line are commonly connected.