JPH0415475B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides a liquid crystal panel divided into upper and lower halves,
The present invention relates to a liquid crystal display controller that drives and controls a liquid crystal module that includes a drive circuit that drives row and column electrodes of this panel.

[Prior art]

Recent liquid crystal display devices usually have the configuration shown in FIG. In this figure, 1 is a CPU (central processing unit), 2 is a liquid crystal display controller, 3 is a display memory, and 4 is a liquid crystal module. Further, the liquid crystal module 4 includes a liquid crystal panel 5 as shown in FIG.
and a panel drive circuit 6 provided around it. For example, the liquid crystal panel 5
It has 640 electrodes and 200 vertical electrodes, and displays images with 640 x 200 dots. Further, this liquid crystal panel 5 is divided into display blocks A and B, and is driven as two panels. Shift register 7a (640 bits), latch 8a (640 bits), electrode drive circuit 9a
are circuits for driving the column electrodes of display block A, respectively;
Shift register 7b (640 bits), latch 8b
(640 bits), the electrode drive circuit 9b is a circuit for driving the column electrodes of display block B, and the shift registers 11a, 11b (100 bits each) and electrode drive circuits 12a, 12b are circuits for driving the row electrodes, respectively. Note that this liquid crystal module 4 is normally manufactured and sold by a panel manufacturer.

In the above configuration, the CPU 1 (FIG. 6) writes image data into the display memory 3, and
A display command is output to the liquid crystal display controller 2.
The liquid crystal display controller 2 receives this display command, reads the image data from the display memory 3, and displays the display data LDa, LDa, based on the read image data.
Creates LDb (serial data) and outputs it to liquid crystal module 4 along with shift clock SCK. Thereby, display data LDa and LDb are sequentially read into shift registers 7a and 7b, respectively. Then, when the display data LDa and LDb (640 bits each) are read into the shift registers 7a and 7b, respectively,
The liquid crystal display controller 2 outputs a latch clock LC and a frame signal FLM, respectively. The output latch clock LC is applied to each load terminal of latches 8a and 8b and shift registers 11a and 11b.
The frame signal FLM is applied to each data input terminal of shift registers 11a and 11b as an upper frame signal FLMa and a lower frame signal FLMb. As a result, the data in shift registers 7a and 7b are transferred to latch 8.
a, 8b, and the shift register 11
A "1" signal is read into the 0th memory cell of cells a and 11b, and the 0th row (top row) and 100th row of the liquid crystal panel 5 are displayed as dots. Next, the liquid crystal display controller 2 outputs data LDa and LDb for displaying each dot on the 1st row and the 101st row, respectively, together with the shift clock SCK, and all data (640 bits) are stored in the shift registers 7a and 7b.
Outputs the latch clock LC when read. As a result, the data in shift registers 7a and 7b are read into latches 8a and 8b, and
A "1" signal is read into the first memory cell of the shift registers 11a and 11b, and dots are displayed on the first and 101st rows of the liquid crystal panel 5.
Thereafter, the above process is repeated to perform panel display. Note that the frame signal FLM is output once per frame scan (at the start of scanning). Also, the frame frequency is usually 70Hz.

[Problem that the invention seeks to solve]

Incidentally, there are various types of liquid crystal panels having the number of vertical electrodes, such as 192, 204, etc., in addition to the 200 described above. Now, if the program for CPU 1 is a program that targets a 640 x 204 dot LCD panel, if that program were to drive a 640 x 192 dot LCD panel, of course some of the displayed image would be missing, making it unsatisfactory. cannot be displayed. On the other hand, if the program for CPU 1 is a program that targets a 640 x 192 dot panel and that program drives a 640 x 204 dot LCD panel, the display will be able to be displayed to some extent, but the following problems will occur. .

That is, as described above, the liquid crystal panel 5 is divided into upper and lower display blocks A and B, and each display block A and B is driven as a separate panel. Further, each row electrode of each display block A, B is sequentially driven from the top one. As a result, when a 640 x 204 dot panel is driven by a 640 x 192 dot program, only 96 lines each of the upper and lower display blocks A and B are driven, so the image of display block A and the display are as shown in Figure 8. A gap will be created between the block B image and the block B image. Therefore, conventionally, 640
If a program for 192 x 192 dots was already prepared, but only a 640 x 204 dot panel could be prepared, the already completed program had to be changed. In this case, the display memory 3 also contains the non-display area of the panel (640×
Blank data had to be written in the storage area corresponding to the area (areas other than 192 dots), which was wasteful in terms of memory capacity.

Therefore, this invention makes it possible to perform correct display with almost no changes to the original program when the number of row electrodes on the panel increases, and also eliminates the need to write extra blank data to the display memory. It is not intended to provide an LCD display controller.

[Means to solve the problem]

In this invention, the register into which data from the outside (CPU) is written and the upper frame signal for the upper display block are set a latch signal period earlier than the lower frame signal for the lower display block by the latch signal period corresponding to the data in the register. and a frame signal output means for outputting the frame signal at the same time.

[Effect]

Data corresponding to the number of different row electrodes is written in the register in advance. For example, when driving a 640 x 204 dot panel with a 640 x 192 dot program, data (for example, "1, 1") corresponding to the number of row electrode differences, 12, is written in the register. As a result, the upper frame signal is outputted earlier than the lower frame signal by the latch signal period (in this case, 6 periods) corresponding to the data "1, 1". As a result, after the six row electrodes of the upper display block are driven, driving of the row electrodes of the lower display block is started. If the display data of the upper display block is output at the same timing as the display data of the lower display block,
Since the upper display block is used as a panel of 96 row electrodes, there is no gap between the top and bottom.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a liquid crystal display device to which a liquid crystal display controller 15 according to an embodiment of the present invention is applied. The controller 15 shown in this figure has 640 x 192 dots, 640 x 200 dots, 640
It is designed to be able to drive each of the 640 x 204 dot LCD panels, and can also drive 640 x 200 dot and 640 x 204 dot LCD panels by a 640 x 192 dot program. The program allows it to drive a 640 x 204 dot liquid crystal panel.

To explain in detail below, in FIG. 1, the reference numeral 16 is
CPU, 17 is memory, and this memory 17 is
It consists of a ROM that stores programs used by the CPU 16 and a RAM for data storage. 18 is a display memory into which display data output from the CPU 16 is written, and 4 is a liquid crystal module shown in FIG. The display memory 18 is
It is a 16K byte RAM, and each bit of this memory 18 corresponds to each dot of the liquid crystal panel 5. FIG. 2 is a diagram showing the storage state of this memory 18. As shown in this diagram, the 0th dot of display block A (the leftmost dot in the top row) is located at address 0.
~ The display data of the 7th dot (8th dot from the left on the top row) is stored as “1” or “0”, and 1
The display data of the 8th to 15th dots are stored at the address, and thereafter the display data of each dot of display block A is stored in sequence. Then, following each display data of display block A, display block B
The display data of the 0th dot, 1st dot, etc. are sequentially stored. Therefore, the liquid crystal panel 5
In the case of 640 x 192 dots, display data is stored between address 0 and 80 x 96 x 2 = 15360 (bytes). Here, 80 (bytes) is the memory capacity in which one line (640 dots) of display data is stored. Similarly, the liquid crystal panel 5
If is 640 x 200 dots, the display data will be between address 0 and 80 x 100 x 2 = 16000 (bytes), and if it is 640 x 204 dots, the display data will be between 80 x 102 x 2 = 16302 (bytes). is memorized. Further, as display data, "11" is stored when the dot is to be displayed, and "0" is stored when the dot is not to be displayed.

Next, in the controller 15, the display control circuit 19 reads each data in the display memory 18 and outputs the read data as display data LDa, LDb. Note that details will be described later. The clock pulse generator 20 is a circuit that generates a basic clock pulse φ0 and a clock pulse φ1 obtained by dividing this clock pulse φ0 into 1/4 (see FIGS. 3A and 3C). A flip-flop (hereinafter abbreviated as FF) 21 is an FF triggered by a clock pulse φ1, and its Q output is output as a clock pulse φ2 (see FIG. 3C). The horizontal counter 22 is a 7-bit up counter that is triggered at the falling edge of the clock pulse φ2, and is reset at the falling edge of the signal TG supplied to its reset terminal R. The decoder 23 receives the count output of the horizontal counter 22 as “3”, “83”,
This is a decoder that outputs a "1" signal from each output terminal when it is "85". 24 is AND gate, 26 is FF
It is. This FF 26 is set/reset at the falling edge of the signals supplied to its set terminal S and reset terminal R, respectively. 29 is a D-type flip-flop (hereinafter referred to as D-FF) which delays the input signal by one cycle of clock pulse φ2 and outputs the delayed signal.
), 30 to 32 are AND gates.

Next, the vertical counter 35 is a 7-bit up counter that is triggered at the falling edge of the signal TG and reset at the falling edge of the signal supplied to the reset terminal R, and its count output is supplied to the decoder 36 and , display control circuit 19
supplied to The decoder 36 is a vertical counter 35
The count output is "11-7", "12-3", "12-
5" and "13-1", this decoder outputs a "1" signal from each output terminal. In addition, "11-3" is
This means that the output data of the upper 4 bits of the vertical counter 35 is "11" and the output data of the lower 3 bits is "3". The same applies to others.
38-40 are the same flip-flops as FF26,
41 to 43 are AND gates, 44 is OR gate,
45 is a register. This register 45 is a 3-bit register, and 3-bit panel data PD output from the CPU 16 is written therein. Here, if the program for CPU 16 is a program that targets a 640 x 192 dot LCD panel,
“001” in register 45 as panel data PD
(0th bit is “1”) is written, and in the case of a 640 x 200 dot program, “010” is written, and 640
In the case of a x204 dot program, "100" is written. Then, the 0th bit PD0 of the data PD written in this register 45 is the AND gate 4
3, the first bit PD1, the second bit PD2
are supplied to AND gates 42 and 41, respectively.

Next, 47 and 48 are AND gates, and 49 is a 3-bit up counter. This counter 49
is triggered on the falling edge of the signal supplied to its clock terminal CK, and reset on the falling edge of the signal supplied to its reset terminal R. 50 to 53 are AND gates, 54 is a NAND gate, 55 to 57 are inverters, and 59 is a comparator. This comparator 59 compares the first and second bits of the count output of the counter 49 with the inverter 5.
The output signals of 6 and 57 are compared, and when the two match, a match signal EQ (“1” signal) is output. 60 is a 2-bit register, into which 2-bit difference number data DF output from the CPU 16 is written.
Here, the difference number data DF is data corresponding to the difference between the number of row electrodes of the liquid crystal panel scheduled to be used in the program of the CPU 16 and the number of row electrodes of the liquid crystal panel actually used. The example is defined as follows:

Difference in number of row electrodes DF1 DF0 12 1 1 8 1 0 4 0 1 0 0 0 Next, the operation of the controller 15 having the above configuration will be explained with reference to the timing diagrams shown in FIGS. 3 to 5.

First, assuming that the clock pulse φ0 is shown in FIG. 3A, the clock pulses φ1 and φ2 are each as follows.
The waveforms shown in b and c in the same figure are obtained, and the clock pulse φ
The count output of the horizontal counter 22 triggered by 2 changes as shown in FIG. 3D. Next, the FF 26 is set by the signal at the output terminal 3 of the decoder 23 and reset by the signal at the output terminal 83 of the decoder 23. Therefore, the signal HD output from the output terminal Q of this FF26 has the waveform shown in Fig. 3 E, and the D-FF
The output of 29 has the waveform shown in FIG. next,
AND gate 24 is output terminal 85 of decoder 23
This is a circuit that ANDs the signal .phi.2 and the clock pulse .phi.2, and therefore its output signal TG has the waveform shown in FIG. And this signal TG
The horizontal counter is reset at the falling edge of
The vertical counter 35 is also triggered. Therefore, the output of the vertical counter 35 changes as shown in FIG. In addition, in this Figure 3,
The number to the left of “-” is the top 4 of the vertical counter 35
The numbers on the right side indicate the lower 3 bits. Next, the AND gate 47 is a circuit that ANDs the signal TG and the clock pulse φ1.
Therefore, the output signal has the waveform shown in FIG. This signal is then supplied to the liquid crystal module 4 as a latch clock LC.

Next, the vertical counter 35 is triggered by the signal TG and reset at the falling edge of the signal at the output terminal 13-1 of the decoder 36. Therefore, the signal
If the TG (see FIG. 3, G) is as shown in FIG. 4, B, the count output of the vertical counter 35 changes as shown in FIG. 4, C. Note that FIG. 4C shows only the upper four bits of the count output of the vertical counter 35. The signal HD shown in Figure 4 A and Figure 3 E
is shown again. Next, FFs 40 to 38 are each set at the falling edge of the signal at the output terminal 13-1 of the decoder 36, and are set at the output terminals 11-7, 1 of the decoder 36.
It is reset at the falling edge of each signal 2-3 and 12-5. Therefore, each of the Q output signals of these FFs 40 to 38 has a waveform shown in FIG. 4D to F, respectively.

Next, if the output of the vertical counter 35 (see FIG. 4 C) is shown in FIG. 5 A, then the signal TG
(Figure 3) is shown by the waveform shown in figure 3(b).Next, the AND gate 48 is a circuit that ANDs the signal at the output terminal 12-3 of the decoder 36 and the signal TG. , the output signal TRA has the waveform shown in FIG. When is reset, the output of the NAND gate 54 becomes "1", and from then on, the signal TG (FIG. 5B) is supplied to the clock terminal CK of the counter 49 via the AND gate 50, thereby causing the output of the counter 49 to become "1". changes as shown in FIG.
The output of the counter 49 becomes "0", and therefore the AND gate 50 is closed, and henceforth, the count output of the counter 49 is held at "7". Then, when the signal TRA is again supplied to the reset terminal R of the counter 49, the counting shown in FIG. 5D is performed again.

Next, if the difference number data DF in the register 60 is “00” (decimal number “0”), the inverter 56,
The output of the comparator 57 becomes "1, 1", so when the count output of the counter 49 is "6, 7", the output signal EQ of the comparator 59 becomes "1". Also,
The output of the inverter 55 becomes "1" when the count output of the counter 49 is "6". Therefore, the AND gate 53 is open when the count output of the counter 49 is "6". Then, when the AND gate 53 becomes open, the signal TG passes through the AND gate 53 to the upper frame signal.
Liquid crystal module 4 as FLMa-0 (Fig. 5 E)
Output to. Similarly, when the difference number data DF in the register 60 is “01” (decimal number “1”), “10” (decimal number “2”), and “11” (decimal number “3”), the counter 49 When the count output is "4", "2", and "0", the AND gate 53 is open, and the signal TG is passed through the AND gate 53 to the upper frame signal.
FLMa-1 (Fig. 5 f), FLMa-2 (Fig. 5 g),
Liquid crystal module 4 as FLMa-3 (Figure 5)
Output to. Next, the AND gate 52 is opened when the count output of the counter 49 is "6". When the AND gate 52 is opened, the signal TG is outputted to the liquid crystal module 4 as a lower frame signal FLMb (see FIG. 5) via the AND gate 52. In this way, the lower frame signal FLMb always occurs at the same timing,
The upper frame signal FLMa is generated at different timings depending on the difference number data DF in the register 60. Note that the above-mentioned upper frame signal FLMa-0~
3 and lower frame signal FLMb, respectively, as shown in Figure 4.
It is shown in the table below. In addition, the latch clock shown in Figure 3
LC is transferred to E in FIG. 4, and the upper frame signal FLMa-0 shown in E in FIG. 5 is transferred to N in FIG. 3.

The above are the output waveforms and output data of each part of the controller 15, and the operations shown in FIGS. 3 to 5 described above are constantly repeatedly executed after the power is turned on.

Next, the overall operation will be explained. When displaying on the liquid crystal panel 5, the CPU 16 first outputs panel data PD (3 bits) and difference number data DF (2 bits). Now, suppose that the program of the CPU 16 is a program for driving a 640 x 192 dot panel, and that the liquid crystal panel 5 in the liquid crystal module 4 is also a 640 x 192 dot panel.
CPU16 sets “001” as panel data PD,
Also, "00" is output as the difference number data DF. The output data PD and DF are written into registers 45 and 60 by display control circuit 19, respectively. When data "001" is written into the register 45, the AND gate 43 becomes open, and the Q output of the FF 40 shown in FIG. Ru. Next, the CPU 16 sequentially outputs display data. The output display data is written into the display memory 18 via the display control circuit 19. Next, the CPU 16 outputs a display command. After this display command is output, the display on the liquid crystal panel 5 is performed through the following process.

That is, first, the display control circuit 15 waits until the count output of the vertical counter 35 becomes "0-0", and then starts the signal HD from the time it reaches "0-0" (see time t0 shown in FIG. 3). Wait for the rise of the clock pulse φ2, and from the time when the signal HD rises (time t1 in the figure), the period of one cycle of the clock pulse φ2 (time t1 to t2)
Then, the display block A (FIG. 7) is transferred from the display memory 18.
The display data (1 byte) of the 0th to 7th bits of the display block B and the display data (1 byte) of the 0th to 7th dots of the display block B are read out. Note that this read address is created based on the count output of the vertical counter 35. Next, display control circuit 19
At times t2 to t3, the display data of display block A is output as display data LDa, and the display data of display block B is output as display data LDb, one bit at a time, sequentially at the timing of clock pulse φ0. Further, at the same time t2 to t3, the display data of the 8th to 15th dots of display block A and the display data of the 8th to 15th dots of display block B are read out, respectively. Next, the display control circuit 19 controls the time
8th to 15th of display blocks A and B at t3 to t4
The display data of each dot is output at the timing of clock pulse φ0, and the display data of display blocks A and B are
The display data of the 16th to 23rd dots are read out, and the above operations are repeated.

On the other hand, the signal HD rises to the "1" signal, and then the output of the D-FF29 at time t2 (see Fig. 3)
When the signal rises to "1", the AND gate 30 is opened, and the clock pulse φ0 is supplied to the liquid crystal module 4 as the shift clock SCK via the AND gate 30. Also, D-FF2
When the signal VD (see FIG. 4 D) rises to a "1" signal due to the output of the vertical counter 35 becoming a "1" signal and the count output of the vertical counter 35 becoming "0-0", AND gates 31 and 32 are both in an open state, and display data LDa and LDb are supplied to liquid crystal module 4 via AND gates 32 and 31, respectively. Then, the display data LDa and LDb are respectively read into shift registers 7a and 7b in FIG. 7 based on the shift clock SCK.

Next, when the signal HD falls to "0" at time t5 shown in FIG. 3, the display control circuit 19 stops reading out the display data, and then at time t6, outputs the display data LDa and LDb. Stop. At this time t6, the shift register 7 in FIG.
Display data for displaying each dot in the 0th row (top row) of display blocks A and B is read into a and 7b, respectively. Next, time t7 in Figure 3
~t8, the latch clock LC and the upper frame signal FLMa-0 are each output to the liquid crystal module 4, and at the same time, the lower frame signal FLMb is output to the liquid crystal module 4.
(FIG. 5) is output, "1" is read into the 0th memory cell of the shift registers 11a and 11b in FIG.
The display data in 7b is read into latches 8a and 8b, thereby causing each 0th
The dots on the row are displayed.

Next, when the signal HD rises again at time t9 in FIG. The data is outputted from the display control circuit 19 as a signal and read into the shift registers 7a and 7b in FIG. Next, at time t10, when the latch clock LC is output to the liquid crystal module 4, the display data in the shift registers 7a and 7b are read into the latches 8a and 8b, and
"1" is read into the first memory cell of the shift registers 11a and 11b, and the table of the first row of each of display blocks A and B is thereby performed. below,
Similarly, the dots in each row of display blocks A and B are sequentially displayed. Then, at time t11 shown in FIG. 4, the display of all dots on the liquid crystal panel 5 is completed,
At this time, the signal VD shown in FIG. 4D falls to "0". Next, at time t12 shown in the figure, when the output of the vertical counter 35 becomes "0-0" again, dot display is performed on the liquid crystal panel 5 in exactly the same process as described above.

In the above description, after the display control circuit 19 receives a display command from the CPU 16,
Although it is assumed that the wait is waited until the count output of the vertical counter 35 becomes "0-0", this wait may not be performed. If waiting is not performed, the first dot display will be performed not from the 0th line of display blocks A and B but from an intermediate line.

The above is the operation when the panel data PD is "001" and the difference data DF is "00". If panel data PD is “010” and difference number data DF is “00”, panel data PD is “100” and difference number data DF
Each operation when is “00” is almost the same as above,
Therefore, the explanation will be omitted.

Next, if the panel data PD is "001" and the difference number data DF is "11", that is, the CPU 16 program is intended for a 640 x 192 dot panel, and the LCD module 4 actually used is
The following describes the operation when the panel has a panel of 640×204 dots (difference in the number of row electrodes=12). In this case, the timing at which the display control circuit 19 reads display data from the display memory 18 and outputs it as data LDa and LDb, the timing at which the latch clock LC and shift clock SCK are output to the liquid crystal module 4, and the timing at which the lower frame signal FLMb is output from the liquid crystal module The timings at which the signals are outputted to 4 are exactly the same as in the above-mentioned cases. The only difference is the timing at which the upper frame signal FLMa is output to the liquid crystal module 4. In other words, the difference count data
When DF is "11", as mentioned above, the upper frame signal FLMa-3 shown in FIG.
is output to the liquid crystal module 4. Now, at time t13 shown in FIG. 4, the upper frame signal FLMa-
3 is output, the shift register 11a (seventh
"1" is read into the 0th memory cell in the figure, and the 0th row of display block A is thereby driven. By the way, the AND gate 32 in FIG.
31 are both closed at the time t11 shown in FIG. The gate 30 (Fig. 1) is connected to D even at times t11 to t13 (Fig. 4).
- When the output of the FF 29 is "1", it becomes open, and therefore the shift clock SCK is supplied to the clock input terminals of the shift registers 7a and 7b. Furthermore, the latch clock LC is constantly supplied to the liquid crystal module 4, as shown in FIG. As a result of the above, the data in the latches 8a and 8b (Fig. 7) are all "0" at time t13, so even if the 0th line of display block A is driven at the same time t13, , is never displayed on the 0th line. Thereafter, each time the latch clock LC is supplied to the liquid crystal module 4, the "1" signal in the shift register 11a is sequentially shifted, thereby causing the first line, second line, etc. of the display block A to be shifted.
The fifth row is sequentially driven. However, in this case, no actual display is performed as in the case described above.

Therefore, as mentioned above, at time t13 in FIG.
The latch clock LC is output six times between time t12 and time t12, and the 0th to 5th rows of display block A are driven. Next, when time t12 is reached, the output of the vertical counter 35 becomes "0-0", and from then on, the display data LDaLDb is output to the liquid crystal module 4 in exactly the same manner as in the case described above, and the shift register 7
A, 7b are read sequentially. Then, when the latch clock LC and the lower frame signal FLMb (FIG. 4) are output at the time (t14) when 640 bits of data are read into each of the shift registers 7a and 7b, "1" in the shift register 11a is output. The signal is shifted, and a “1” signal is read into the shift register 11b, and the shift register 7
The data in a, 7b is read into latches 8a, 8b. As a result, the 6th line of display block A and the 0th line of display block B are displayed. At this point, the sixth display block of display blocks A and B
The data displayed on the 0th line and the 0th line are the same as the data displayed on the 0th line of display blocks A and B in the case of the 192-line panel described above. Thereafter, each row of display blocks A and B is sequentially displayed in the same manner as in the case described above.

According to the above process, display block B
are displayed sequentially from the 0th line, while display block A is displayed from the 6th line. As a result, the number of row electrodes of display block A is 102, and the CPU 16
If the program targets a panel with 192 lines (96 lines on one side), there will be no gap between the display image of display block A and the display image of display block B.

Next, when the panel data PD is "001" and the difference number data DF is "10", that is, the program of the CPU 16 targets a panel of 640 x 192 dots,
If the panel actually used is a panel with 640 x 200 dots (difference in the number of row electrodes = 8), the upper frame signal
Upper frame signal shown in Figure 4 as FLMa
FLMa-2 is output to the liquid crystal module 4. The latch clock LC is output four times between the rising edge of the upper frame signal FLMa-2 and time t12 in FIG. That is, in this case,
The 0th to 3rd lines of display block A are not displayed, and the display starts from the 4th line. Similarly, when the panel data PD is “010” and the difference number data DF is “0,
1'', display starts from the second line of display block A.

Note that in each of the above cases, display block B
Of course, the portion at the bottom corresponding to the non-display area of display block A also becomes a non-display area. It is also possible to make the entire non-display area "black". In this case, when the signal VD (FIG. 4 D to F) is "0", "1" is sent to the data input terminals of the shift registers 7a and 7b.
It is sufficient to apply .

〔Effect of the invention〕

As explained above, according to the present invention, even when the number of row electrodes on a liquid crystal panel increases, the original program can hardly be changed and unnecessary blank data can be written in the display memory. The effect of correct display can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a liquid crystal display device using a liquid crystal display controller 15 according to an embodiment of the present invention, FIG. 2 is a diagram showing the data storage state of the display memory 18 in FIG. 1, and FIG. Figures 1 to 5 each show the liquid crystal display controller 1 shown in Figure 1.
FIG. 6 is a block diagram showing the configuration of a general liquid crystal display device, FIG. 7 is a block diagram showing the configuration of the liquid crystal module 4 in FIG. 6, and FIG. By a program targeting a 640 x 192 dot LCD panel
FIG. 3 is a diagram for explaining problems when driving a 640×204 dot panel. 4...Liquid crystal module, 5...Liquid crystal panel, 6
... Panel drive circuit, 48, 50-53 ... AND gate, 54 ... NAND gate, 55-57...
...Inverter, 59...Comparator, 60...Register.

Claims (1)

[Scope of Claims] 1. A liquid crystal panel divided into upper and lower display blocks, and a drive circuit for driving the row and column electrodes of this liquid crystal panel, respectively, to which an upper frame signal and a lower frame signal are respectively supplied. From this point on, in a liquid crystal display controller that drives and controls a liquid crystal module configured such that each row electrode of the upper and lower display blocks is sequentially driven at the timing of the latch signal, there is a register into which external data is written, and the upper frame signal. frame signal output means for outputting the lower frame signal at a time point corresponding to the data in the register by a latch signal cycle corresponding to the data in the register.