JPH04151700A - Pattern matching control circuit - Google Patents

Abstract

PURPOSE:To shorten a necessary write time and to increase the processing speed of the whole voice recognition device by giving a common address area to input data storage parts that plural pattern matching means have internally and writing input pattern data of respective voice sections in the input data storage parts at the same time. CONSTITUTION:The address signal input terminals, data input terminals, write signal terminals, and chip select signal terminals of the input data memories 201-206 are connected in parallel and a common address signal, input data, a write signal, and a chip select signal are supplied to the respective input data memories. Therefore, a CPU can write input pattern data in the #1-#6 input data memories 201-206 at the same data write time TW1=TW2=...=TW6 in parallel. Consequently, the time required to write the input pattern data in the pattern matching means is shortened greatly and the processing speed of the whole voice recognition device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern matching control circuit that controls a plurality of pattern matching means provided in a speech recognition device.

[Prior Art] Conventionally, in speech recognition devices, etc., a large number of dictionary patterns are stored in a large number of memories, a pattern matching circuit is provided for each of these large numbers of memories, and processing is performed by parallel operation of the pattern matching circuits. There are many things going on.

FIG. 2 is a block diagram showing the configuration of a conventional speech recognition device. In the figure, 1-1, 1-2, . . . are dictionary pattern memory sections in which dictionary patterns with different contents are stored, respectively, and 2-1, 2-2, . . . are dictionary pattern memory sections. 1-1, 1-2, . . . are pattern matching circuits provided respectively.

This pattern matching circuit 2-1 (1-1, 2,
) is supplied with the feature quantity (also called a feature pattern, in this example, the frequency component of the audio signal is used as the feature quantity) extracted from the input pattern (written in the built-in data storage unit). Then, the dictionary pattern memory unit 1-1 (1-1, 2,...
・Compare the dictionary patterns stored in ) and find the dictionary pattern that is most similar to the feature amount among the dictionary patterns,
Distance data (data indicating similarity) between the two is calculated. This is called pattern matching processing, and a processing method such as DP (dynamic programming) matching using dynamic programming is widely known. Reference numeral 3 denotes an input pattern memory, which temporarily stores the input pattern as the feature amount. Reference numeral 5 denotes a control unit which calculates distance data between the input cover pattern and the dictionary pattern calculated by the pattern matching circuit 2-i (i-1, 2, . . . ) by performing pattern matching processing, respectively. This is the part that selects the one with the smallest value and performs speech recognition. A display section 6 displays the category name for which the control section 5 has performed voice recognition. Reference numeral 7 denotes a sub-control unit, which based on the matching start signal or matching stop signal supplied from the control unit 5, outputs an input cover turn read signal to be supplied to the input cover turn memory 3, and a counter up signal to be supplied to the address counter 8. Outputs counter clear signal. Reference numeral 8 designates an address counter, which supplies a count value obtained by counting the counter up signal under the control of the sub-control unit 7 to the input cover turn memory 3 as an address signal. 9 is a microphone;
It converts the input audio signal into an electrical signal and outputs it. 10
is an A/D converter, which converts an input analog signal into a digital signal and outputs it. Reference numeral 11 denotes a pre-processing section, which in this embodiment performs, for example, processing for emphasizing high-frequency components of the audio frequency band. Reference numeral 12 denotes a cutting section, which detects, for example, a section where the audio level is higher than a certain threshold, and performs a process of dividing and cutting out the section as one unit of audio section. Reference numeral 13 denotes a feature calculation unit, which performs calculations for calculating frequency components of a voice signal cut out as one voice section by, for example, autocorrelation processing. - Linear plan for boat fishing #J
(LPC) The above arithmetic processing is performed by signal processing called cepstrum (cepstru*). The clock in the figure is pattern matching circuit 2-1.
It is used as a synchronizing signal for the operation of various parts such as (i-1°2, . . . ) and the sub-control section 7.

The operation shown in FIG. 2 will be explained. The audio signal as an acoustic signal input to the microphone 9 is converted into an analog electrical signal, and the audio signal as an analog electrical signal is converted into a digital audio signal by the A/D converter 10. Since the high frequency components of the audio frequency band are generally at a lower level than the low frequency components, the preprocessing section 11 performs processing to enhance the high frequency components by increasing their level. Next cutout part 1
In step 2, the audio signal is compared with a certain threshold value, and the audio level section above this threshold value is extracted as one unit of audio section. Next, the feature amount calculation unit 13 calculates the frequency component of the audio signal cut out for each section, and supplies this to the input pattern memory 3 as feature amount data. The input cover turn memory 3 stores the feature amount data of the audio signal for each section at the address specified by the address counter 8.

In order to recognize the audio signal stored in the input pattern memory 3, the control section 5 first drives the sub-control section 7 using a matching start signal and a matching stop signal. Sub-control unit 7
supplies the input cover pattern readout signal to the input cover pattern memory 3, reads the feature amount data of the audio signal for each section from the input cover pattern memory 3, and performs each pattern matching circuit 2-
1 (i=1°2,...) sequentially. This operation of sequentially writing the same input pattern to each pattern matching circuit 2-i is generally performed by a microprocessor (hereinafter referred to as CP).
Sequential write control is performed by a sub-control unit 7 including a sub-control unit 7 (referred to as U). That is, pattern matching involves the operation of first writing an input cover pattern to the input data memory in the pattern matching circuit 2-1, and then writing this same input cover pattern to the input data memory in the pattern matching circuit 2-2. The process was repeated as many times as there were circuits 2-i.

FIG. 3 is a connection diagram of a plurality of pattern matching circuits and a CPU, in which 101 to 106 are pattern matching circuits #1 to #6, 107 is a pass line, and 108 is a CPU. In the figure, each pattern matching circuit 101 to
106 is connected in parallel to the CPU 8 via a pass line 107.

FIG. 4 is a timing chart showing sequential writing to a conventional pattern matching circuit. In the same figure, T
W, (1-1, 2, . . . 6) is the input pattern writing time, and T M 1 (t-1, 2, . . . 6) is the pattern matching processing time. The CPU 8 writes the input pattern to the #1 pattern matching circuit 101 at the timing TW1, and immediately writes the same pattern to the #2 pattern matching circuit 102 at the next timing TW2. The #1 pattern matching circuit 101 performs pattern matching processing on TM1 at a timing parallel to the timing of T W 2. In this way, the CPU 10g sequentially performs six write operations to write the input pattern of one voice section to all the pattern matching circuits 101-10B. Therefore, the time required to write to the six pattern matching circuits is 6 x TW1.
becomes.

FIG. 5 is a diagram showing an address map of a conventional input data memory. In the figure, for example, the input data memory in pattern matching circuit #1 has an address area from the first address OO to the last address 7F, and each input data memory in pattern matching circuits 101 to 106 has a different address area. are doing. By assigning a different address area to each input data memory in this way, the CPU 108 allows each pattern matching circuit 10
It is possible to sequentially write input bartan data to 1 to 106.

In FIG. 2, each pattern matching circuit 2-i
(1-1, 2, . . . ) is the dictionary pattern memory unit 1- that corresponds to the pattern data most similar to the input pattern data (feature data) written sequentially as described above.
1 (i=1, 2,...), calculates the distance data between the two, and controls this distance data and the matching end signal E1 (t-1, 2,...) together. Send it to Department 5. The control unit 5 includes each pattern matching circuit 2
-1 to 2-1, each time the matching end signal E1 is input, interrupt processing is performed and the corresponding pattern matching circuit 2-
The distance data is taken from i and stored in the built-in memory. The distance data is taken in by this interrupt processing for each pattern matching circuit 2-i, and when all the distance data have been taken in, the one with the smallest value among these distance data is selected and the one with the smallest value is selected. Recognize category names as audio patterns. The control section 5 performs the above-mentioned recognition process on the data for each voice section, and displays the category name of the recognition result on the display section 6.

[Problems to be Solved by the Invention] However, in the pattern matching control circuit as described above, since the input pattern data for each voice section is sequentially written to a plurality of pattern matching circuits, the pattern matching It was necessary to repeat the write operation as many times as there were circuits. Therefore, when the number of pattern matching circuits increases, the time required for writing increases in proportion to this number, resulting in a problem in that the processing speed of the speech recognition apparatus as a whole decreases.

The present invention has been made to solve this problem, and can shorten the time required to write input pattern data to the plurality of pattern matching circuits, and improve the processing speed of the speech recognition device as a whole. The purpose is to obtain a pattern matching control circuit.

[Means for Solving the Problems] A pattern matching control circuit according to the present invention matches a speech pattern for each speech section of speech input to a speech recognition device with a dictionary pattern preliminarily stored in the device. In a circuit that controls a plurality of pattern matching means that perform pattern matching processing in parallel, a common address area is given to the input data storage section built into each of the plurality of pattern matching means, and the input audio The apparatus further includes write control means for simultaneously writing input pattern data for each voice section into each of the plurality of input data storage sections having the common address area.

[Operation] In the present invention, a plurality of pattern matching processes are performed in parallel between a speech pattern for each speech section of speech input to a speech recognition device and a dictionary pattern stored in advance in the speech recognition device. In the circuit for controlling the matching means, the write control means assigns a common address area to the input data storage units incorporated in each of the plurality of pattern matching means, and writes the input pattern for each voice section of the input voice. Data is simultaneously written to each of the plurality of input data storage units having the common address area.

[Embodiment 1] FIG. 1 is a block diagram showing the configuration of a plurality of input data memories according to the present invention. In the figure, 201 to 206 are data memories for #1 to #6 people, respectively.
This is a memory built into the 6-pattern matching circuit.

FIG. 6 is a timing chart showing parallel writing to the input data memory according to the present invention. In the same figure, T W
, (1-1, 2,...6) is the writing time of input data to the input data memory, and "rWl-TW
-...-TW. TM, (1-
1°2, . . . 6) is the pattern matching processing time.

FIG. 7 is a diagram showing an address map of the input data memory according to the present invention. In the same figure, #1 to #6 person data memories 201 to 206 in each pattern matching circuit.
are all assigned a common address area, that is, from the first address OO to the last address 7F.

The operation of FIG. 1 will be explained with reference to FIGS. 6 and 7.

As shown in the address map shown in FIG. 7, #1 to #6 person data memory 201 in each pattern matching circuit.
~206 are given a common address area, so
As shown in Figure 1, the address signal terminal, data input terminal, write signal terminal, and chip select signal terminal of each input data memory are connected in parallel, and the address signal, input data, and write signal terminal common to each input data memory are connected in parallel. signal and chip select signal. Therefore, as shown in the timing chart of FIG.
U tag is #1 to #6 person data memory 201-2
Same data writing time to 0B TW1-TW -...
- Input pattern data can be written in parallel using the TV6. In addition, each pattern matching circuit 101
If the pattern matching processing times performed by the circuits 101 to 106 are the same, then all the pattern matching circuits 101 to 1
The time from writing the input data to 06 to the end of the pattern matching process is TV + TM. On the other hand, the time from the writing of input data to all pattern matching circuits 101 to 106 to the end of pattern matching processing in the timing chart of FIG. 4 is as follows.

TW +TW ...+TW6+TM6-6xTW
1+TM6 Therefore, in the present invention, the time required for operation of the conventional pattern matching circuit is reduced by 5XTW1.

Furthermore, during the operating time period of each pattern matching circuit (that is, the time period during which input pattern data is written and pattern matching processing is performed), the A/D converter 10 shown in FIG.
, the preprocessing unit 11, the extraction unit 12, and the feature amount calculation unit 13 perform respective processing on the input cover turn of the next voice section of the input voice, and store the calculated feature amount data in the human cover turn memory 3. Operations can be performed in parallel.

Therefore, reducing the operating time of the pattern matching circuit reduces the processing time of the audio storage device as a whole and contributes to improving its processing speed.

[Effects of the Invention] As described above, according to the present invention, the pattern matching process of the speech pattern for each speech section of the speech input to the speech recognition device and the dictionary pattern stored in advance in the speech recognition device is performed in parallel. In a circuit for controlling a plurality of pattern matching means that performs automatic matching, a common address area is assigned to an input data storage section built into each of the plurality of pattern matching means, and a common address area is assigned to each voice section of the input voice. Since each input pattern data is simultaneously written to each of the plurality of input data storage units having the common address area, the time required to write the input pattern data to the plurality of pattern matching means is significantly reduced compared to the conventional method. shorten,
The effect of improving the processing speed of the speech recognition device as a whole can also be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a plurality of input data memories according to the present invention, FIG. 2 is a block diagram showing the configuration of a conventional speech recognition device, and FIG. 3 is a block diagram showing the configuration of a plurality of pattern matching circuits and a CPU. Connection diagram, FIG. 4 is a timing chart showing sequential writing to a conventional pattern matching circuit, FIG. 5 is a diagram showing an address map of a conventional input data memory, and FIG. 6 is a diagram showing an input data memory according to the present invention. FIG. 7 is a timing chart showing the parallel writing of the data, and FIG. 7 is a diagram showing the address map of the input data memory according to the present invention. In the figure, 1-1, 1-2, . . . are dictionary pattern memory sections, 2-1, 2-2, . . . are pattern matching circuits, 3 is an input pattern memory, 5 is a control section,
6 is a display section, 7 is a sub-control section, 8 is an address counter, 9
10 is a microphone, 10 is an A/D converter, 11 is a preprocessing unit, 12 is a cutting unit, 13 is a feature calculation unit, 101 to 10
B is #1 to #6 pattern matching circuit, 107 is a pass line, and is a CPU. ~20B is a data memory for #1 to #6 people.

Claims (1)

[Scope of Claims] Controls a plurality of pattern matching means that performs pattern matching processing in parallel between a speech pattern for each speech section of speech input to a speech recognition device and a dictionary pattern stored in advance in the device. In the circuit, each of the plurality of pattern matching means assigns a common address area to a built-in input data storage unit, and input pattern data for each voice section of the input voice is stored in the plurality of pattern matching units having the common address area. A pattern matching control circuit comprising write control means for simultaneously writing to each input data storage section.