JPH04150639A - Digital modulator - Google Patents

Abstract

PURPOSE:To set an offset frequency freely with respect to a data clock frequency similarly to the case with adoption of a multiplier by implementing the frequency offset through addition processing. CONSTITUTION:An instantaneous phase angle data outputted from a phase detection circuit 24 is fetched in a differentiating circuit 25, in which the data is differentiated and from which an instantaneous frequency data is outputted. An adder 26 receives an offset frequency data and an instantaneous frequency data outputted from an offset frequency setting circuit 27 and outputs the result of sum to an integration circuit 28. The integration circuit 28 integration the sum of addition to output the instantaneous phase angle data subject to frequency offset. Since the frequency offset is implemented through the addition processing in this way, the offset frequency (channel interval) is set freely with respect to the data clock frequency without use of a multiplier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital modulator used in digital wireless communications. In particular, it relates to digital modulators using quadrature modulators.

[Conventional technology]

In mobile communications, a transmitter that performs common amplification at a base station or a modulator that performs multicarrier transmission needs to simultaneously generate signals for multiple channels as shown in FIG. In FIG. 5, f.

~f, is the center frequency corresponding to each channel, and the dashed line f
, , fs indicates a free channel.

Incidentally, a digital phase modulated wave can be generated by inputting the I channel and Q channel baseband signals to a quadrature modulator, but if a frequency offset is applied to the Hespant signal, Channel and Q channel baseband signals 5t(t), 5o(
t) are respectively S + (t) = Acos(φ, +
Δωt) ・”(1) SQ(t)=Asin
(φi+Δωt)...(2), and furthermore, S + (t) = A (cosφ1cO3Δωt−
5inφHsinΔωt)...(3) So(t)=A(sinφ1cO3Δω is 10CO3φ,
sinΔωt) (4) It can be transformed as follows. Therefore, in digital phase modulation, frequency offset is possible by multiplying the base hand signal signal by an offset signal. That is, as shown in FIG. 6, by performing frequency offset in the baseband, it is possible to generate signals of multiple channels as shown in FIG. 5.

Conventionally, there have been two methods for obtaining this multiplication result: (1) directly performing multiplication using a multiplier; and (2) writing the multiplication result in a ROM and reading it from there. Hereinafter, with reference to FIGS. 7 and 8, configurations for generating QPSK signals of multiple channels will be described in accordance with each method.

FIG. 7 is a block diagram showing the configuration of a conventional baseband channel-independent QPSK modulator that uses a multiplier to offset the frequency.

In the figure, the baseband signals of the ■ channel and the Q channel are transmitted through shift registers 70, . The signal is input to a ROM filter (LPF) 711.71° via a 70° angle and band-limited. Each ROM filter is provided with a sampling bit from counter 72.

On the other hand, the frequency synthesizer 7 is connected to the multipliers 73□ and 73°.
Offset frequency data is input from 4 through an analog/digital converter (A/D) 75, and is multiplied by data of each band-limited channel, thereby specifying each channel in the baseband. The signals designated for each channel are added by an adder 761.76° for each channel and Q channel, and are added by a digital/analog converter (D/A) 771.77° and a low-pass filter (
LPF) 7B+, via TEL, quadrature modulator 7
9, and a composite modulated signal of multiple channels can be obtained.

Figure 8 shows the frequency-offset signal data as RO
FIG. 2 is a block diagram showing the configuration of a conventional spanned channel designation type QPSK modulator using a method of reading from M.

In the figure, in order to realize equations (3) and (4), each term of each equation (cosφi CO3Δωt),
(sinφ.

sinΔωt), (sinφ1cesΔωt), (co
The multiplication result of sφ4sinΔωt) is written in the ROM filter.

That is, the I channel data and Q channel data of channel 1 are transferred to shift registers 81, . ROM filters 82 . 81 . ．． 82□ and address input for ROM filters 823 and 824. Counter 83 takes in a sampling clock and supplies sampling bits to each ROM filter 821-824.

Adder 84. Now, ROM filter 82. By adding the output data of 82 degrees, a frequency-offset I channel data cos (Δω1 is 10φ) is obtained, and the adder 84. By adding the output data of the ROM filter 82□82, a frequency-offset Q channel inverter 5 inches (Δω, 10φ,) is obtained.

Note that the ROM filter 82 and the adder 84 constitute a frequency offset section 85.

The I channel data and Q channel data offset in frequency corresponding to each channel are sent to an adder 86+, respectively.
, 86Q, and the digital/analog converter (
D/A)87. ．． 87°, low pass filter (LPF)
8B, ,8B. The signal is input to the orthogonal modulator 89 via the channel 89, and a composite modulated signal of multiple channels is obtained.

[Problems to be Solved by the Invention] By the way, when generating a signal with an arbitrary frequency offset from a baseband signal, the method of using a multiplier for multiplying the offset frequency as shown in the configuration shown in FIG. , the circuit size becomes larger and the power consumption also becomes larger. Furthermore, a highly accurate oscillator (frequency synthesizer) is required for each channel, and as the number of channels increases, the circuit scale increases.

Furthermore, in the method of writing the multiplication results in the ROM, as shown in the configuration shown in FIG. 8, addressing is performed for the ROM filter using input data and sampling bits, but the In order to maintain the transmission data rate (data clock frequency) f, the offset frequency was limited to an integral multiple of the transmission data rate (data clock frequency) f.

That is, there is a relationship between the offset frequency Δf and the data clock frequency f as Δfc=m−fb (m is a natural number), and there are restrictions on the frequency that can be offset according to the data transmission rate, that is, the channel spacing. there were.

The present invention does not use a multiplier and the offset frequency Δf
It is an object of the present invention to provide a digital modulator that can relax the integral multiple relationship between , and data clock frequency f, and can freely set the offset frequency (channel spacing).

[Means for Solving the Problems] The present invention provides a plurality of baseband digital signal processing circuits that output channel data and Q channel data whose band is limited by a ROM filter and whose frequency is offset corresponding to a plurality of channels; In the digital modulator, the baseband digital signal processing circuit includes a quadrature modulator that digitally adds and acquires the E-channel data and the Q-channel data for each channel, and performs phase modulation. ■Amplitude and phase detection means for detecting the instantaneous amplitude of each of the channel signal and Q channel signal and the instantaneous phase angle of the composite vector of each signal, a differentiating means for obtaining instantaneous frequency data from the instantaneous phase angle data, and the instantaneous frequency an adding means for adding the data and the offset frequency data to obtain offset instantaneous frequency data; an integrating means for obtaining the phase locus from the offset instantaneous frequency data; and the frequency-offset phase locus and the instantaneous amplitude. Based on the data, a signal point locus corresponding to each channel is generated, and signal generation means is configured to output channel data and Q channel data.

(Operation) FIG. 1 is a block diagram showing the basic configuration of the digital modulator of the present invention.

In the figure, ■ channel data and Q channel data are stored in the ROM of the baseband digital signal processing circuit 10.
Bandwidth is limited by filters 111 and 11°, respectively. The instantaneous amplitude and instantaneous phase angle of the band-limited I channel data and Q channel data are obtained by the amplitude and phase detection means 12, and the instantaneous phase angle is obtained by the differentiating means 13.
Instantaneous frequency data can be obtained by differentiating with . Furthermore, the adding means 14 adds offset frequency data to this instantaneous frequency data to perform frequency offset.

That is, in the baseband digital signal processing circuit 10, signals with different center frequencies are generated by frequency offsetting in the baseband, but when performing frequency offset on the baseband signal, if the input signal is frequency information, , any frequency offset is possible by adding offset frequency data.

By integrating this addition result by the integrating means 15, a frequency-offset instantaneous phase angle is obtained. The signal generating means 16 generates frequency-offset l-channel data and Q-channel data from this instantaneous phase angle and instantaneous amplitude.

That is, in digital phase modulation, a discrete phase trajectory is obtained according to the input data, but when input data is band-limited, a continuous phase trajectory is obtained. Therefore, the instantaneous frequency obtained by time-differentiating the phase locus also becomes a finite and continuous value, and by adding offset frequency data to this and time-integrating it again, the phase locus of the frequency-offset signal is obtained. By changing the value of the offset frequency data, a signal with a different arbitrary center frequency can be generated without using a multiplier, and an arbitrary channel can be accessed in the baseband.

Note that the l channel data and Q channel data designated for each channel are converted into radio frequency signals by a quadrature modulator.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

Note that although this embodiment has a configuration compatible with the QPSK modulation method, the same configuration can also be applied to other modulation methods on the π/4 shift QPSK modulation.

In the figure, input data for each channel is input to a baseband digital signal processing circuit 20 for each channel (1) and Q channel.

In the baseband digital signal processing circuit 20, the input signals are R
OM filter (LPF) 22. ．． 22° and the band is limited. Each ROM filter is given a sampling focus from a counter 30 to which a sampling clock is input. Note that by rewriting data in the ROM filter, various band restrictions can be easily implemented.

The band-limited l-channel data and Q-channel data are input to an amplitude detection circuit 23 and a phase detection circuit 24, respectively, each comprised of a ROM, and instantaneous amplitude and instantaneous phase angle are obtained. The instantaneous phase angle data output from the phase detection circuit 24 is taken into the differentiation circuit 25 and differentiated, and instantaneous frequency data is output. The adder 26 takes in the offset frequency data and instantaneous frequency data output from the offset frequency setting circuit 27 and outputs the addition result to the integrating circuit 28. In the integrating circuit 28,
By integrating this addition result, frequency-offset instantaneous phase angle data is output.

Signal generation circuit composed of ROM (ROMsin, RO
McO3) 294.292 takes in the instantaneous amplitude data output from the amplitude detection circuit 23 and the frequency-offset instantaneous phase angle data output from the integration circuit 28, and outputs the frequency-offset l channel data and Q
Generate and output channel data.

The above is the configuration of the baseband digital signal processing circuit 20, and each channel is specified in the baseband.

Signals designated for each channel are digitally added by an adder 310.31° for each channel (1) and Q channel.

The 1-channel data and the Q-channel data of the plurality of channels added by the adder 311. LF
'F) 3''31.33. High frequency components are removed, and the RF signal is input to the quadrature modulator 34 and multiple channels are combined.
This configuration allows a band modulated signal to be obtained. Note that the quadrature modulator 3
4 is mixer 35. ．． It is composed of a 35° and 90° phase shifter 36, a carrier wave oscillator 37, and an analog adder 38.

The operation of one series (channel) will be explained below.

FIG. 3 shows the relationship between the instantaneous amplitude and the instantaneous phase angle of L channel data and Q channel data, and FIG. 4 shows the output waveforms of each part.

In FIG. 4, (a) is each input data of the I channel and Q channel, (b) is the output waveform of the ROM filter 22, (C) is the output waveform of the phase detection circuit 24, and (d) is the output waveform of the differentiating circuit 25. The output waveforms, (e) are the output waveforms of the adder 26, and (f) are the output waveforms of the integrating circuit 28, which show the phase trajectory after frequency offset.

The input data (a) of the (2) channel and the Q channel is normal NRZ format binary data. On the other hand, since the ROM filter 22 operates digitally, its output waveform (
b) lacks smoothness. The output waveform (C) of the phase detection circuit 24 is an instantaneous phase angle θ6 obtained from the band-limited I channel take S1 and Q channel data SQ, that is, θa=jan-'(SQ/S+)'
-(5) is shown. The differentiating circuit 25 differentiates this with time to obtain the instantaneous frequency f4, that is, fa=
aθ,/dt (6) is obtained, resulting in the output waveform (d).

When offset frequency data Δω is added to this, the frequency after frequency offset is f, +Δω...(7)
This becomes the output waveform (e) of the adder 26.

The integrating circuit 28 integrates this over time to obtain the phase locus φ after frequency offset, that is, the output waveform.

From this phase locus, the signal generation circuit 291.29° generates frequency-offset l channel data and Q
Channel data is obtained. Therefore, if the offset frequency is shifted for each series (channel) by changing the offset frequency data, the output data of each series can be added for each channel and Q channel and multiplexed into one series. can.

Here, the minimum frequency that can be offset will be explained. The quantization bit of the offset frequency is P, and the sampling bit is 82. The transmission data rate is f.

Then, the minimum frequency that can be offset Δf si,.

is Δf, ゎ=fb/2'-3...(9). For example, if P is 10 bits, S is 5 bits, and f is 16 kbps, Δf mir+ is Q, 5 kHz.
becomes.

Note that this is a value that poses no problem in practice.

[Effects of the Invention] As described above, the present invention uses a highly stable and highly accurate clock to apply a frequency offset in a baseband digital signal processing circuit to generate signals with different center frequencies. Any channel specification can be made without depending on precision.

Furthermore, since the frequency offset is performed by the addition process, the offset frequency (channel interval) can be freely set with respect to the data clocker frequency, as in the case of using a multiplier.

In addition, since the configuration does not perform multiplication processing on frequency offsets, multipliers and oscillators (frequency synthesizers) are not required, making it possible to significantly reduce circuit size and power consumption as the number of channels increases. It is possible to downsize equipment and reduce power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the digital modulator of the present invention. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 3 is a diagram showing the relationship between instantaneous amplitude and instantaneous phase angle of L channel data and Q channel data. FIG. 4 is a diagram showing output waveforms of each part. FIG. 5 is a diagram showing spectra of multiple channels in the RF band. FIG. 6 is a diagram showing spectra of multiple channels frequency offset in baseband. FIG. 7 is a block diagram showing the configuration of a conventional baseband channel specification type QPSK modulator that uses a multiplier to offset the frequency. Figure 8 shows the frequency-offcented signal data stored in the ROM.
1 is a block diagram showing the configuration of a conventional baseband channel specification type QPSK modulator using a method of reading from a baseband channel; FIG. lO...Baseband digital signal processing circuit, 11
ROM filter, 12... Amplitude and phase detection means, 13... Differentiating means, 14... Adding means, 15
... Integrating means, 16... Signal generating means, 20...
Baseband digital signal processing circuit, 21...shift register, 22...ROM filter, 23...amplitude detection circuit, 24...phase detection circuit, 25...differentiation circuit, 26...addition circuit , 27... Offset frequency setting circuit, 28... Integrating circuit, 29... Signal generation circuit, 30... Counter, 31... Adder, 32...
・・Digital/analog converter (D/A), 33・
...Low pass filter (LPF), 34... Quadrature modulator. Diagram

Claims (1)

[Claims] (1) A plurality of baseband digital signal processing circuits that output I channel data and Q channel data whose band is limited by a ROM filter and whose frequency is offset corresponding to multiple channels; In a digital modulator including a quadrature modulator that digitally adds and captures each channel and performs phase modulation, the baseband digital signal processing circuit adds each of the band-limited I channel signal and Q channel signal. amplitude and phase detection means for detecting the instantaneous amplitude and instantaneous phase angle of a composite vector of each signal; differentiating means for determining instantaneous frequency data from the instantaneous phase angle data; and adding the instantaneous frequency data and offset frequency data; an adding means for obtaining offset instantaneous frequency data; an integrating means for obtaining a phase trajectory from the offset instantaneous frequency data; and a signal point trajectory corresponding to each channel from the frequency offset phase trajectory and the instantaneous amplitude data. and I
A digital modulator comprising signal generating means for outputting channel data and Q channel data.