JPH02211746A - Digital psk demodulating circuit - Google Patents

Abstract

PURPOSE:To simplify the loop adjustment and to miniaturize a circuit by using a digital circuit to constitute the loop of the principal part of a PSK demodulating circuit. CONSTITUTION:This circuit is provided with a low pass filter LPF 1, an A/D converter 2, a digital multiplier 3, an I digital multiplier/adder 4, a Q digital multiplier/adder 5, a scaler 6, a D/A converter 7, a third digital multiplier/adder 8 for costas, a DSP(digital single processor) 9, a cosine wave generating part 10, a sine wave generating part 11, an NCO(numerical control oscillator) 12 for bit rate, an NCO 13 for subcarrier, a frequency synthesizer 14, and a scaler control part 15. Consequently, the principal part of the PSK demodulating circuit consists of the digital circuit in this constitution. Thus, the loop adjustment is facilitated and the circuit is miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital demodulation circuit for demodulating a digital signal subjected to PSK modulation tM (phase modulation), and particularly relates to a two-phase PSK demodulation circuit.

[Conventional technology]

Conventionally, as this type of circuit, there is a demodulation circuit using a Costas loop. An example is shown in Figure 2.

In the figure, 21 is an I (in-phase) multiplier;
22 is a low-pass filter, 23 is a voltage controlled oscillator (■C
o), 24 is a loop filter, 25 is a third multiplier, 26
is a 90° phase shifter, 27 is a Q (quadraturep
hase) multiplier, 28 is a low pass filter.

The baseband modulated carrier wave is multiplied by the output clock signal (0°, 90'') of the VCO 23 in the 1 multiplier 21 and the 9 multiplier 27, respectively, and then passed through the low-pass filter 2.
2.28 and are output to the third multiplier 25, respectively. After being multiplied here, the signals are passed through a loop filter 24 and inputted to the VCO 23, the oscillation frequency is controlled, and clock signals are again output to the I multiplier 21 and the 9 multiplier 27, respectively.

The PSK demodulated output is taken from the output of the low pass filter 2.

[Problem to be solved by the invention]

The conventional Costas loop demodulator described above is constructed of analog circuits, and therefore requires a lot of time for adjustment and testing. Also resistors and capacitors.

Since there are many discrete components such as coils, there is a problem in that it is difficult to miniaturize the circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital PSK demodulation circuit that allows easy loop adjustment and miniaturization.

[Means to solve the problem]

The digital PSK demodulation circuit of the present invention includes an A/D converter that converts an input signal into a digital signal, a frequency synthesizer for generating a clock for sampling the A/D conversion, and a level adjustment of the converted digital signal. an I digital multiplier/adder and a Q digital multiplier/adder that multiply and add the level-adjusted digital signal with sine wave information/cosine wave information, respectively, and a third digital multiplier/adder that adds these outputs. a digital signal processor that takes in the output of this third digital multiplier/adder and processes it in a loop filter, and each numerically controlled oscillator for subcarrier/bit rate driven based on the output of this digital signal processor. , a sine wave generator/cosine wave generator that outputs the sine wave information/cosine wave information using these oscillators.

[Effect]

In the above configuration, the main loop of PSK demodulation is configured as a digital circuit, and the loop can be adjusted using a digital signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of the present invention. In the figure, 1 is a low-pass filter, 2 is an A/D converter, 3 is a digital multiplier, 4 is a digital multiplier/adder, 5 is a Q digital multiplier/adder, 6 is a scaler, and 7 is a D/A converter. 8 is a third digital multiplier/adder for Costas, 9 is a DSP (digital signal processor), 10 is a cosine wave generator, 11
12 is a bit rate NGO (numerically controlled oscillator), 13 is a subcarrier NGO 114 is a frequency synthesizer, and 15 is a scaler control unit.

The two-phase PSK modulated signal passes through a low-pass filter 1 to improve its S/N ratio, and then is converted into digital data by an A/D converter 2. The converted digital data is multiplied by the level information detected from the outputs of the I digital multiplier/adder 4 and the Q digital multiplier/adder 5 through the scaler control section 15 in the digital multiplier 3, thereby adjusting the level. This level-adjusted data is I
The digital multiplier-adder 4 and the Q-digital multiplier-adder 5 multiply the sine wave information and cosine wave information output from the sine wave generator 11 and the cosine wave generator 10, respectively, and then add them and output them. do.

■One of the outputs of the digital multiplier/adder 4 passes through the scaler 6 and is input to the third multiplier/adder 8 for Costas, and the other output is the D/
It passes through the A converter 7 and becomes a PSK demodulated output. Further, the output of the Q digital multiplier/adder 5 is directly input to the third multiplier/adder 8 for Costas. Note that the scaler 6 is used to prevent overflow of this adder when the third multiplier-adder 8 for Costas performs addition to a degree slow enough to be taken in by the DSP 9.

Then, the output of the third multiplier-adder 8 for Costas is taken into the DSP 9, and after D and SP 9 perform loop filter processing, control data is sent to the bit rate NCO 12 and subcarrier NC 013 as frequency deviation data. Set. The data of these NCOs 12 and 13, together with the frequency control data from the DSP 9, are output to a cosine wave generator 10° and a sine wave generator 11, and are then output to a digital multiplier/adder 4. It is output again to the Q digital multiplier/adder 5.

The frequency synthesizer 14 receives the subcarrier frequency information from the DSP 9 and uses the sampling clock of the A/D converter 2, the bit rate NCO 12, and the subcarrier N
They are respectively output to CO13.

Therefore, in this configuration, the main part of the PSK demodulation circuit is configured with a digital circuit, and the loop adjustment can be simplified compared to a conventional circuit configured with an analog circuit. Also resistors and capacitors.

By reducing the number of discrete components such as coils, it is possible to miniaturize the circuit.

〔Effect of the invention〕

As described above, in the present invention, since the main loop of the conventional analog PSK demodulation circuit is configured with a digital circuit, adjustment of the complicated loop can be simplified and the present invention can be used for general purposes. Furthermore, by changing from an analog circuit to a digital circuit, there is an effect that miniaturization can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the digital PSK demodulation circuit of the present invention, and FIG. 2 is a block diagram of a general Costas loop. l...Low pass filter, 2...A/D converter, 3
... digital multiplier, 4... digital multiplier/adder, 5... Q digital multiplier/adder, 6... scaler,
7...D/A converter,...Third digital multiplier/adder for Costas loop, 9...DSP, 10...Cosine wave generator, 11...Sine wave generator, 12...・NC0,13 for bit rate...NC0,14 for subcarrier
... Frequency synthesizer, 15... Scaler control unit, 21... 1 multiplier, 22... Low pass filter, 23... ■C0124... Loop filter, 25... Third multiplication device, 26...90° phase shifter, 2
7...9 multipliers, 28...low pass filters.

Claims (1)

[Claims] 1. An A/D converter that converts an input signal into a digital signal, a frequency synthesizer for generating a clock for sampling this A/D conversion, and a digital multiplier that adjusts the level of the converted digital signal. an I digital multiplier/adder and a Q digital multiplier/adder that multiply and add the level-adjusted digital signal by sine wave information/cosine wave information, respectively; a third digital multiplier/adder that adds the outputs of these; A digital signal processor that takes in the output of the multiplier-adder and processes it in a loop filter, numerically controlled oscillators for subcarriers/bit rates that are driven based on the output of this digital signal processor, and these oscillators generate the sine wave. A digital PSK demodulation circuit comprising a sine wave generation section/cosine wave generation section that outputs information/cosine wave information.