JPH04145713A - High frequency power amplifier - Google Patents

High frequency power amplifier

Info

Publication number
JPH04145713A
JPH04145713A JP2269953A JP26995390A JPH04145713A JP H04145713 A JPH04145713 A JP H04145713A JP 2269953 A JP2269953 A JP 2269953A JP 26995390 A JP26995390 A JP 26995390A JP H04145713 A JPH04145713 A JP H04145713A
Authority
JP
Japan
Prior art keywords
high frequency
fets
power
field effect
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2269953A
Other languages
Japanese (ja)
Other versions
JP3102023B2 (en
Inventor
Tsutomu Noguchi
野口 務
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP02269953A priority Critical patent/JP3102023B2/en
Publication of JPH04145713A publication Critical patent/JPH04145713A/en
Application granted granted Critical
Publication of JP3102023B2 publication Critical patent/JP3102023B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To increase the output synthesis efficiency at a high frequency even when an FET is subject to the effect of a high frequency component and a divided frequency component by setting the ground condition of plural FETs connected in cascade identically over a wide frequency. CONSTITUTION:A gate width of FETs Q1, Q2 and a gate width of a current source FETQ3 are set to 1mm respectively and a gate voltage VG3 of the FETQ3 is set to 0V. Thus, the FETs Q1, Q2 are operated by a current a half of the saturation current IDSS. Furthermore, the capacitance of high frequency short-circuit capacitors C1, C2 is set identical to set the ground condition of the FETs Q1, Q2 over a wide frequency range. Thus, even when the FETs Q1, Q2 are in operation with a high output and affected by higher harmonic and divided frequency components due to the nonlinear component, they are operated in the same operating condition and the combination efficiency of high frequency power is enhanced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高周波電力増幅器に関し、特にフィルドエフ
ェクトトランジスタCFET)を用いた高出力の高周波
電力増幅器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high frequency power amplifier, and more particularly to a high output high frequency power amplifier using a field effect transistor (CFET).

〔従来の技術〕[Conventional technology]

従来の高周波高出力増幅器、特に縦続接続にして高い電
源電圧で動作させ、動作電流を減少させるように工夫し
た増幅器の一例を第3図に示す。
FIG. 3 shows an example of a conventional high-frequency, high-output amplifier, particularly an amplifier designed to be connected in cascade, operated at a high power supply voltage, and to reduce operating current.

第3図において、従来1の高周波電力増幅器、すなわち
、増幅回路1は、入力結合キャパシタと入力整合回路を
含む入力回路11.12と、出力整合回路と出力結合キ
ャパシタを含む出力回路13゜14と、FETQl、Q
2と、高周波短絡用のキャパシタC1lと、高周波チョ
ークコイルL1、L2とに構成されている。
In FIG. 3, a conventional high-frequency power amplifier, that is, an amplifier circuit 1, has input circuits 11 and 12 including an input coupling capacitor and an input matching circuit, and output circuits 13 and 14 including an output matching circuit and an output coupling capacitor. , FETQl,Q
2, a high frequency short circuit capacitor C1l, and high frequency choke coils L1 and L2.

FETQl、Q2を電源vI、l)ニ対し直列に接続し
、同じ電流IDDで動作させることにより、単体FET
の耐圧より高い電源電圧■DDで動作させることを可能
にした増幅器である。
By connecting FETQl and Q2 in series to the power supplies vI and l) and operating them with the same current IDD, a single FET
This is an amplifier that can be operated at a power supply voltage DD higher than the withstand voltage of DD.

一般に、FETの耐圧は大きくても20V程度であり、
その直流動作電圧は耐圧の十程度に抑えて使用される。
Generally, the breakdown voltage of FET is about 20V at most.
Its DC operating voltage is kept to about 10,000 volts, which is the withstand voltage.

したがって、FETの動作電圧は10v以下に設定され
るのが普通である。
Therefore, the operating voltage of the FET is usually set to 10V or less.

しかし、この種のマイクロ波電力増幅器を用いる送信装
置は通常、15Vから26Vと高い電源電圧の電源を持
っており、この電圧を降圧してFETに供給している。
However, a transmitter using this type of microwave power amplifier usually has a power supply with a high power supply voltage of 15V to 26V, and this voltage is stepped down and supplied to the FET.

このため降圧時に電力を消費し装置全体としての電力効
率を低下させている。
For this reason, power is consumed during step-down, reducing the power efficiency of the entire device.

したがって、高い電源電圧で増幅器を動作させることが
できれば、送信装置全体の電力効率を向上させることが
出来る場合がしばしば有る。
Therefore, if the amplifier can be operated with a high power supply voltage, it is often possible to improve the power efficiency of the entire transmitter.

このために考案された回路が第3図に示す従来例の増幅
回路である。各々のFETQI、Q2に対し、入力回路
11.12および出力回路13゜14を設け、電源v、
Dに対するチョークコイルL1、L2と高周波短絡用の
キャパシタC1を接続し、入力回路11.12および出
力回路13゜14を各々合成することにより2倍の出力
を得ることができる。しかも動作電流IDDはFETの
1個分の電流で動作出来るという利点がある。
A circuit devised for this purpose is a conventional amplifier circuit shown in FIG. An input circuit 11.12 and an output circuit 13.14 are provided for each FETQI, Q2, and a power supply v,
By connecting the choke coils L1 and L2 to D and the capacitor C1 for high frequency shorting, and composing the input circuits 11, 12 and output circuits 13 and 14, it is possible to obtain twice the output. Moreover, there is an advantage that the operating current IDD can be operated with a current equivalent to one FET.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来の高周波電力増幅器では、高周波短絡用のキャ
パシタを用いて、直流的に高電位側のFETを接地して
いるが、このキャパシタの値を無限大、すなわち、イン
ピーダンスを零にすることはできないため、光全な接地
を取ることは不可能であるという欠点があった。
In this conventional high-frequency power amplifier, a capacitor for high-frequency shorting is used to ground the FET on the high potential side in terms of direct current, but the value of this capacitor cannot be made infinite, that is, the impedance cannot be made zero. Therefore, there was a drawback that it was impossible to obtain a perfect optical grounding.

このため、直流的に高電位側のFETと低電位側のFE
Tの接地条件が異なり、特に、高出力動作時に、両方の
FETの動作が非直線特性による高調波数成分およびそ
の十周波成分の影響を受けることによりアンバランスと
なりRF’電力の合成効率が低下するという問題点があ
った。
For this reason, the FET on the high potential side and the FE on the low potential side in terms of DC
The grounding conditions of T are different, and especially during high output operation, the operation of both FETs is affected by the harmonic number component and its ten frequency components due to nonlinear characteristics, resulting in imbalance and a decrease in the RF' power synthesis efficiency. There was a problem.

すなわち、高周波接地用のキャパシタの実用上選択可能
な値は、周波数IGHzにて、数千PFのオーダであり
、このときのインピーダンスは約1Ωである。一方、F
ETのソース抵抗約1Ωであるので、非直線特性に対す
るキャパシタの影響を無視すると、1dB程度の合成損
失を発生するという問題点があった。
That is, the practically selectable value of the capacitor for high frequency grounding is on the order of several thousand PF at a frequency of IGHz, and the impedance at this time is about 1Ω. On the other hand, F
Since the source resistance of the ET is about 1 Ω, there is a problem in that if the influence of the capacitor on the nonlinear characteristics is ignored, a combined loss of about 1 dB occurs.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の高周波電力増幅器は、電源に対し複数の電力増
幅用フィルドエフェクトトランジスタを縦続接続した高
周波電力増幅器において、直流電位的に高電位にある前
記電力増幅用フィルドエフェクトトランジスタのソース
と接地間に接続した第一のキャパシタと、 直流電位的に低電位にある前記電力増幅用フィルドエフ
ェクトトランジスタのソースと接地間に接続した前記第
一のキャパシタと同一容量の第二のキャパシタと、 前記第二のキャパシタと並列に接続した直流バイアス回
路とを有するものである。
The high frequency power amplifier of the present invention is a high frequency power amplifier in which a plurality of field effect transistors for power amplification are connected in cascade to a power source, and the field effect transistor for power amplification is connected between the source of the field effect transistor for power amplification, which is at a high potential in terms of DC potential, and the ground. a second capacitor having the same capacitance as the first capacitor connected between the source of the power amplifying field effect transistor which is at a low DC potential and the ground; and the second capacitor connected to the ground. and a DC bias circuit connected in parallel.

〔実施例〕〔Example〕

次に、本発明について、図面を参照して説明する。第1
図は本発明の一実施例を示す回路図である。
Next, the present invention will be explained with reference to the drawings. 1st
The figure is a circuit diagram showing one embodiment of the present invention.

第1図において、本実施例の高周波電力増幅器は、従来
のものと同様の増幅回路1に、直流的に低電位側のFE
TQ2のソースを高周波的に接地するキャパシタC2と
、バイアス回路用の電流源FETQ3とを追加した構成
となっている。
In FIG. 1, the high frequency power amplifier of this embodiment has an amplifier circuit 1 similar to the conventional one, and an FE on the low potential side in terms of DC.
It has a configuration in which a capacitor C2 for grounding the source of TQ2 at high frequency and a current source FETQ3 for a bias circuit are added.

ここで、FETQI、Q2のゲート幅をIIIIIll
とし、電流源FETQ3のゲート幅を1mmとし、Q3
のゲート電圧V。3をOvとすることにより、FETQ
I、Q2は飽和電流I DSSの半分の電流で動作させ
ることができる。
Here, the gate width of FETQI and Q2 is
, the gate width of current source FETQ3 is 1mm, and Q3
The gate voltage V. By setting 3 to Ov, FETQ
I and Q2 can be operated with a current that is half the saturation current IDSS.

また、高周波短絡用のキャパシタC1,C2を同一容量
とすることによりFETQI、Q2の接地条件を広い周
波数範囲にわたり同一に設定できる。
Furthermore, by setting the capacitors C1 and C2 for high frequency shorting to have the same capacity, the grounding conditions of the FETs QI and Q2 can be set to be the same over a wide frequency range.

したがって、これ等のFETQI、Q2が高出力動作し
非線形成分による高調波および分周波の周波数成分の影
響を受けた場合でも、同一動作条件で動作させることが
可能となるので、高周波電力の合成効率を上げることが
できる。
Therefore, even if these FETs QI and Q2 operate at high output and are affected by harmonics and frequency components of frequency division due to nonlinear components, they can be operated under the same operating conditions, resulting in high frequency power synthesis efficiency. can be raised.

第2図は本発明の第2の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

第2図において、本実施例と第1図に示す第一の実施例
との相違点は、FETC2のソース側の高周波接地用キ
ャパシタC2を並列接続した、電流源FETQ3の代り
に、抵抗R1と、高周波チョークコイルL3との直列回
路を接続したことである。
In FIG. 2, the difference between this embodiment and the first embodiment shown in FIG. , by connecting a series circuit with the high frequency choke coil L3.

本実施例においても、抵抗R1を約10Ωとし、この電
圧降下を1vとし、VGIを零ボルトに設定することに
より、FETQI、C2の動作電流を約+工。、Sに設
定することができる。
In this embodiment as well, by setting the resistor R1 to about 10Ω, the voltage drop to 1V, and setting VGI to zero volts, the operating current of FETQI and C2 can be reduced to about 10Ω. , S can be set.

また、ソースインピーダンスも、これ等FETに対し等
しく設定出来るため、電力合成効率を上げることが出来
る。
Further, since the source impedance can be set equally for these FETs, power synthesis efficiency can be increased.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、縦続接続した複数のFE
Tの接地条件を広い周波数に亘り等しく設定することに
より、FETが高出力動作の非直線特性により高調波お
よびその分周波成分の影響を受けた場合にも、同一の動
作条件が保たれるため、高周波の出力合成効率を高くす
ることができ、したがって、高周波電力増幅器全体の効
率を高くすることができるという効果がある。
As explained above, the present invention has a plurality of cascade-connected FEs.
By setting the T grounding conditions equally over a wide range of frequencies, the same operating conditions can be maintained even when the FET is affected by harmonics and their subfrequency components due to the nonlinear characteristics of high-output operation. , the high frequency output synthesis efficiency can be increased, and therefore the efficiency of the entire high frequency power amplifier can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2図は本発
明の第二の実施例を示す回路図、第3図は従来の高周波
電力増幅器の一例を示す回路図である。 1・・・・・・増幅回路、11.12・・・・・・入力
回路、13゜14・・・・・・出力回路、C1,、C2
・・・・・・キャパシタ、L1〜L3・・・・・・高周
波チョークコイル、Q1〜Q3・・・・・・フィルドエ
フェクトトランジスタ(FET)。 代理人 弁理士  内 原   晋
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the invention, and FIG. 3 is a circuit diagram showing an example of a conventional high frequency power amplifier. 1...Amplification circuit, 11.12...Input circuit, 13゜14...Output circuit, C1,, C2
... Capacitor, L1 to L3 ... High frequency choke coil, Q1 to Q3 ... Field effect transistor (FET). Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】 1、電源に対し複数の電力増幅用フィルドエフェクトト
ランジスタを縦続接続した高周波電力増幅器において、 直流電位的に高電位にある前記電力増幅用フィルドエフ
ェクトトランジスタのソースと接地間に接続した第一の
キャパシタと、 直流電位的に低電位にある前記電力増幅用フィルドエフ
ェクトトランジスタのソースと接地間に接続した前記第
一のキャパシタと同一容量の第二のキャパシタと、 前記第二のキャパシタと並列に接続した直流バイアス回
路とを有することを特徴とする高周波電力増幅器。 2、前記直流バイアス回路は前記電力増幅用フィルドエ
フェクトトランジスタと同一のゲート幅のゲートを持つ
ソース接地のフィルドエフェクトトランジスタによる電
流源であることを特徴とする請求項1記載の高周波電力
増幅器。
[Claims] 1. In a high frequency power amplifier in which a plurality of field effect transistors for power amplification are connected in cascade to a power source, a connection between the source of the field effect transistor for power amplification, which is at a high potential in terms of DC potential, and ground. a second capacitor having the same capacitance as the first capacitor connected between the source of the power amplifying field effect transistor which is at a low DC potential and the ground; and the second capacitor connected to the ground. and a DC bias circuit connected in parallel. 2. The high frequency power amplifier according to claim 1, wherein the DC bias circuit is a current source formed by a source-grounded field effect transistor having a gate having the same gate width as the power amplifying field effect transistor.
JP02269953A 1990-10-08 1990-10-08 High frequency power amplifier Expired - Fee Related JP3102023B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02269953A JP3102023B2 (en) 1990-10-08 1990-10-08 High frequency power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02269953A JP3102023B2 (en) 1990-10-08 1990-10-08 High frequency power amplifier

Publications (2)

Publication Number Publication Date
JPH04145713A true JPH04145713A (en) 1992-05-19
JP3102023B2 JP3102023B2 (en) 2000-10-23

Family

ID=17479517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02269953A Expired - Fee Related JP3102023B2 (en) 1990-10-08 1990-10-08 High frequency power amplifier

Country Status (1)

Country Link
JP (1) JP3102023B2 (en)

Also Published As

Publication number Publication date
JP3102023B2 (en) 2000-10-23

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