JPH04144460A - Method for folding digital exchange by communication control device - Google Patents

Abstract

PURPOSE:To attain a folding test by selectively outputting the data of a latch means to a corresponding time slot in an outgoing multiplex signal. CONSTITUTION:A command outputted from a digital subscriber's circuit (DLC) interface 11 to an incoming highway is reached to an optical interface 12 and its command information is detected by a folding instruction detecting means 120 for detecting time-slot information. The detection output of the means 120 is supplied to a specified data link latching means 21 and data are extracted from the incoming highway and latched at the timing of the specified data link. When an outgoing highway is set up to a prescribed time slot, a switching means 122 is driven and the latched information is selectively outputted to the outgoing highway. Consequently, a communication control device 13 can obtain a test result by comparing the information returned by its folding with transmitted contents.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a loopback method using a communication control device of a digital exchange connected to a network interface provided between a plurality of subscriber circuits and a switch mechanism.

The purpose of this invention is to provide a method that enables repeat testing by specifying a data link for control information within the optical interface of a network interface.

The communication control device inserts a return instruction including a data link number for control information into a specific time slot in the two multiplexed signals, and the optical interface facing the switch mechanism in the network interface receives the return instruction by the return instruction detection means. Extracts return instruction information of the specific time slot, stores the data of the instructed data link number in the instruction data link launch means, and selectively outputs the data of the launch means to the corresponding time slot in the downlink multiplexed signal. Configure it like this.

[Field of Industrial Application] The present invention relates to a loopback method using a communication control device of a digital exchange connected to a network interface provided between a plurality of subscriber circuits and a switch mechanism.

In recent years, switching equipment compatible with I5DN has been put into practical use, and it is expected that it will become widespread in the future.

Particularly in public networks, digital exchanges compatible with I5DN are desired to have a duplex configuration and to be able to easily perform maintenance tests in order to improve reliability.

[Prior Art] FIG. 7 is a block diagram of a digital switching system that is an object of improvement of the present invention.

In Fig. 7, 1 is a digital telephone (D-TTE L
:Digital Telephone), 2
is a network terminal equipment (NT).
tion [equipment), 3B digital subscriber circuit (DLC: Digital 5ubs)
criber Line C1rcuit), 4 is a network interface (NW IF: Ne
5 is a communication control device (DLCC: DLC-Common),
6 is a local switch (LSW: Local 5w1
tch), 7 is line processor (LPR)
It is.

This switching system is equipped with a switching function compatible with I5DN (Integrated Service Digital Communication Network), and a telephone 1 and a network termination device 2 are installed on the subscriber side, and Dl and IJ are installed on the subscriber side.

C3 and each unit W4 to W7 are provided on the exchange side.

In Fig. 7, between the telephone set 1 and the network termination device 2, there is a B channel (two channels on each side) for information such as 64 Kbps voice and data (not shown by a dotted line), and information for connection control shown by a dashed line. A D channel is provided for transmitting packet information. In addition, between the network termination device 2 and the communication control device 5 via the DLC 3 and the network interface 4, control information for maintenance (testing, etc.) is transmitted between the exchange and the M termination device, in addition to the above-mentioned D channel. A C channel for transmitting and receiving data is set up as shown by a two-dot chain line.

Furthermore, between the two communication control devices 5, LSW 6, and LPR 7, there is a 64K
Data links are established as shown in bold lines. In addition,
NW [F4 receives 1. , S
Data link control information, etc. is transmitted between the W 6 and the B channel and the 64 mentioned above.

This communication control device 5 sends and receives control signals to and from each subscriber's telephone 1 via the D channel, and establishes a channel called the C channel with the network termination device 2 to send and receive maintenance data. , further 1. Exchange connection control information between SW 6 and LPR 7 via 64 data links (arbitrary time slots are allocated and used) using common line signaling system (No. 7 signaling system according to CCITT recommendation) It is sent and received by

In the communication control device 5, 50 SD/SCN (Signa
(1) Distributor/5canner) This is a control unit which has a built-in microprocessor sensor (not shown) and is program-controlled by firmware. and.

Transmission/reception of each signal via data link on C channel, D channel, and 64 (setting of control data, etc.)

(including reading status data), and the read data and control data by the C channel are stored in the SD/SCN memory 51. Reference numeral 52 denotes an HD LC control unit that controls the transmission and reception of D channel and 64K data link signals according to HDLC (high level data link control).

FIG. 8 is a diagram showing details of a part of the configuration shown in FIG. 7, and in FIG. 8, 3 to 6 correspond to devices with the same reference numerals as in FIG.

An optical interface 41 in the NVtIIFd is connected to an optical module 42 from which 1. , SW 6 through an optical transmission line. The communication control device 5 has the seventh
A device not shown in the figure, that is, a CPU that performs overall control
53. Direct memory access controller (DMAC)
54. A memory 55 is provided, and a DMAC 54 is an SD/S
It controls the transfer of various control data (data link to the D channel and 64) from the CN control unit 50 to and from the memory.

In addition, the selector 43 of the NWIF 56 is connected to the 2 communication control device 5.
It has a function of looping back signals (all channels B, C, and D) in the down direction from the exchange to the subscriber side (DLCa side) in the up direction according to instructions from the NFIF loop register 56. .

FIG. 9 is a block diagram of the optical interface, and FIG. 10 shows the accommodation of time slots on the optical interface.

The time slots on the optical interface are 32 time slots (TS) from 0 to 31 in total for one subhighway (TS).
S H) consists of 2 total 4 sub-highway SHO~S
It is composed of H3. Each time slot has an 8-bit configuration, and there are 128 time slots (subhighway S
HO to 5H3) constitute one frame, and one frame has a length of 125 μSec. Furthermore, one multiframe is composed of 16 frames.

As shown in Fig. 10, the time slot TSO in each subhighway is a control signal (for Dch) only in the case of SHI.
used for TSI to TS15 and TS17 to TS31
are used for information transmission (Bl, B2). The TS 16 (#0 to #3) of each subhighway is used as a data link to the above 64.

The configuration shown in FIG. 9 for interfacing multiplexed signals having the above-described time slot configuration will be explained.

The frame synchronization establishment unit 410 receives the 8M clock signal from the right optical module and the detected frame clock (F
CK) and the receiver establish synchronization.

The output after the synchronization has been established is supplied to the down counter 412. The down counter counts the clock based on the frame synchronization signal, controls the operation timing in the optical interface control information extraction section 411 and the data/frame clock (FCK) phase adjustment section 413, and outputs control information (data and , for Dch, etc.) and the received data (RData) such as audio. This control information is supplied to the communication control device 5 (FIG. 8).

Further, the up direction signal is controlled by the above 8M clock and down counter 412 to generate an up direction timing control output and optical interface insertion data (control information sent from the communication control device 5). is the optical interface control information insertion section 41
Data such as voice (B channel) generated from the subscriber side and manually inputted to the corresponding time slot position in step 5 is phase-adjusted by the updater phase adjustment unit 416 and sent to the multiplex circuit (
MPX) and is output as an updater to the optical module (42 in FIG. 8) from the up counter 414 together with the transmission frame clock (SFCK).

[Problems to be Solved by the Invention] In the configuration of the conventional example described above, there is a 64-channel interface between the 1 communication control device 5 and the device (LSW6.I, PR7) having a switching mechanism for transmitting and receiving various control information. A K data link is provided, and failure of this data link will have serious consequences. In such a case, Lr'
The R maintenance person returned the data link to 64 within the switch function (LSW) and checked the normality of transmission/reception, and found the cause of the failure.

■Is it inside the switch (LSW)?

■Determine whether it is the device that interfaces to the switch.

At this time, to check the normality within the switch,
Control such as forming a loop of specific time slots is done by LP.
This can be easily executed by a maintenance person inputting a command to R, but it is not possible to control loop formation (return to LSW) on the network interface (4 in Figure 8), especially on the DLC interface and optical interface. (because a loop in LSW was easily possible).

Generally, digital exchanges, especially public network digital exchanges, use LSW6. The switch mechanism side of the LPRl, the NWIF 4 that interfaces with the switch mechanism, and the communication control device each have a redundant configuration.1 For example, the switch mechanism side of the LPRl, and the NWIF 4 and communication control device that interface to the switch mechanism, are configured in a redundant manner. Switching is performed, and various tests can be performed in the standby state. However, due to loop formation within the conventional switch (LSW), it was not possible to detect a failure in the data link 64 within the network interface in the test. When such a communication control device and network interface change from a standby system to an active system, a situation occurs in which a data link cannot be established even if an attempt is made to establish the data link to the 64.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method that enables repeat testing by specifying a data link for control information within an optical interface of a network interface.

[Failure to solve the problem] FIG. 1 is a diagram showing the principle configuration of the present invention.

In FIG. 1, 10 is a network interface (
NWIF), 11 is a D I-C interface, 12 is an optical interface, 120 is a return instruction detection means, 1
Reference numeral 21 represents a designated data link latch means, 122 a switching means, 13 a communication control device (DLCC), 130 a transmitting/receiving unit, and 131 a return instruction storage means.

A large number of subscriber circuits (DLC) are connected to the left side of the network interface 1o in Fig. 1, and L S is connected to the right side of the network interface 1o.
A switch mechanism including W and the like is provided.

The present invention generates a return instruction specifying a data link number for control information from a communication control device, and when the return instruction is input into a specific time slot on the uplink highway of the network I/network interface, the instruction is detected at the optical interface. The data of the corresponding data link is extracted and outputted on the down highway to perform loopback, and one communication control device receives the loopback data to perform a check.

[Operation] The communication control device includes a return instruction storage means 13 containing the link number of one of a plurality of data links for control information.
1, the contents of the return instruction storage means 131 are sent from the transmitting/receiving section 130 when it is desired to perform a return test while the communication control device 3 and the network interface 10 are on standby. At this time, this instruction information is not used for subscriber information, and is manually entered in a specific time slot other than the data link for control information. D.I., C.
At the interface 11, the command output to the -1 Yuri Highway reaches the optical ink face 12, and the command information is detected by the return command detection means 120 which detects the tie J and slot information.

The detection output is supplied to the specified data link latch means 121. designation? - The link crunching means 121 extracts and latches data from the up-highway at the designated data link (tights, slot) timing.

Next, the information latched by the designated data link latch means 121 is selectively output onto the down highway by driving the switching means 122 when a predetermined time slot on the down highway comes. The test result can be obtained by comparing the information returned by the communication system exterior W13 with the transmitted content.

[Example] Fig. 2 shows the configuration of return instruction information of the embodiment, Fig. 3 is a block diagram of the embodiment of the optical interface, Fig. 4 shows the time relationship of each signal, and Fig. 5 shows the optical interface. The sixth figure is a circuit configuration diagram of the main part, and the sixth is a timing chart of the circuit configuration.

A in FIG. 2 shows the bin I configuration of return instruction information consisting of 8 bits. This instruction information is
Among the time slots on the optical interface shown in the figure,
An unused (NO-115E) time slot number may be used. In this example, subhighway 2 (SH2
) shall be used. 3 bits B6 in this command information. By l37BB (these are called Do, Di, D2).

Specifies one of the data links for control information to be looped back.

That is, in the case of accommodating the time slots shown in FIG.
4, the data link is TS16, and there are four links SHO to SH3, and which link is used to form a loop is designated by the four bit configuration shown in B in FIG. 2 by DO to D2.

The other bit configurations of DO to D2 mean an instruction to turn off the loop (release the loop).

To explain using the configuration of FIG. 8, when the test operation by the CPU 53 is started, the return instruction information of one data link is placed in the position corresponding to the specific time slot (TSO, 5H2) of the SD/SCN control unit 50. written. - On the other hand, the CPU 53 also presets the data (known return data) to be sent to the data link 64 in the memory 55, and uses the DMA function to transfer the data to the HD link.
L (J control unit sends it to the SD/SCN control unit 50. These return instruction information and the data link information 64 are sent to the DLC interface 40 of the network interface 4 via the data link 64 at the corresponding time slot. It is multiplexed with information from the subscriber side and sent to the optical interface 41.

FIG. 3 shows the configuration of the embodiment within the optical interface. The configuration shown in FIG. 3 is obtained by adding new devices to the configuration of the conventional example shown in FIG. 9, and the same parts as in the conventional example are given the same reference numerals as in FIG. 9.

FIG. 4 shows the time relationship of each signal input/output to each part of FIG. 3, and its contents will be summarized.

FCK in ① is the frame clock generated in the optical module (42 in Fig. 8), and down data in ② is the data that is input from the switch mechanism CLSW side to the optical module (42 in Fig. 8) and output from there. . This ■ and ■,
■ and ■ are the time axes expanded, respectively, and ■ and ■ are those further expanded. Data is 125 μsec between frames, 16 from frame 0 to frame 15.
The frames constitute a multi-frame (2 msec), and each frame has 128 time slots (TS 0-
TS 127) is provided. ■ is an 8M (megahertz) clock, generated from the optical module,
Each bit (see ■) in each time slot (8 bits) is synchronized with this clock signal. RFCK in ■ is the frame clock on the receiving side, and the D
This is the receive frame clock sent to the LC interface side.

Next, ■ RData is DL from the optical interface.
Received data sent to C interface, [phase] is DL
The 8M (megahertz) clock sent to the C interface and the Tdata (2) are transmission data sent from the DLC interface to the optical interface. Furthermore, 5FCK at @ is the transmission frame clock output from the optical ink interface (41 in Figure 8) to the optical module (42 in Figure 8), and up Data at ■ is the data output from the optical interface to the optical module side. It is.

The basic operation of information transmission in the configuration of the optical interface shown in FIG. 3 is the same as that of the conventional system (FIG. 9).

To explain the configuration related to the return operation, when the up count 414 detects the timing of time slot 0 (TSO) of subhighway S H2 in the signal (up) from the DLC interface side, the return instruction extraction unit 41B is driven to send uplink transmission data (TD
The corresponding time slots (8 hits) are extracted from (data).

At this time, when it is decoded as a bit instructing loop formation as shown in FIG. 2, the instruction is held and the specified data link number 64 is output to the data link latch section 419.

At 64, the data link launch unit 419 determines, based on the count value of the up counter 414, that the designated number 64 is a data link time slot from among the transmission data (TData) shown in (■) in FIG. Once identified, the data for that time slot is latched and held. This launch data is transmitted from the optical module side to D1. ,
Inserted in the down data to the C interface.

That is, the return instruction extraction unit 418 generates an output of a return instruction, and the down counter 4-12 generates an output indicating to the data link time slot 64. The selector 420 is switched and driven from the AND gate 421, and the data held in the data link latch section 419 is transferred to D as received data (RData).
Sent to the LC interface side. In this way, a data link loop (return loop) is performed at 64.

The folded 64 data link time slot is
The SD/S CN control unit 50 of the communication control device 5 receives the data from the DLC interface 40 in FIG. 8, and transmits the HI from there.1. , C control section 52 is manually operated.

The CPU 53 can check whether the return data is normal or abnormal by comparing it with the transmitted data (stored in the memory 55).

FIG. 5 shows the circuit configuration of the main part in the optical interface shown in FIG. 3 above. In FIG. 5, the data frame clock phase stage unit 413. The amplifier phase matching unit 416 is the same circuit as in FIG. 3, and 61 to 64 in FIG. 1 are 6/6 in FIG.
An IK data link crunching section 419 is configured.

The operation shown in FIG. 5 will be explained with reference to the timing chart shown in FIG.

Transmission data (TDat, a) is input, not shown in (2), in synchronization with RFCK (reception frame J clock).

The transmission data is converted into parallel data every 8 bits by a serial/parallel conversion circuit (S/P) 60, and the timing of the 2-fold return instruction (S/P) is
Of the 8 bits input to 'FSO) of H2, the lower three pins are set in the three-stage flip-flop circuit 61. The turn-back instruction latch pulse (timing pulse) supplied from the up counter 414 (FIG. 3) at this time is shown in {circle around (2)} in FIG.

Flip-flop circuit (F/F) 61 3 pins) (D
o, DI, D2) are shown in ■ in Figure 6.

In the example (2), the number of the data link (TS 16 in each sub-highway) = O (time slot 1-16 of sub-highway 0) is specified in 64. These 3 bits are decoded by the decoder 62.

The output corresponding to the link number O is supplied to the coincidence detection circuit 63.

On the other hand, a latch pulse is generated at each time slot 1-ITs16) of the data link at 64 by the up-power link 414 (FIG. 3), and the -number output circuit 63 When the signal is inputted to the input signal and matches the output of the decoder 62, a matching output is generated at TS16 of SHO (pulse of ■) in this example.

It is supplied to the clock terminal CK of the launch circuit 64.

As a result, the 64 data (8 bits) received as TData at that time is set from the serial/parallel conversion circuit 60 to the rande circuit 64 (■ in FIG. 6).

The data sent to the latch circuit 64 is supplied as one input of the selector 420, but is not immediately output. The down counter (412 in FIG. 3) counts the time slots to 41 and generates a data timing output at 4 for each subhighway in the down direction at TS16. A match detection operation with the output link number O is performed, and when a match is obtained, the selector 420 is driven. When the selector 420 is driven, it changes from the state in which it had previously selected data to the 8 data output from the latch circuit 64.
It is switched to select the data of pin 1-, and its output is sent to the communication control device side as RD at a.

Rl of [phase] in Figure 6) a 1. The operations of 'rS16 in a and the loop selector in 2 are performed in frames that are temporally later than the frames 2 to 2 in the figure.

[Effects of the Invention] According to the present invention, loopback (7) is executed in response to an instruction from the communication control device at the optical interface in the network interface of a digital exchange, making it possible to perform a loopback test. failures can be detected early and system reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a configuration of return instruction information in an embodiment, FIG. 3 is a block diagram of an optical interface in an embodiment, and FIG. 4 is a diagram showing the time relationship of each signal. , FIG. 5 is a circuit configuration diagram of the main parts in the optical interface, FIG. 6 is a timing chart of the circuit configuration, FIG. FIG. 9 is a diagram showing details of a part of the configuration shown in the figure, and FIG. 9 is a diagram showing the configuration of the optical interface, and FIG. 10 is a diagram showing accommodation of time slots on the optical interface. In Figure 1. 10: Network interface (NWIF) 11
: DLC interface (DLCIF) 12: Optical interface 0: Return instruction detection means 1: Specified data link latch means 2: Switching means: Communication control device (DLCC) 0: Transmission/reception unit 1: Return instruction storage means

Claims (1)

[Claims] In a loopback method using a communication control device of a digital exchange connected to a network interface provided between a plurality of subscriber circuits and a switch mechanism, the communication control device includes a loopback system that includes a data link number for control information. The instruction is inserted into a specific time slot in the uplink multiplexed signal, and the optical interface facing the switch mechanism in the network interface extracts the loopback instruction information of the specific time slot using the loopback instruction detection means, and then connects the specified data link. A return method using a communication control device of a digital exchange, characterized in that data of a number is stored in an instruction data link latch means, and the data of the latch means is selectively outputted to a corresponding time slot in a downlink multiplexed signal.