JPH041420B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a disk rotation speed control device for controlling the rotation speed of a disk used in, for example, an optical video disk player.

(b) Conventional technology In optical video discs, the recorded information is FM.
It is modulated and recorded on the disk, and during playback, the signal extracted by pickup is FM demodulated and the information signal is played back. Further, the rotational speed of the disk is controlled by separating the reproduction synchronization signal from the reproduction information signal and passing it through a phase control loop that compares the phase of this signal with a reference signal. Therefore, a desired rotational speed can be obtained depending on the pickup playback position even for a disk with a constant linear velocity as well as a constant angular velocity.

By the way, when the rotation of the disk is unstable, for example when starting the spindle motor that rotates the disk, or immediately after a track jump to obtain a still image, the playback synchronization signal deviates from the normal frequency, so the above-mentioned The phase control loop takes a long time to reach the desired rotation speed.

Therefore, Japanese Patent Application Laid-open No. 58-37875 (G11B19/2
In 4), the period of H level or L level in the synchronized portion of the reproduced signal is counted by a clock pulse, and based on this counted value, a speed up signal or speed down signal is generated to increase the rotation speed of the disk, Furthermore, an output corresponding to the amount of radial movement of the pick-up with respect to the center of rotation of the disk is outputted by a potentiometer, and the aforementioned speed-up signal or speed-down signal is added to the control signal for controlling the spindle motor, which is inversely proportional to this output. A technique has been disclosed that realizes speed control of a spindle motor based on the radial movement amount of a pickup and the pulse width of a synchronization portion of a reproduction signal without using a phase control loop.

(c) Problems to be Solved by the Invention In the above-mentioned conventional technology, only a read signal that is inversely proportional to the radius from the rotation center of the disk to the read position is extracted and this read position signal is supplied to the spindle motor. Rotation control is performed to maintain a constant linear velocity, and speed-up and speed-down signals are added from the playback signal for more precise control, so a means of indicating the position information of the pick-up, such as a potentiometer, is essential. becomes.

(d) Means for Solving the Problems The present invention provides for a pulse width measuring means for measuring the pulse width of a reproduction synchronizing signal as a digital value and a voltage converting means for converting the input digital value into a voltage value. counting down based on a synchronous first counter clock substantially equal to a regular synchronous signal;
When the input value is larger than the output countdown value, the held contents are updated by the input value, and the count-up is performed based on the second counter clock, which has a longer period than the first counter clock. and an up counter whose held contents are updated with the input value when the input value is smaller than the count up value, are arranged in series, and the rotational speed of the disk is controlled by the output of the voltage conversion means. .

(E) Effect Since the present invention is configured as described above, the pulse width of the reproduction synchronization signal is counted, the rotational speed of the disk is detected while ignoring instantaneous noise components, and this detection output is converted into a voltage value. This makes it possible to directly control the rotational speed of the spindle motor.

(F) Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram of the entire embodiment.

In FIG. 1, reference numeral 1 denotes an optical video disk, on which video or audio signals are recorded spirally at a constant linear velocity. 2 is an optical pickup (reproduction means) that irradiates the disk 1 with a laser beam and reads recorded information from the reflected light;
3 is a spindle motor (disk rotation motor) that rotates the disk 1 through a turntable (not shown), 4 is a preamplifier that amplifies the signal read by the pickup 2 to a predetermined level, and 5 is the amplified signal. FM demodulate
FM demodulation circuit, 6 is a signal processing circuit that processes the FM demodulated playback signal and derives the video and audio signals to the output terminal (OUT), 7 is a composite synchronization signal that detects the composite synchronization signal from the FM demodulation circuit 5 output Detection circuit (synchronization signal detection means), 8 is a phase synchronization circuit that separates only the horizontal synchronization signal from the composite synchronization signal and generates a signal that is synchronized with the horizontal synchronization signal in both frequency and phase; 10 is a phase synchronization circuit that generates various reference signals; 11 is a phase comparison circuit that compares the phase of the output of the phase synchronization circuit 8 and the reference signal; 9 is a phase comparison circuit that compares the phase of the output of the phase synchronization circuit 8 and the reference signal; 9 is a phase comparison circuit that detects when the synchronization signal is greatly disturbed when the spindle motor 3 itself is started or immediately after the pickup 2 has a truck jump; 12 is an output that selects the output of the phase comparison circuit 11 or the output of the speed control circuit 9 and supplies it to the driver 13 for driving the spindle motor 3. It is a control circuit.

Next, the operation of the device of this embodiment will be explained.

First, the disk 1 is irradiated with a laser beam from the pickup 2 and the beam is focused. Next, a preset DC voltage (initial voltage) is applied to the spindle motor 3 to forcibly accelerate the rotation of the disk 1. Increase the speed to a speed that allows FM demodulation, which will be described later. Then, the laser beam emitted from the pickup 2 is reflected by the disk 1 and returns to the pickup 2, where it is photoelectrically converted by the built-in photo sensor, and the converted output is amplified by the preamplifier 4 and sent to the FM demodulation circuit 5. Supplied. Here, the FM demodulated signal does not become a normal video or audio signal because the reproduced composite synchronization signal contained therein does not reach the predetermined frequency and does not match the reference signal of the reference signal generation circuit 10 in phase. Not yet. Therefore,
First of all, the FM demodulated signal is input to the composite sync signal detection circuit 7, where the reproduced composite sync signal is separated and supplied to the speed control circuit 9.

The speed control circuit 9 will now be described in detail with reference to the circuit block diagram of FIG. 2 and the waveform diagram of FIG.

The composite synchronization signal (a in FIG. 3) from the composite synchronization signal detection circuit 7 is inputted to the pulse generation circuit 21 via the input terminal 20. This pulse generation circuit 2
1, as shown in FIG. 3, a first timing signal d is generated with a certain period (t1) delay in response to the fall of the composite synchronization signal, and a second timing signal d is generated in synchronization with the fall of the first timing signal d. 2 timing signal e,
A shaped composite synchronization signal whose waveform is shaped as shown in FIG. 3c so as to be synchronized with the reference clock b from the oscillator 22 is output. Note that both the first and second timing signals d and e are signals synchronized with the reference clock b. The second timing signal e and the shaped composite synchronization signal c are input to a counter (pulse width measuring means) 23.

The counter 23 counts the reference clock while the shaped composite synchronization signal c is at H level as shown in FIG. 3F, and is reset by the second timing signal e. Therefore, each shaped composite synchronization signal c
The pulse width of is counted based on the reference clock and output as pulse width data (digital value).
The signals are sequentially input to the latch circuit 24.

The latch circuit 24 inputs and holds the pulse width data of the counter 23 using the first timing signal d as a latch timing pulse, and this latch circuit 24 latches the pulse width data of each shaped composite synchronization signal c. be done.

This latch output pulse width data is input to a down counter 25 to remove extremely small values. That is, the down counter 25 is a first counter whose frequency is slightly longer than the period (1/ _H ) ( _H : horizontal scanning frequency) of the regular horizontal synchronizing signal by dividing the reference clock b by the first frequency dividing circuit 26. clock
Based on CL1, pulse width data, which is input data, is counted down. Also, the first comparison circuit 27
compares the pulse width data with the countdown value of the down counter 25, and outputs an H level output when the pulse width data is larger than the countdown value, and the load pulse generation circuit 28 outputs a load pulse when this comparison output is at the H level. The pulse width data is allowed to be input to the down counter 25.

For example, when the pulse width data of the shaped composite synchronization signal changes from "100" → "110" → "30" → "115" → "100" is initially held in the down counter 25, and the pulse width data is slightly smaller than 1/ _H . The first comparator circuit 27 compares the count value "99" with the next latch output "110" and counts down from "100" to "99" based on the first counter clock CL1 in a long period. Since the output is large, an H level comparison output is issued, and the load pulse generation circuit 28 issues a load pulse. In response to this, the pulse width data of "110", which is the next latch output, is input to the down counter 25, and the down After the content held in the counter 25 is updated, the countdown continues from "110" to "109". The first comparison circuit 27 continues to output this countdown value "109" and the next latch output "30".
However, since the countdown value is larger, no load pulse is generated, and the content held in the down counter 25 is not updated to "30" but "109".
→ The countdown continues as "108", and if the latch output becomes larger than this countdown value in the same way, the latch output will cause the down counter 25 to rise.
The content of is updated, and if it is small, the countdown continues.

Therefore, this down counter 25 holds the longest pulse width data, and as a result, this operation results in an equivalent pulse with a shorter period than the regular horizontal synchronization signal (horizontal synchronization in the composite synchronization signal). (included with the signal) and horizontal synchronization signals with abnormally small pulse widths that occur when the rotational speed is extremely increased in an unstable state. In addition, in the above example, if the rotation speed of the spindle motor is higher than normal, the countdown value does not necessarily decrease from "100" to "99" or from "109" to "108", but from "100" to "108". It is possible that it may remain "109".

Next, the output of the down counter 25 is input to an up counter 29 to remove extremely large values from the pulse width data. That is, the frequency of the first counter clock CL1 is divided by the second frequency dividing circuit 30 to twice (or may be 2 to 4 times) the period (1/ _H ) of the regular horizontal synchronizing signal, and the frequency of the first counter clock CL1 is divided by the second frequency dividing circuit 30. CL2 becomes the clock input of the up counter 29, and the second comparison circuit 30 compares the output of the down counter 25 and the output of the up counter 29, and when the output of the down counter 25 is smaller than the output of the up counter 29, the comparison output is at H level. is supplied to the load pulse generation circuit 31. Load pulse creation circuit 31
emits a load pulse when this comparison output is at H level, allowing input of the down counter 25 output to the up counter 29.

For example, if the down counter 25 removes an extremely small value in the pulse width data and the output changes from "140" → "138" → "300" → "142" →..., the up counter is used for the time being. The value "140" is input to 29, and the second counter clock
Based on CL2, the count is increased from "140" to "141". Furthermore, the second comparison circuit 30 compares this count up value "141" with the next down counter 2.
5 output "138" is compared, and since the count up value is larger, a load pulse is generated from the load pulse generation circuit 31, and the contents held in the up counter 29 are updated by the output of the down counter 25. It becomes "138". Next, this "138"
is counted up and changes from "138" to "139", but the second comparison circuit 30 counts up the next down counter 2.
However, since the count up value is smaller, no load pulse is generated, and the down counter 2, which is ``300'', is compared.
Input to the 5-output up counter 29 is blocked. Therefore, the value of the up counter 29 is not updated and continues counting up from "139" to "140". Thereafter, the up counter 29 is controlled in the same manner based on the comparison result of the second comparison circuit 30, and as a result, "141" → "139" → "140" →
The output of the up counter 29 changes from "143" to.... In the above example, the up counter 29 changes from "139" to "140" each time the pulse width data changes.
However, it goes without saying that it is possible to change the amount of increase by appropriately setting the frequency of the reference clock. In addition, the first and second comparison circuits 27 and 30 always compare two inputs, but the load pulse generation circuit 2
8 and 31 generate a load pulse only during the period when the second timing signal e is at H level. Therefore, the up counter 29 holds the smallest pulse width data from which extremely small ones have already been removed by the down counter 25, and this operation causes the rotation of the spindle motor 3 to become unstable and extremely small. The horizontal synchronization signal when the rotation speed is slow and the horizontal synchronization signal with a long period when dropout occurs are removed.

The pulse width data from which abnormal values have been removed after passing through the down counter 25 and up counter 29 is converted into a voltage value by a voltage conversion circuit (voltage conversion means) 32 and output to an output terminal 33. That is, when the spindle motor 3 has not reached the desired rotational speed, the pulse width data has a larger value than the pulse width of the regular composite synchronization signal, and is output as a high voltage value. Further, when the rotation speed is higher than the desired rotation speed, the pulse width data becomes a value smaller than the normal pulse width, and this is output as a low voltage value.

The output of this speed control circuit 9 is supplied to the driver 13 via the output control circuit 12, and when the voltage is high, the spindle motor 3 is made slower, and when the voltage is low, the spindle motor 3 is made faster. The drive is controlled.

When the spindle motor 3 is brought to approximately the desired rotational speed by the speed servo loop composed of the composite synchronization signal detection circuit 7 and the speed control circuit 9,
The phase servo loop formed by the phase synchronization circuit 8 and the phase comparison circuit 11 begins to function. That is, the composite synchronization signal detected by the composite synchronization signal detection circuit 7 is supplied to the speed control circuit 9 and simultaneously to the phase synchronization circuit 8, and the reproduced horizontal synchronization signal is separated from the phase synchronization signal 8. , generates a signal that is synchronized in both frequency and phase with this reproduced horizontal synchronizing signal, and functions to supplement the missing reproduced horizontal synchronizing signal if it is missing due to dropout. The output of this phase synchronization circuit 8 and a reference signal whose frequency is equal to the regular horizontal scanning frequency ( _H ) generated by the oscillation of the crystal pendulum are connected to the phase comparator circuit 11.
The phases are compared, and if the error is within a predetermined level range, the output of the phase comparison circuit 11, that is, the error signal is supplied to the driver 13 via the output control circuit 12, and the spindle motor 3 is driven. During this time, the output of the speed control circuit 9 is blocked by the output control circuit 12 from passing through. Furthermore, when performing special playback, if the frequency and phase of the reproduced horizontal synchronizing signal deviate greatly from the reference signal, such as immediately after the track jump of the pickup 2, the error signal from the phase comparison circuit 11 exceeds a predetermined level range, and the speed The output of the control circuit 9 is preferentially outputted from the output control circuit 12 to control the rotation of the spindle motor 3.

Although this embodiment has been explained using an optical video disk player as an example, it is not limited to this example, and can be applied to compact disks, floppy disks, VTRs, etc.
Any information reading device may be used as long as it reads information by detecting a synchronization signal from an information recording medium and controlling the speed of a device that drives the information recording medium. Furthermore, it goes without saying that the configuration of the apparatus of this embodiment can be processed using software.

(G) Effects of the Invention As described above, according to the present invention, there are composite synchronization signals that have a period significantly shorter than the original horizontal synchronization signal, such as equivalent pulses, and those whose period is significantly shorter than the original horizontal synchronization signal due to dropout. By removing the longer length, it becomes possible to control the rotational speed of the disk based on the horizontal synchronization signal extracted.

[Brief explanation of drawings]

The drawings all relate to one embodiment of the present invention; FIG. 1 is an overall circuit block diagram, FIG. 2 is a main circuit block diagram, and FIG. 3 is a waveform diagram. DESCRIPTION OF SYMBOLS 1...Disk, 2...Pickup (reproduction means), 3...Spindle motor (disk rotation motor), 7...Composite synchronous signal detection circuit (synchronous signal detection means), 9...Speed control circuit, 23... Counter (pulse width measuring means), 25... Down counter, 29... Up counter, 32... Voltage conversion circuit (voltage conversion means).

Claims (1)

[Scope of Claims] 1. A disk on which an information signal is recorded on a spiral track, a reproduction means for reproducing the information signal from the disk, and a synchronization signal detection means for detecting a reproduction synchronization signal included in the information signal. , a pulse width measuring means for measuring the pulse width of the reproduction synchronization signal as a digital value, a voltage converting means for converting the input signal of the digital value into a voltage value, and a disk rotating motor driven by the output of the voltage converting means. a down counter that counts down based on a first counter clock having a period substantially equal to the regular synchronization signal, and whose held contents are updated with the input value when the input value is larger than the countdown value; an up counter that counts up based on a second counter clock having a longer period than the first counter clock, and whose held contents are updated with the input value when the input value is smaller than the count up value; A disk rotation speed control device, characterized in that the device is arranged in series between a pulse width measuring means and the voltage converting means.